Move cpu_exec_init() call from instance_init to realize. This allows
any failures from cpu_exec_init() to be handled appropriately.
Correspondingly move cpu_exec_exit() call from instance_finalize
to unrealize.
Signed-off-by: Bharata B Rao
---
target-ppc/translate_init.c | 15 +++
1
Add an Error argument to cpu_exec_init() to let users collect the
error. Change all callers to currently pass NULL error argument. This change
is needed for the following reasons:
- A subsequent commit changes the CPU enumeration logic in cpu_exec_init()
resulting in cpu_exec_init() to fail if c
XICS is setup for each CPU during initialization. Provide a routine
to undo the same when CPU is unplugged.
This allows reboot of a VM that has undergone CPU hotplug and unplug
to work correctly.
Signed-off-by: Bharata B Rao
Reviewed-by: David Gibson
---
hw/intc/xics.c| 12
Currently CPUState.cpu_index is monotonically increasing and a newly
created CPU always gets the next higher index. The next available
index is calculated by counting the existing number of CPUs. This is
fine as long as we only add CPUs, but there are architectures which
are starting to support CPU
Signed-off-by: Bharata B Rao
Signed-off-by: Andreas Färber
---
hw/ppc/Makefile.objs| 1 +
hw/ppc/cpu-core.c | 46
hw/ppc/cpu-socket.c | 47 +
include/hw/ppc/cpu-core.h | 32 +
Support hot removal of CPU for sPAPR guests by sending the hot unplug
notification to the guest via EPOW interrupt. Release the vCPU object
after CPU hot unplug so that vCPU fd can be parked and reused.
Signed-off-by: Bharata B Rao
---
hw/ppc/spapr.c | 101 ++
Add CPU hotplug handler to spapr machine class and let the plug handler
initialize spapr CPU specific initialization bits for a realized CPU.
This lets CPU boot path and hotplug path to share as much code as possible.
Signed-off-by: Bharata B Rao
Reviewed-by: David Gibson
---
hw/ppc/spapr.c | 2
From: Andreas Färber
Signed-off-by: Andreas Färber
Signed-off-by: Bharata B Rao
---
hw/cpu/Makefile.objs| 2 +-
hw/cpu/socket.c | 21 +
include/hw/cpu/socket.h | 14 ++
3 files changed, 36 insertions(+), 1 deletion(-)
create mode 100644 hw/cpu/sock
Support CPU hotplug via device-add command. Set up device tree
entries for the hotplugged CPU core and use the exising EPOW event
infrastructure to send CPU hotplug notification to the guest.
Also support cold plugged CPUs that are specified by -device option
on cmdline.
Signed-off-by: Bharata B
ppc machine init functions create individual CPU threads. Change this
for sPAPR by switching to socket creation. CPUs are created recursively
by socket and core instance init routines.
TODO: Switching to socket level CPU creation is done only for sPAPR
target now.
Signed-off-by: Bharata B Rao
--
Factor out bits of sPAPR specific CPU initialization code into
a separate routine so that it can be called from CPU hotplug
path too.
Signed-off-by: Bharata B Rao
Reviewed-by: David Gibson
---
hw/ppc/spapr.c | 54 +-
1 file changed, 29 inserti
Keep cpu_model field in MachineState uptodate so that it can be used
from the CPU hotplug path.
Signed-off-by: Bharata B Rao
Reviewed-by: David Gibson
---
hw/ppc/mac_newworld.c | 10 +-
hw/ppc/mac_oldworld.c | 7 +++
hw/ppc/ppc440_bamboo.c | 7 +++
hw/ppc/prep.c |
Add support for ibm,lrdr-capacity since this is needed by the guest
kernel to know about the possible hot-pluggable CPUs and Memory. With
this, pseries kernels will start reporting correct maxcpus in
/sys/devices/system/cpu/possible.
Define minimum hotpluggable memory size as 256MB and start stori
Reorganize CPU device tree generation code so that it be reused from
hotplug path. CPU dt entries are now generated from spapr_finalize_fdt()
instead of spapr_create_fdt_skel().
Note: This is how the split-up looks like now:
Boot path
-
spapr_finalize_fdt
spapr_populate_cpus_dt_node
sp
Use max_cpus instead of smp_cpus when intializating xics system. Also
report max_cpus in ibm,interrupt-server-ranges device tree property of
interrupt controller node.
Signed-off-by: Bharata B Rao
Reviewed-by: David Gibson
---
hw/ppc/spapr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletion
Advertise CPU DR-capability to the guest via device tree.
Signed-off-by: Bharata B Rao
Signed-off-by: Michael Roth
[spapr_drc_reset implementation]
---
hw/ppc/spapr.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.
From: Michael Roth
Introduce an sPAPRMachineClass sub-class of MachineClass to
handle sPAPR-specific machine configuration properties.
The 'dr_phb[cpu,lmb]_enabled' field of that class can be set as
part of machine-specific init code, and is then propagated
to sPAPREnvironment to conditional ena
This is v3 of the CPU and Memory hotplug patches for PowerPC sPAPR.
- CPU hotplug implementation here is based on device_add command and has
nothing to do with the existing cpu-add QEMU monitor command.
(qemu) device_add powerpc64-cpu-socket,id=sock1
(qemu) device_del sock1
- This version ad
On 04/16/2015 08:07 PM, Thomas Huth wrote:
Am Sat, 11 Apr 2015 01:24:36 +1000
schrieb Alexey Kardashevskiy :
This makes use of the new "memory registering" feature. The idea is
to provide the userspace ability to notify the host kernel about pages
which are going to be used for DMA. Having this
On 04/24/2015 10:01 AM, Fam Zheng wrote:
> On Thu, 04/23 14:23, Paolo Bonzini wrote:
>>
>>
>> On 23/04/2015 14:19, Dr. David Alan Gilbert wrote:
> So that means the bdrv_start_replication and bdrv_stop_replication
> callbacks are more or less redundant, at least on the primary?
>
>
The thing I am trying to achieve is to get the data and guest physical
address of every guest memory access, so I need to known which API can be
used to do the address transform.
Thanks a lot.
2015-04-23 22:03 GMT+08:00 Peter Maydell :
> On 23 April 2015 at 14:56, Wenjie Liu wrote:
> > Can anyb
On Thu, 04/23 14:23, Paolo Bonzini wrote:
>
>
> On 23/04/2015 14:19, Dr. David Alan Gilbert wrote:
> >> > So that means the bdrv_start_replication and bdrv_stop_replication
> >> > callbacks are more or less redundant, at least on the primary?
> >> >
> >> > In fact, who calls them? Certainly not
On Thu, Apr 23, 2015 at 11:16 AM, Peter Maydell
wrote:
> On 23 March 2015 at 11:05, Peter Crosthwaite
> wrote:
>> Use SMC PSCI, with the standard policy of secondaries starting in
>> power-off.
>>
>> Reviewed-by: Alistair Francis
>> Signed-off-by: Peter Crosthwaite
>> ---
>> changed since v1:
>
On Thu, Apr 23, 2015 at 11:15 AM, Peter Maydell
wrote:
> On 23 March 2015 at 11:05, Peter Crosthwaite
> wrote:
>> Using standard ARM bootloader.
>
> Commit msg, etc.
>
>> Signed-off-by: Peter Crosthwaite
>> ---
>> hw/arm/xlnx-ep108.c | 8
>> 1 file changed, 8 insertions(+)
>>
>> diff -
On Thu, Apr 23, 2015 at 11:12 AM, Peter Maydell
wrote:
> On 23 March 2015 at 11:05, Peter Crosthwaite
> wrote:
>> Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model.
>>
>> Signed-off-by: Peter Crosthwaite
>> ---
>> changed since v1:
>> Add ram size clamps and warnings
>>
>> hw/ar
On Thu, Apr 23, 2015 at 10:59 AM, Peter Maydell
wrote:
> On 23 March 2015 at 11:05, Peter Crosthwaite
> wrote:
>> In preparation for migrating the state struct and type cast macro to a public
>> header. The acronym "UART" on it's own is not specific enough to be used in a
>> more global namespace
On Thu, Apr 23, 2015 at 11:00 AM, Peter Maydell
wrote:
> On 23 March 2015 at 11:05, Peter Crosthwaite
> wrote:
>> To allow using the device with modern SoC programming conventions. The
>> state struct needs to be visible to embed the device in SoC containers.
>>
>> Reviewed-by: Alistair Francis
On Thu, Apr 23, 2015 at 10:52 AM, Peter Maydell
wrote:
> On 23 March 2015 at 11:05, Peter Crosthwaite
> wrote:
>> There are 4x Cadence GEMs in ZynqMP. Add them.
>>
>> Signed-off-by: Peter Crosthwaite
>
> Reviewed-by: Peter Maydell
Thanks.
> (other than the use of that error-check macro...)
>
On Thu, Apr 23, 2015 at 10:51 AM, Peter Maydell
wrote:
> On 23 March 2015 at 11:05, Peter Crosthwaite
> wrote:
>> To allow using the device with modern SoC programming conventions. The
>> state struct needs to be visible to embed the device in SoC containers.
>>
>> Reviewed-by: Alistair Francis
On Sun, Mar 29, 2015 at 6:29 PM, Alistair Francis wrote:
> On Mon, Mar 23, 2015 at 9:05 PM, Peter Crosthwaite
> wrote:
>> Connect the GPIO outputs from the individual CPUs for the timers to the
>> GIC.
>>
>> Signed-off-by: Peter Crosthwaite
>> ---
>> hw/arm/xlnx-zynqmp.c | 16
>
On Thu, Apr 23, 2015 at 10:45 AM, Peter Maydell
wrote:
> On 23 March 2015 at 11:05, Peter Crosthwaite
> wrote:
>> And connect IRQ outputs to the CPUs.
>
> Can you make sure the body of the commit message
> makes sense when read as a standalone text without
> the subject line, please?
>
Fixed.
R
On Thu, Apr 23, 2015 at 05:32:33PM +1000, David Gibson wrote:
> On Tue, Apr 07, 2015 at 02:43:43PM +0200, Christian Borntraeger wrote:
> > We had a call and I was asked to write a summary about our conclusion.
> >
> > The more I wrote, there more I became uncertain if we really came to a
> > conc
On 04/23/2015 04:57 PM, miny...@acm.org wrote:
> The major changes from last time are:
That says this series should probably be named v2 (git
format-patch/send-email -v2) or later, as part of the subject line. If
the previous version is more than a couple weeks ago, it's also nice
(but not require
On 04/23/2015 06:46 AM, Kashyap Chamarthy wrote:
> Although the canonical source of reference for QMP commands is
> qapi-schema.json, for consistency's sake, update qmp-commands.hx to
> state the list of supported transactionable operations, namely:
>
> drive-backup
> blockdev-backup
>
From: Corey Minyard
Signed-off-by: Corey Minyard
---
tests/bios-tables-test.c | 112 ---
1 file changed, 107 insertions(+), 5 deletions(-)
diff --git a/tests/bios-tables-test.c b/tests/bios-tables-test.c
index 735ac61..35d20fc 100644
--- a/tests/bios
From: Corey Minyard
Use the new ACPI table construction tools to create an ACPI
entry for IPMI.
Signed-off-by: Corey Minyard
---
hw/ipmi/Makefile.objs | 1 +
hw/ipmi/ipmi_acpi.c | 122 ++
hw/ipmi/isa_ipmi.c| 4 ++
3 files changed, 127 i
From: Corey Minyard
This is the same place that the ACPI SSDT table gets added, so that
devices can add themselves to the SMBIOS table.
Signed-off-by: Corey Minyard
---
hw/i386/pc.c | 35 ++-
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/hw/i38
From: Corey Minyard
Some devices, like IPMI, need to add ACPI table entries to report
their presence. Add a method for adding these entries.
Signed-off-by: Corey Minyard
---
hw/acpi/Makefile.objs | 1 +
hw/acpi/acpi-dev-tables.c | 80 ++
From: Corey Minyard
Add an IPMI table entry to the SMBIOS.
Signed-off-by: Corey Minyard
---
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/ipmi/Makefile.objs | 1 +
hw/ipmi/ipmi_smbios.c | 89 +
From: Corey Minyard
There was no way to directly add a table entry to the SMBIOS table,
even though the BIOS supports this. So add a function to do this.
This is in preparation for the IPMI handler adding it's SMBIOS table
entry.
Signed-off-by: Corey Minyard
---
hw/i386/smbios.c | 153
From: Corey Minyard
This provides a minimal local BMC, basically enough to comply with the
spec and provide a complete watchdog timer (including a sensor, SDR,
and event).
Signed-off-by: Corey Minyard
---
default-configs/i386-softmmu.mak |1 +
default-configs/x86_64-softmmu.mak |1 +
From: Corey Minyard
Add a way for IPMI devices to register their firmware information
with the IPMI subsystem so that various firmware entities can pull
that information later for adding to firmware tables.
Signed-off-by: Corey Minyard
---
hw/ipmi/ipmi.c | 25 +
hw/ipmi
From: Corey Minyard
Test the KCS interface with a local BMC and a BT interface with an
external BMC.
Signed-off-by: Corey Minyard
---
tests/Makefile| 4 +
tests/ipmi-bt-test.c | 440 ++
tests/ipmi-kcs-test.c | 294 +
From: Corey Minyard
Signed-off-by: Corey Minyard io_length = 3;
memory_region_init_io(&s->io, NULL, &ipmi_bt_io_ops, bt, "ipmi-bt", 3);
+vmstate_register(NULL, 0, &vmstate_ipmi_bt, bt);
}
static void ipmi_bt_class_init(ObjectClass *klass, void *data)
diff --git a/hw/ipmi/ipmi_exter
From: Corey Minyard
This provides the simulation of the BT hardware interface for
IPMI.
Signed-off-by: Corey Minyard
---
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/ipmi/Makefile.objs | 1 +
hw/ipmi/ipmi_bt.c | 374
From: Corey Minyard
Add some basic documentation for the IPMI device.
Signed-off-by: Corey Minyard
---
qemu-options.hx | 38 ++
1 file changed, 38 insertions(+)
diff --git a/qemu-options.hx b/qemu-options.hx
index 319d971..598c631 100644
--- a/qemu-options.
From: Corey Minyard
This adds an interface for IPMI that connects to a remote
BMC over a chardev (generally a TCP socket). The OpenIPMI
lanserv simulator describes this interface, see that for
interface details.
Signed-off-by: Corey Minyard
---
default-configs/i386-softmmu.mak | 1 +
defa
From: Corey Minyard
This provides the base infrastructure to tie IPMI low-level
interfaces into a PC ISA bus.
Signed-off-by: Corey Minyard
---
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/ipmi/Makefile.objs | 1 +
hw/ipmi/isa_ipmi.c
From: Corey Minyard
This provides the simulation of the KCS hardware interface.
Signed-off-by: Corey Minyard
---
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/ipmi/Makefile.objs | 1 +
hw/ipmi/ipmi_kcs.c | 337
From: Corey Minyard
Add the basic IPMI types and infrastructure to QEMU. Low-level
interfaces and simulation interfaces will register with this; it's
kind of the go-between to tie them together.
Signed-off-by: Corey Minyard
---
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_6
The major changes from last time are:
* Don't use callbacks for adding firmware tables, provide binary
blobs instead.
* Add the SSDT as a separate table.
* Modify the BIOS tests to test for the IPMI tables.
-corey
On 04/22/2015 07:25 PM, Noel Burton-Krahn wrote:
> OK, I've build qemu and openipmi. I'm simulating a system where a
> central control node boots from USB, then uses IPMI to boot a cluster
> of slave nodes and provisions them by tftpboot. If I understand
> correctly, I'll be running one ipmi_sim
On 23 April 2015 at 20:21, Peter Crosthwaite
wrote:
> On Thu, Apr 23, 2015 at 10:42 AM, Peter Maydell
> wrote:
>> On 23 March 2015 at 11:05, Peter Crosthwaite
>> wrote:
>>> --- a/hw/arm/Makefile.objs
>>> +++ b/hw/arm/Makefile.objs
>>> @@ -10,3 +10,4 @@ obj-$(CONFIG_DIGIC) += digic.o
>>> obj-y +
On 04/23/2015 03:18 PM, Eric Blake wrote:
On 04/23/2015 08:41 AM, John Snow wrote:
I know I said "primarily to be difficult" but I was just being
facetious. I didn't find the GPL2+ to be suitable for documentation,
strictly, so I went to read up on the documentation licenses that the
fsf supp
On Thu, Apr 23, 2015 at 10:47 AM, Peter Maydell
wrote:
> On 23 March 2015 at 11:05, Peter Crosthwaite
> wrote:
>> +static void xlnx_zynqmp_init(Object *obj)
>> +{
>> +XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
>> +int i;
>> +
>> +for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
>> +ob
On 04/23/2015 06:55 AM, Kevin Wolf wrote:
> Am 15.04.2015 um 14:56 hat Eric Blake geschrieben:
>> On 04/15/2015 03:16 AM, Alberto Garcia wrote:
>>> On Sat 11 Apr 2015 01:06:58 AM CEST, Eric Blake wrote:
>>>
> +{ 'type': 'SchemaInfoEnum',
> + 'data': { 'values': ['str'] } }
At on
On Thu, Apr 23, 2015 at 10:42 AM, Peter Maydell
wrote:
> On 23 March 2015 at 11:05, Peter Crosthwaite
> wrote:
>> With quad Cortex-A53 CPUs.
>>
>> Signed-off-by: Peter Crosthwaite
>> ---
>> changed since v2:
>> Added [*] to cpu child property name.
>> changed since v1:
>> Add &error_abort to CPU
On 04/23/2015 08:41 AM, John Snow wrote:
> I know I said "primarily to be difficult" but I was just being
> facetious. I didn't find the GPL2+ to be suitable for documentation,
> strictly, so I went to read up on the documentation licenses that the
> fsf support/recommend.
>
> There's the GNU doc
On 04/23/2015 08:14 AM, Radim Krčmář wrote:
> 2015-04-06 17:45-0600, James Sullivan:
>> Added argument to apic_get_delivery_bitmask() for msi_redir_hint,
>> and changed calls to the function accordingly (using 0 as a default
>> value for non-MSI interrupts).
>>
>> Modified the implementation of a
(CCing the PC maintainer, Michael)
On Wed, Apr 22, 2015 at 12:38:10AM +0200, Alexander Graf wrote:
> This patch adds all the boilerplate required to handle a 2.4 machine type
> and compatibility options required on older machines.
>
> Signed-off-by: Alexander Graf
> ---
> hw/i386/pc_piix.c|
On 04/23/2015 07:49 AM, Radim Krčmář wrote:
> 2015-04-06 17:45-0600, James Sullivan:
>> Currently, apic_get_arb_pri() is unimplemented and returns 0.
>>
>> Implemented apic_get_arb_pri() and added two helper functions
>> apic_compare_prio() and apic_lowest_prio() to be used for LAPIC
>> arbitrati
On 23 March 2015 at 11:05, Peter Crosthwaite
wrote:
> There are 2x Cadence UARTs in Zynq MP. Add them.
>
> Reviewed-by: Alistair Francis
> Signed-off-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
thanks
-- PMM
On 23 March 2015 at 11:05, Peter Crosthwaite
wrote:
> Use SMC PSCI, with the standard policy of secondaries starting in
> power-off.
>
> Reviewed-by: Alistair Francis
> Signed-off-by: Peter Crosthwaite
> ---
> changed since v1:
> Add &error_abort to property setter calls
>
> hw/arm/xlnx-zynqmp.
On 23 March 2015 at 11:05, Peter Crosthwaite
wrote:
> Using standard ARM bootloader.
Commit msg, etc.
> Signed-off-by: Peter Crosthwaite
> ---
> hw/arm/xlnx-ep108.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c
> index 6e89456..a86f5
On 23 March 2015 at 11:05, Peter Crosthwaite
wrote:
> Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model.
>
> Signed-off-by: Peter Crosthwaite
> ---
> changed since v1:
> Add ram size clamps and warnings
>
> hw/arm/xlnx-ep108.c | 21 +
> 1 file changed, 21 inse
On 23 March 2015 at 11:05, Peter Crosthwaite
wrote:
> Add a machine model for the Xilinx ZynqMP SoC EP108 board.
>
> Signed-off-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
thanks
-- PMM
On 23 March 2015 at 11:05, Peter Crosthwaite
wrote:
> To allow using the device with modern SoC programming conventions. The
> state struct needs to be visible to embed the device in SoC containers.
>
> Reviewed-by: Alistair Francis
> Signed-off-by: Peter Crosthwaite
Non-standalone commit messa
On 23 March 2015 at 11:05, Peter Crosthwaite
wrote:
> In preparation for migrating the state struct and type cast macro to a public
> header. The acronym "UART" on it's own is not specific enough to be used in a
> more global namespace so preface with "cadence". Fix the capitalisation of
> "uart"
On 23 March 2015 at 11:05, Peter Crosthwaite
wrote:
> There are 4x Cadence GEMs in ZynqMP. Add them.
>
> Signed-off-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
(other than the use of that error-check macro...)
thanks
-- PMM
On 23 March 2015 at 11:05, Peter Crosthwaite
wrote:
> To allow using the device with modern SoC programming conventions. The
> state struct needs to be visible to embed the device in SoC containers.
>
> Reviewed-by: Alistair Francis
> Signed-off-by: Peter Crosthwaite
> ---
> changed since v1:
>
On 23 March 2015 at 11:05, Peter Crosthwaite
wrote:
> In preparation for migrating the state struct and type cast macro to a public
> header. The acronym "GEM" on it's own is not specific enough to be used in a
> more global namespace so preface with "cadence". Fix the capitalisation of
> "gem" in
On 23 March 2015 at 11:05, Peter Crosthwaite
wrote:
> +static void xlnx_zynqmp_init(Object *obj)
> +{
> +XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
> +int i;
> +
> +for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
> +object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
> +
On 23 March 2015 at 11:05, Peter Crosthwaite
wrote:
> And connect IRQ outputs to the CPUs.
Can you make sure the body of the commit message
makes sense when read as a standalone text without
the subject line, please?
Otherwise
Reviewed-by: Peter Maydell
thanks
-- PMM
On 23 March 2015 at 11:05, Peter Crosthwaite
wrote:
> With quad Cortex-A53 CPUs.
>
> Signed-off-by: Peter Crosthwaite
> ---
> changed since v2:
> Added [*] to cpu child property name.
> changed since v1:
> Add &error_abort to CPU child adder call.
>
> default-configs/aarch64-softmmu.mak | 2 +-
Hi Leon,
On 04/23/2015 07:00 AM, Leon Alrae wrote:
> Hi Christopher,
>
> On 09/04/2015 18:57, Peter Maydell wrote:
>> On 9 April 2015 at 18:23, Christopher Covington
>> wrote:
>>> On Fri, Mar 27, 2015 at 12:40 PM, Peter Maydell
>>> wrote:
You need to have the semihosting_enabled check here
On 23 March 2015 at 11:05, Peter Crosthwaite
wrote:
> In preparation for support for Cortex a53. Use "axx" to describe the
> shareable features. Some of the CP15 registers (such as ACTLR) are
> specific to implementation, but we currently just RAZ them so continue
> with that as the policy for all
Well, that's a peculiar commit title. :-)
I guess it's supposed to be "qemu-iotests: s390x: fix test 130"?
On 23.04.2015 04:42, Xiao Guang Chen wrote:
From: Bo Tu
The tests for device type "ide_cd" should only be tested for the pc platform.
The default device id of hard disk on the s390 platf
On 23.04.2015 04:42, Xiao Guang Chen wrote:
From: Bo Tu
Hm, why is Bo Tu the patch author, but doesn't have an S-o-b in the
commit message?
when creating an image qemu-img enable us specifying the size of the
image using -o size=xx options. But when we specify an invalid size
such as a neg
On 04/22/2015 01:20 PM, Dr. David Alan Gilbert wrote:
> * Daniel P. Berrange (berra...@redhat.com) wrote:
>> On Wed, Apr 22, 2015 at 06:12:25PM +0100, Dr. David Alan Gilbert wrote:
>>> * Daniel P. Berrange (berra...@redhat.com) wrote:
On Wed, Apr 22, 2015 at 06:01:56PM +0100, Dr. David Alan Gi
On Thu, Apr 23, 2015 at 10:34:57AM -0400, John Snow wrote:
> The qmp-shell is a little rudimentary, but it can be hacked
> to give us some transactional support without too much difficulty.
>
> (1) Prep.
> (2) Add support for serializing json arrays
> (3) Allow users to use 'single quotes' instead
On 04/23/2015 10:34 AM, John Snow wrote:
The qmp-shell is a little rudimentary, but it can be hacked
to give us some transactional support without too much difficulty.
(1) Prep.
(2) Add support for serializing json arrays
(3) Allow users to use 'single quotes' instead of "double quotes"
(4) Ad
On 23.04.2015 02:04, John Snow wrote:
Use a transaction to request an incremental backup across two drives.
Coerce one of the jobs to fail, and then re-run the transaction.
Verify that no bitmap data was lost due to the partial transaction
failure.
Signed-off-by: John Snow
---
tests/qemu-iot
Alex Bennée writes:
> Frederic Konrad writes:
>
>>
>> Does that makes sense?
>>
>> BTW here is the repository:
>> git clone g...@git.greensocs.com:fkonrad/mttcg.git -b multi_tcg_v4
>
> Is there a non-authenticated read-only http or git:// access to this repo?
I should have done some poking fi
On 23.04.2015 02:04, John Snow wrote:
This patch actually implements the transactional callback system
for the drive_backup action.
(1) We manually pick up a reference to the bitmap if present to allow
its cleanup to be delayed until after all drive_backup jobs launched
by the transact
Frederic Konrad writes:
> On 10/04/2015 18:03, Frederic Konrad wrote:
>> On 30/03/2015 23:46, Peter Maydell wrote:
>>> On 30 March 2015 at 07:52, Mark Burton
>>> wrote:
So - Fred is unwilling to send the patch set as it stands, because
frankly this part is totally broken.
On 23.04.2015 02:04, John Snow wrote:
We'd like to be able to specify the callback given to backup_start
manually in the case of transactions, so split apart qmp_drive_backup
into an implementation and a wrapper.
Switch drive_backup_prepare to use the new wrapper, but don't overload
the callback
On 23.04.2015 02:04, John Snow wrote:
The goal here is to add a new method to transactions that allows
developers to specify a callback that will get invoked only once
all jobs spawned by a transaction are completed, allowing developers
the chance to perform actions conditionally pending complete
On 23.04.2015 02:04, John Snow wrote:
Test simple usage cases for using transactions to create
and synchronize incremental backups.
Signed-off-by: John Snow
---
tests/qemu-iotests/124 | 54 ++
tests/qemu-iotests/124.out | 4 ++--
2 files chan
On 04/23/2015 05:22 PM, Paolo Bonzini wrote:
>
>
> On 23/04/2015 17:08, Eric Auger wrote:
>> int kvm_irqchip_add_irqfd_notifier(KVMState *s, EventNotifier *n,
>> EventNotifier *rn, int virq);
>> int kvm_irqchip_remove_irqfd_notifier(KVMState *s, EventNotifier
On 23/04/2015 17:08, Eric Auger wrote:
> int kvm_irqchip_add_irqfd_notifier(KVMState *s, EventNotifier *n,
> EventNotifier *rn, int virq);
> int kvm_irqchip_remove_irqfd_notifier(KVMState *s, EventNotifier *n, int
> virq);
> +int kvm_irqchip_add_qemuirq_irqf
Hi Baptiste,
Well I need to increase the size of the platform bus mmio and number of
IRQs according to Alex' advice and hence move it after VIRTIO_MMIO for
alignment reason. This is a small change I can carry out by tomorrow.
Then Alex proposed to bind VIRT_MMIO to the platform bus. This sounds a
On 23 April 2015 at 16:00, Greg Bellows wrote:
>
>
> On Thu, Apr 23, 2015 at 9:51 AM, Peter Maydell
> wrote:
>> We should check what the architecture manual says, but I think
>> that in all the trap-WFE cases it says "traps if the CPU
>> would go into a low power state". QEMU *never* goes into a
VFIO platform device needs to setup irqfd but it does not know the
gsi corresponding to the device qemu_irq. This series proposes to
store a hash table in kvm_state using the qemu_irq as key and the gsi
as a value.
kvm_irqchip_set_qemuirq_gsi allows to insert such a pair. The interrupt
controller
The arm_gic_kvm now calls kvm_irqchip_set_qemuirq_gsi to build
the hash table storing qemu_irq/gsi mappings. From that point on
irqfd can be setup directly from the qemu_irq using
kvm_irqchip_add_qemuirq_irqfd_notifier.
Signed-off-by: Eric Auger
---
hw/intc/arm_gic_kvm.c | 5 +
1 file change
The VFIO platform needs to setup irqfd but it does not know the gsi associated
to the sysbus device qemu_irq.
With PCI there is a PCIINTxRoute bus lookup mechanism that enables to
retrieve the gsi from the PCI host controller/bridge pin. The conversion
is implemented by the PCI host controller. Wi
Hi Eric,
Is there anything still blocking this patch ? Can I get the status ?
Thanks,
Baptiste
On Wed, Mar 4, 2015 at 5:18 PM, Eric Auger wrote:
> This patch series enables machvirt to dynamically instantiate sysbus
> devices from command line (using -device option).
>
> All those sysbus devic
On 04/23/2015 04:34 AM, Chen Fan wrote:
>
> On 04/20/2015 06:29 AM, Laine Stump wrote:
>> On 04/17/2015 04:53 AM, Chen Fan wrote:
>>> - on destination side, check whether need to hotplug new NIC
>>> according to specified XML.
>>> usually, we use migrate "--xml" command option to specify the
>
On Thu, Apr 23, 2015 at 9:51 AM, Peter Maydell
wrote:
> On 23 April 2015 at 15:41, Greg Bellows wrote:
> > Ok it sounds like the primary concern is the performance impact of
> > constantly trapping wfe to EL2 (in which case HCR must be set to cause
> > this). Should we still honor EL3 and EL1 t
On 23 April 2015 at 15:41, Greg Bellows wrote:
> Ok it sounds like the primary concern is the performance impact of
> constantly trapping wfe to EL2 (in which case HCR must be set to cause
> this). Should we still honor EL3 and EL1 trapping ofr wfe? In other words
> check if they are the target
On 04/23/2015 09:19 AM, Stefan Hajnoczi wrote:
On Fri, Apr 17, 2015 at 07:49:48PM -0400, John Snow wrote:
===
v6:
===
01: s/underlaying/underlying/
Removed a reference to 'disabled' bitmaps.
Touching up inconsistent list indentation.
Added FreeBSD Documentation License, primari
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