From: Peter Crosthwaite
Assume that when using MULTI arch, the -firmware switch dictates the
software to load on microblaze. A hack until we get generic bootloading
working.
Signed-off-by: Peter Crosthwaite
---
hw/microblaze/boot.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/mic
From: Peter Crosthwaite
The only generic code relying on this is linux-user. Linux user already
has a lot of #ifdef TARGET_ customisation so just define ELF_MACHINE
locally there.
The microblaze bootloader can just pass EM_MICROBLAZE directly, as that
is architecture specific code.
This remove
From: Peter Crosthwaite
Add a Microblaze processor with full system visibility to the machine
model. This emulates a single Microblaze implemented in the Zynq SoC
programmable logic.
Use the standard microblaze bootloader to loader software.
Conditionally compile these components on TARGET_MULT
From: Peter Crosthwaite
Multi-arch platforms may wish to use the ARM bootloader. Don't assert
that all CPUs in the CPU list are ARM.
Signed-off-by: Peter Crosthwaite
---
hw/arm/boot.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
inde
From: Peter Crosthwaite
Device land code that needs cpu.h only needs it for architecture
specific reasons. So include target-microblaze/cpu.h explicitly rather
than the just the one provided by common code.
This prepares support for multi-arch where the common cpu.h will be
minimal and not conta
Move the ARM coprocessor API to a new C file. Two reasons:
1: helper.c is huge and splitting off this self contained piece is a
modularity win.
2: Prepare support for multi-arch where this API is used from system
code but the rest of target-arm will be invisible to system level code.
Signed-off-b
From: Peter Crosthwaite
Linux kernel booting is not yet defined for multi-arch and Microblaze's
DTB loader sometimes gets in the way of elfs. Just disable it for
multi-arch.
Signed-off-by: Peter Crosthwaite
---
hw/microblaze/boot.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/mic
From: Peter Crosthwaite
Device land code that needs cpu.h only needs it for architecture
specific reasons. So include target-arm/cpu.h explicitly rather than
the one provided by common code.
This prepares support for multi-arch where the common cpu.h will be
minimal and not contain any arch spec
Multi-arch conversion consisting of:
* configury
- defining CONFIG_ARCH_MULTI
- adding to MULTI_TARGETS
- enabling disas for MULTI_ARCH
* Converting target-arm to arch-obj-y
* cpu.h
- Compiling out all target-arm private contents
when doing multi-arch build
- Redefining ta
From: Peter Crosthwaite
The only generic code relying on this is linux-user. Linux user already
has a lot of #ifdef TARGET_ customisation so just define ELF_MACHINE
locally there.
The armv7m bootloader can just pass EM_ARM directly, as that
is architecture specific code.
This remove another arc
Move this implementation up to the header so it is visible from system
level code once the architecture is converted to arch-obj-y. Alternative
would be to create init.c in target-arm/hw but this implementation is
trivial enough for static inline.
Signed-off-by: Peter Crosthwaite
---
target-arm/
Create the multi-softmmu build target. The multi-arch build will be
a combination of all softmmu targets that are:
1: also configured for build (as --target-list items)
2: support multi-arch
target-multi will define TARGET_FOO for each supported target. This is
to allow access to these defs from
It does not work in multi-arch as it requires the CPU specific
TARGET_VIRT_ADDR_SPACE_BITS global define. Just use the generic
version that does no masking. If this masking is still needed (??)
then the variable can be virtualised in the CPUState.
Signed-off-by: Peter Crosthwaite
---
disas.c | 1
Not sure as to whether virtualise or not here, just commenting out for
the moment as watchpoints are nor critical to this RFC.
Signed-off-by: Peter Crosthwaite
---
exec.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/exec.c b/exec.c
index 71ec173..200d18b 100644
--- a/exec.c
+++ b/e
This won't work in multi-arch where this service is not provided to
core code. The architecture specific uses of this in monitor.c should
have their functionality migrated out of monitor.c to arch specific
virtualised hooks. For the moment, just get rid of it to enable testing
of multi-arch on plat
Not dealing with this issue as of this RFC. Comments welcome on how to
handle it. It is probably a case that any form of CPU selection is ill
defined in multi-arch. So just a case of #ifndef TARGET_MULTI or
something like that?
Signed-off-by: Peter Crosthwaite
---
cpus.c | 2 ++
1 file changed,
The core code interfaces to translate-all, cpu-tlb and cpu-exec are
virtualised. This prepare support for multi-arch where these modules
are multi-compiled for the different target backends and will need
to co-exist.
The names of functions are not changed. They still have their generic
names and c
Move the architecture agnostic function prototypes for exec.c out of
cputlb.h to exec-all.h. This allows hiding of the arch specific
cputlb.h from exec.c which should be getting close to having no
architecture specifics. Prepares support for multi-arch, which will have
a minimal cpu.h that services
This is almost certainly wrong but it should work for my test case
where TARGET_PAGE_SIZE is cross-arch consistent. This is needed to get
vfio/pci.c to compile due to it's use of HOST_PAGE_ALIGN.
Cc: Alex Williamson
Signed-off-by: Peter Crosthwaite
---
translate-all.c| 4
translate-com
Multi-arch conversion consisting of:
* configury
- defining CONFIG_ARCH_MULTI
- adding to MULTI_TARGETS
- enabling disas for MULTI_ARCH
* Converting target-microblaze to arch-obj-y
* cpu.h
- Compiling out all target-microblaze private contents
when doing multi-arch build
-
This is currently provided by cpu-defs and is a target specific
definition. However, to prepare for multi-arch only the bare minimum
content from cpu-defs.h should be exported to core code. And this is
all we need. So split it to a new header that the target_multi cpu.h
can include to save on havin
These are not Architecture specific in any way so move them out of
cpu-defs.h. tb-hash.h is an appropriate place as a leading user and
their strong relationship to TB hashing and caching.
Signed-off-by: Peter Crosthwaite
---
include/exec/cpu-defs.h | 8
include/exec/tb-hash.h | 8 +
This function has no architecture specific dependencies and should be
callable from core code. Move it to qom/cpu.h.
Signed-off-by: Peter Crosthwaite
---
include/exec/exec-all.h | 21 -
include/qom/cpu.h | 21 +
2 files changed, 21 insertions(+), 21
Not dealing with this problem as of this RFC, but comments on how
to solve it welcome. The approach adopted by this series is to
implement multi-arch as multiple translators, so a single global
TCG profiler is now ill-defined.
Signed-off-by: Peter Crosthwaite
---
monitor.c | 4
1 file chang
This is one of very few things in exec-all with a genuine CPU
architecture dependency. Move these hashing helpers to a new
header to trim exec-all.h down to a near architecture-agnostic
header.
The defs are only used by cpu-exec and translate-all which are both
arch-obj's so the new tb-hash.h has
The goal is to split the functions such that cpu-exec is CPU specific
content, while cpus.c is generic code only. The function interface to
cpu-exec needs to be virtualised to prepare support for multi-arch and
moving these definitions out saves bloating the QOM interface. So
move these definitions
In system mode emulation (at least) this definition has no architecture
specific dependencies. Move it to common code such that common code can
use it (primarily for defining function prototypes).
Signed-off-by: Peter Crosthwaite
---
include/exec/cpu-common.h | 4
include/exec/exec-all.h
These exception indicies are generic and don't have any reliance on the
per-arch cpu.h defs. Move them to cpu-all.h so they can be used by core
code that does not have access to cpu-defs.h.
Signed-off-by: Peter Crosthwaite
---
include/exec/cpu-all.h | 6 ++
include/exec/cpu-defs.h | 6 -
Add a new *obj- category, arch-obj. arch-obj-y will be a subset of the
existing obj-y. The difference, is arch-obj components are usable by
multi-arch builds. That is, following the single-arch target builds, the
already-built arch_obj components for multiple targets can be linked
together to form
Allow subsequent inclusion of cpu-defs.h. This allows including
multiple cpu.h's and each getting the right set of definitions for
its env structure definition. All define symbols are undeffed and
redeffed to the new values.
CPUTLBEntry and CPUIOTLBEntry need to be renamed via #define by
the calle
Create a global list of tcg_exec_init functions that is populated at
startup. Multiple translation engines can register an init function
and all will be called on the master call to tcg_exec_init.
Introduce a new module, translate-common. This is a common-obj for
translation functionality such as
Remove un-needed usages of CPU_GET_ENV by converting the APIs to use
CPUState pointers and retrieving the env_ptr as minimally needed.
FIXME: apply target-foo change pattern to all archs.
Signed-off-by: Peter Crosthwaite
---
cpu-exec.c | 28 +---
cpus.c
** Note: Very different to V1 **
Hi All,
This is target-multi, a system-mode build that can support multiple
cpu-types.
Two architectures are initially converted. Microblaze and ARM. Step
by step conversion in done for each. A microblaze is added to
Xilinx Zynq platform as a test case. This will
Move this function to common code. It has no arch specific
dependencies. Prepares support for multi-arch where the translate-all
interface needs to be virtualised. One less thing to virtualise.
Signed-off-by: Peter Crosthwaite
---
translate-all.c| 30 --
translate
The usages of this define are pure TCG and there is no architecture
specific variation of the value. Localise it to the TCG engine to
remove another architecture agnostic piece from cpu-defs.h.
This follows on from a28177820a868eafda8fab007561cc19f41941f4 where
temp_buf was moved out of the CPU_CO
On Sat, May 30, 2015 at 3:08 PM, aurelio remonda
wrote:
>>> if (op < 4) {
>>> /* Saturating add/subtract. */
>>> +if (!(arm_dc_feature(s, ARM_FEATURE_THUMB_DSP))){
>>> +/* qsub, qadd, qdadd, qdsub are DSP instructions. */
>>> +
>> if (op < 4) {
>> /* Saturating add/subtract. */
>> +if (!(arm_dc_feature(s, ARM_FEATURE_THUMB_DSP))){
>> +/* qsub, qadd, qdadd, qdsub are DSP instructions. */
>> +goto illegal_op;
>> +}
>>
v1 -> v2:
* s/PDRC/CCR/ for clarity and match ICH9 spec
* remove unnecessary OperationRegion for RCRB
Signed-off-by: Paulo Alcantara
---
hw/i386/q35-acpi-dsdt.dsl | 14 ++
tests/acpi-test-data/q35/DSDT | Bin 7666 -> 7723 bytes
2 files changed, 14 insertions(+)
diff --git a
v1 -> v2:
* some cleanup
* added test for TCO_LOCK bit
Signed-off-by: Paulo Alcantara
---
tests/Makefile | 2 +
tests/tco-test.c | 419 +++
2 files changed, 421 insertions(+)
create mode 100644 tests/tco-test.c
diff --git a/tests/Make
This interface provides some registers within a 32-byte range and can be
acessed through PCI-to-LPC bridge interface (PMBASE + 0x60).
It's commonly used as a watchdog timer to detect system lockups through
SMIs that are generated -- if TCO_EN bit is set -- on every timeout. If
NO_REBOOT bit is not
Add related configuration, make files for tilegx. Now, qemu tilegx can
pass building, and finish running "Hello world" static/shared elf64
binary.
Signed-off-by: Chen Gang
---
configure | 2 ++
default-configs/tilegx-linux-user.mak | 1 +
target-tilegx/Makefile.objs
Generate related tcg instructions, and qemu tilegx can finish running
"Hello world". The elf64 binary can be static or shared.
Signed-off-by: Chen Gang
---
target-tilegx/translate.c | 2787 +
1 file changed, 2787 insertions(+)
create mode 100644 targe
The related instructions are exception, cntlz, cnttz, and shufflebytes.
Signed-off-by: Chen Gang
---
target-tilegx/helper.c | 73 ++
target-tilegx/helper.h | 4 +++
2 files changed, 77 insertions(+)
create mode 100644 target-tilegx/helper.c
crea
It implements minimized cpu features for linux-user.
Signed-off-by: Chen Gang
---
target-tilegx/cpu.c | 143 +++
target-tilegx/cpu.h | 171
2 files changed, 314 insertions(+)
create mode 100644 target-t
The related copy is from Linux kernel "arch/tile/include/uapi/arch/
spr_def_64.h".
Signed-off-by: Chen Gang
---
target-tilegx/spr_def_64.h | 216 +
1 file changed, 216 insertions(+)
create mode 100644 target-tilegx/spr_def_64.h
diff --git a/target-ti
Use 'inline' instead of '__inline', and also use 'uint64_t' instead of
"unsigned long long"
Signed-off-by: Chen Gang
---
target-tilegx/opcode_tilegx.h | 220 +-
1 file changed, 110 insertions(+), 110 deletions(-)
diff --git a/target-tilegx/opcode_tilegx.h
It is copied from Linux kernel "arch/tile/include/uapi/arch/
opcode_tilegx.h".
Signed-off-by: Chen Gang
---
target-tilegx/opcode_tilegx.h | 1406 +
1 file changed, 1406 insertions(+)
create mode 100644 target-tilegx/opcode_tilegx.h
diff --git a/target-ti
Some of architectures (e.g. tilegx), several syscall macros are not
supported, so switch them.
Signed-off-by: Chen Gang
---
linux-user/syscall.c | 50 +-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/linux-user/syscall.c b/linux-use
Add main working flow feature, system call processing feature, and elf64
tilegx binary loading feature, based on Linux kernel tilegx 64-bit
implementation.
Signed-off-by: Chen Gang
---
include/elf.h | 2 +
linux-user/elfload.c | 23 +
linux-user/main.c | 236 +
They are based on Linux kernel tilegx architecture for 64 bit binary,
and also based on tilegx ABI reference document, and also reference from
other targets implementations.
Signed-off-by: Chen Gang
---
linux-user/tilegx/syscall.h| 35
linux-user/tilegx/syscall_nr.h | 324 +
It can finish running "Hello world" elf64 binary, and the related test
cases:
- with "--enable-debug", enable assertion with "-g":
./tilegx-linux-user/qemu-tilegx -L /upstream/release-tile
/upstream/release-tile/test/test_shared
./tilegx-linux-user/qemu-tilegx -d all -L /upstream/relea
On Sat, May 30, 2015 at 1:54 PM, Peter Maydell wrote:
> On 30 May 2015 at 21:10, Peter Crosthwaite
> wrote:
>> I think the risu tool is able to do something. A quick look at the
>> readme shows it should have thumb support:
>>
>> https://git.linaro.org/people/peter.maydell/risu.git/blob/HEAD:/RE
On 30 May 2015 at 21:10, Peter Crosthwaite wrote:
> I think the risu tool is able to do something. A quick look at the
> readme shows it should have thumb support:
>
> https://git.linaro.org/people/peter.maydell/risu.git/blob/HEAD:/README
It does rely on the remote end running Linux though, which
On Sat, May 30, 2015 at 3:32 AM, Paolo Bonzini wrote:
>
>
> On 30/05/2015 11:55, Peter Crosthwaite wrote:
>> I think the same is true of NOR.
>
> NOR is sized according to the capacity of its backing file, at least in
> the PC case.
>
So that might be the exception to the rule. I assume that is t
On Sat, May 30, 2015 at 12:27 PM, Liviu Ionescu wrote:
>
> I could not follow the details of this patch, but since it touches the core
> of qemu, are there any tests available to check if these instructions are
> emulated correctly?
>
>
I think the risu tool is able to do something. A quick loo
Le 30/05/2015 21:32, Peter Maydell a écrit :
> On 30 May 2015 at 20:28, Laurent Vivier wrote:
>> Orginal qemu-binfmt-conf.h is only able to write configuration
>> into /proc/sys/fs/binfmt_misc, and the configuration is lost on reboot.
>>
>> This script can configure debian and systemd services t
On 30 May 2015 at 20:28, Laurent Vivier wrote:
> Orginal qemu-binfmt-conf.h is only able to write configuration
> into /proc/sys/fs/binfmt_misc, and the configuration is lost on reboot.
>
> This script can configure debian and systemd services to restore
> configuration on reboot. Moreover, it is
Orginal qemu-binfmt-conf.h is only able to write configuration
into /proc/sys/fs/binfmt_misc, and the configuration is lost on reboot.
This script can configure debian and systemd services to restore
configuration on reboot. Moreover, it is able to manage binfmt
credential and to configure the pat
I could not follow the details of this patch, but since it touches the core of
qemu, are there any tests available to check if these instructions are emulated
correctly?
regards,
Liviu
> On 30 May 2015, at 07:17, Alistair Francis wrote:
>
> I also have a lot better support out of tree, I'm still slowly working
> on upstreaming it (I should have another patch series today).
my implementation is based on the existing Stellaris MCUs, and SysTick was
functional from the very beg
I run qemu in single step mode and user-mode. I want to know where i386
flags are stored after a run of one Translation Block.
If the argument r1 was the same as the extended result register r3+1, we would
overwrite r1 and then use it.
Signed-off-by: Bastian Koppelmann
Message-Id: <1432289758-6250-2-git-send-email-kbast...@mail.uni-paderborn.de>
---
target-tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 de
Signed-off-by: Bastian Koppelmann
Message-Id: <1432289758-6250-4-git-send-email-kbast...@mail.uni-paderborn.de>
---
target-tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 8560d00..8d41239 100644
mu-tricore-upstream.git
tags/pull-tricore-20150530
for you to fetch changes up to 07e15486faf353260431f10e85185372c5036baa:
target-tricore: fix BOL_ST_H_LONGOFF using ld (2015-05-30 16:49:19 +0200)
TriCor
The inversion of the overflow bit as a special case, which was needed for the
madd32_q instructions, does not apply for msub32_q instructions. So remove it.
Signed-off-by: Bastian Koppelmann
Message-Id: <1432289758-6250-3-git-send-email-kbast...@mail.uni-paderborn.de>
---
target-tricore/translat
29.05.2015 21:52, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> The help/man text for
>
> -incoming defer
>
> didn't make it through the merge of the code that implemented it.
>
> Signed-off-by: Dr. David Alan Gilbert
> ---
> qemu-options.hx | 6 +-
> 1 file ch
29.05.2015 08:26, Shannon Zhao wrote:
> From: Shannon Zhao
>
> These are relevant to misusing qemu_allocate_irqs for requesting single
> irq and they cause memory leak. So these patches use qemu_allocate_irq
> for single irq to fix these memory leaks.
>
> PS: These patches are split from my pre
applied to -trivial, thanks!
/mjt
Signed-off-by: Michael Tokarev
---
hw/display/tcx.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/display/tcx.c b/hw/display/tcx.c
index a9f9f66..c2b32c3 100644
--- a/hw/display/tcx.c
+++ b/hw/display/tcx.c
@@ -1014,10 +1014,13 @@ static void tcx_realizefn(Device
Signed-off-by: Michael Tokarev
---
hw/display/cg3.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/display/cg3.c b/hw/display/cg3.c
index 1e6ff2b..5f869a7 100644
--- a/hw/display/cg3.c
+++ b/hw/display/cg3.c
@@ -302,10 +302,12 @@ static void cg3_realizefn(DeviceSta
On 29/05/2015 13:11, Andrey Korolyov wrote:
> Sorry for a potential thread hijack, but I`m curious about the reasons
> to not making advertised queue depth for non-passthrough backends an
> independent tunable, is there any concerns behind that?
It certainly can be made tunable. Usually it is b
On 2015/5/30 18:34, Paolo Bonzini wrote:
On 28/05/2015 14:08, Shannon Zhao wrote:
>-static qemu_irq *irq_cpu_hotplug; /* Only used in this file */
>+static qemu_irq irq_cpu_hotplug; /* Only used in this file */
>
> #define EVENT_QUAL_CPU_CHANGE 1
>
> void raise_irq_cpu_hotplug(void)
> {
>
Hi Gerd,
On Thu, 28 May 2015 09:13:35 +0200
Gerd Hoffmann wrote:
> > +Scope(\_SB) {
> > +OperationRegion (RCRB, SystemMemory, 0xfed1c000, 0x4000)
>
> Where does this address come from?
This address is reserved in an ACPI DSDT table for Intel Haswell in
Coreboot project, Vlv2DeviceRefCodePk
On Thu, May 28, 2015 at 2:09 PM, Aurelio C. Remonda
wrote:
> This patch adds the Cortex-M4 CPU. The M4 is basically the same as the M3,
> the main differences being the DSP instructions and an optional FPU.
> The DSP instructions are already implemented in Qemu, as the A and R profiles
> use them.
On 28/05/2015 14:08, Shannon Zhao wrote:
> -static qemu_irq *irq_cpu_hotplug; /* Only used in this file */
> +static qemu_irq irq_cpu_hotplug; /* Only used in this file */
>
> #define EVENT_QUAL_CPU_CHANGE 1
>
> void raise_irq_cpu_hotplug(void)
> {
> -qemu_irq_raise(*irq_cpu_hotplug);
On 30/05/2015 11:55, Peter Crosthwaite wrote:
> I think the same is true of NOR.
NOR is sized according to the capacity of its backing file, at least in
the PC case.
Paolo
On Fri, May 29, 2015 at 4:08 AM, Paolo Bonzini wrote:
>
>
> On 29/05/2015 00:11, Liviu Ionescu wrote:
>> for more flexibility, in the new Cortex-M implementation I'm working on, I
>> can overwrite the vendor defined MCU internal SRAM size by using:
>>
>> -m sizeK
>>
>> I'm trying to find a
On Fri, May 29, 2015 at 2:49 PM, Liviu Ionescu wrote:
>
>> On 30 May 2015, at 00:40, Peter Maydell wrote:
>>
>> ... Whether you call it
>> an SoC or an MCU, the key point is that there's a level of
>> abstraction, a container, between the CPU itself and the board.
>> That's where the RAM and flas
I'm trying to reduce qemu as much as possible, so I decide to cut off
some hardware support, i.e. bluetooth, audio, USB and so on.
After some time, compilation succeeded, but when I run qemu --help,
assertion failed.
$ i386-softmmu/qemu-system-i386 --help
**
ERROR:qom/object.c:165:type_get_paren
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/arm/palm.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
index 7f1cfb8..6fe28e5 100644
--- a/hw/arm/palm.c
+++ b/hw/arm/palm.c
@@ -156,7 +156,7 @@ static
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/arm/spitz.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index 5bf032a..454919d 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -812,8 +812,8 @@
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/m68k/an5206.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/m68k/an5206.c b/hw/m68k/an5206.c
index f63ab2b..6ebf2d2 100644
--- a/hw/m68k/an5206.c
+++ b/hw/m68k/an5206.c
@@ -58,7 +58,7 @@
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/sh4/r2d.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c
index 4221060..39edefd 100644
--- a/hw/sh4/r2d.c
+++ b/hw/sh4/r2d.c
@@ -230,7 +230,6 @@ st
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/mips/mips_jazz.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c
index 2c153e0..259458b 100644
--- a/hw/mips/mips_jazz.
From: Shannon Zhao
Signed-off-by: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/arm/tosa.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index 73572eb..4711514 100644
--- a/hw/arm/tosa.c
+++ b/hw/arm/tosa.c
@@ -85,10 +85,8 @@ sta
From: Shannon Zhao
Here we add a member in MachineState to store the irq array returned
from qemu_allocate_irqs. Then these irq arrays will be free before QEMU
exit and it fixes the memory leak spotted by valgrind.
valgrind complains about:
==6366== 4,936 (256 direct, 4,680 indirect) bytes in 1
From: Shannon Zhao
These are relevant to memory leak in machine init function. Here we add
a member in MachineState to store irq array returned from
qemu_allocate_irqs.
PS. These patches are split from my previous patchset [1] since they are
relevant to MachineState.
Thanks,
Shannon
[1] [PATCH
On 2015/5/28 21:11, Cornelia Huck wrote:
> On Thu, 28 May 2015 20:08:52 +0800
> Shannon Zhao wrote:
>
>> > From: Shannon Zhao
>> >
>> > valgrind complains about:
>> > ==1413== 188 (8 direct, 180 indirect) bytes in 1 blocks are definitely
>> > lost in loss record 951 of 1,199
>> > ==1413==
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