This code is already being run in the mb_cpu_realizefn()
function. As PVR registers are preserved on reset this
code is not required.
Signed-off-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
---
target-microblaze/cpu.c |4
1 files changed, 0 insertions(+), 4 deletions(-)
diff --
Remove the hardcoded values from the machine specific reset
function, as the same values are already set in the standard
MicroBlaze reset.
This also allows the entire reset function to be deleted, as
PVR registers are now preserved on reset.
Signed-off-by: Alistair Francis
Reviewed-by: Edgar E.
Move the hard coded register values to the init function.
This also allows the entire reset function to be deleted, as
PVR registers are now preserved on reset.
The hardcoded PVR0 values can be removed as they are setting
the endianness and stack protection, which is already done
or invalid.
Sign
Originally the pvr-full PVR bits were manually set for each machine. This
is a hassle and difficult to read, instead set them based on the CPU
properties.
Signed-off-by: Alistair Francis
---
V2:
- Rename DTS mapping
target-microblaze/cpu-qom.h |1 +
target-microblaze/cpu.c |5 +++--
Originally the version_mask PVR bits were manually set for each
machine. This is a hassle and difficult to read, instead set them
based on the CPU properties.
Signed-off-by: Alistair Francis
---
V2:
- Convert version_mask to a string instead of a bool
hw/microblaze/petalogix_ml605_mmu.c |2
Originally the endi PVR bits were manually set for each machine. This
is a hassle and difficult to read, instead set them based on the CPU
properties.
Signed-off-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
---
hw/microblaze/petalogix_ml605_mmu.c |2 +-
target-microblaze/cpu-qom.h
Rename the usefpu variable to use_fpu.
Signed-off-by: Alistair Francis
---
target-microblaze/cpu-qom.h |2 +-
target-microblaze/cpu.c |8
target-microblaze/translate.c |6 +++---
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-microblaze/cpu-qom
This patch series extends the MicroBlaze properties
that I have been working on. It applies on top of my
original work:
'Add Microblaze configuration options'.
This patch series converts various MicroBlaze PVR registers
to properties. This then allows the individual Microblaze
machine reset functi
On 06/05/2015 02:25 PM, Bharata B Rao wrote:
Reorganize CPU device tree generation code so that it be reused from
hotplug path. CPU dt entries are now generated from spapr_finalize_fdt()
instead of spapr_create_fdt_skel().
Note: This is how the split-up looks like now:
Boot path
-
spapr
On 06/05/2015 02:25 PM, Bharata B Rao wrote:
Use max_cpus instead of smp_cpus when intializating xics system. Also
report max_cpus in ibm,interrupt-server-ranges device tree property of
interrupt controller node.
Signed-off-by: Bharata B Rao
---
hw/ppc/spapr.c | 7 +++
1 file changed, 3
On Fri, Jun 5, 2015 at 10:47 AM, Edgar E. Iglesias
wrote:
> On Thu, Jun 04, 2015 at 11:24:34AM +1000, Alistair Francis wrote:
>> Move the hard coded register values to the init function.
>> This also allows the entire reset function to be deleted, as
>> PVR registers are now preserved on reset.
>
When supporting CPU hot removal by parking the vCPU fd and reusing
it during hotplug again, there can be cases where we try to reenable
KVM_CAP_IRQ_XICS CAP for the vCPU for which it was already enabled.
Introduce a boolean member in ICPState to track this and don't
reenable the CAP if it was alrea
Keep cpu_model field in MachineState uptodate so that it can be used
from the CPU hotplug path.
Signed-off-by: Bharata B Rao
Reviewed-by: David Gibson
---
hw/ppc/mac_newworld.c | 10 +-
hw/ppc/mac_oldworld.c | 7 +++
hw/ppc/ppc440_bamboo.c | 7 +++
hw/ppc/prep.c |
Reorganize CPU device tree generation code so that it be reused from
hotplug path. CPU dt entries are now generated from spapr_finalize_fdt()
instead of spapr_create_fdt_skel().
Note: This is how the split-up looks like now:
Boot path
-
spapr_finalize_fdt
spapr_populate_cpus_dt_node
sp
Factor out bits of sPAPR specific CPU initialization code into
a separate routine so that it can be called from CPU hotplug
path too.
While at this, use MSR_EP define instead of using 6 directly.
Signed-off-by: Bharata B Rao
---
hw/ppc/spapr.c | 54 +-
Add support for ibm,lrdr-capacity since this is needed by the guest
kernel to know about the possible hot-pluggable CPUs and Memory. With
this, pseries kernels will start reporting correct maxcpus in
/sys/devices/system/cpu/possible.
Also define the minimum hotpluggable memory size as 256MB.
Sign
Add CPU_FOREACH_REVERSE that walks CPUs in reverse.
Needed for PowerPC CPU device tree reorganization.
Signed-off-by: Bharata B Rao
Cc: Andreas Färber
---
include/qom/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 39f0f19..42f42f5 100644
XICS is setup for each CPU during initialization. Provide a routine
to undo the same when CPU is unplugged. Also ensure xics reset doesn't set
irq for CPUs that are already unplugged.
This allows reboot of a VM that has undergone CPU hotplug and unplug
to work correctly.
Signed-off-by: Bharata B
Use max_cpus instead of smp_cpus when intializating xics system. Also
report max_cpus in ibm,interrupt-server-ranges device tree property of
interrupt controller node.
Signed-off-by: Bharata B Rao
---
hw/ppc/spapr.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/hw/pp
Hi,
These are the patches that are required to support CPU hotplug for sPAPR
guests. Until now these patches were carried as part of the combined
patchset for sPAPR CPU and Memory hotplug. Since some of these patches
are well reviewed and can be included before the core hotplug changes,
I am posti
On Fri, Jun 5, 2015 at 12:54 PM, Edgar E. Iglesias
wrote:
> On Fri, Jun 05, 2015 at 12:53:05PM +1000, Alistair Francis wrote:
>> On Fri, Jun 5, 2015 at 12:51 PM, Alistair Francis
>> wrote:
>> > On Fri, Jun 5, 2015 at 10:42 AM, Edgar E. Iglesias
>> > wrote:
>> >> On Thu, Jun 04, 2015 at 11:23:19A
We allocate an dummy log even if the size is zero. So we should put it
unconditionally too.
Signed-off-by: Jason Wang
---
hw/virtio/vhost.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
index 01f1e04..3a52a4d 100644
--- a/hw/virtio/v
On 06/04/2015 06:20 PM, John Snow wrote:
> Add the ability to copy one bitmap to a new bitmap.
>
> Signed-off-by: John Snow
> ---
> blockdev.c | 22 ++
> qapi/block-core.json | 16
> qmp-commands.hx | 30 ++
> 3 file
On 06/04/2015 06:44 PM, Michael S. Tsirkin wrote:
> On Thu, Jun 04, 2015 at 05:28:46AM -0400, Jason Wang wrote:
>> > Currently we allocate one vhost log per vhost device. This is sub
>> > optimal when:
>> >
>> > - Guest has several device with vhost as backend
>> > - Guest has multiqueue devices
On Fri, Jun 5, 2015 at 10:44 AM, Edgar E. Iglesias
wrote:
> On Thu, Jun 04, 2015 at 11:23:57AM +1000, Alistair Francis wrote:
>> Originally the pvr-full PVR bits were manually set for each machine. This
>> is a hassle and difficult to read, instead set them based on the CPU
>> properties.
>>
>> Si
On Fri, Jun 05, 2015 at 12:53:05PM +1000, Alistair Francis wrote:
> On Fri, Jun 5, 2015 at 12:51 PM, Alistair Francis
> wrote:
> > On Fri, Jun 5, 2015 at 10:42 AM, Edgar E. Iglesias
> > wrote:
> >> On Thu, Jun 04, 2015 at 11:23:19AM +1000, Alistair Francis wrote:
> >>> Originally the version_mask
On Thu, Jun 4, 2015 at 7:00 PM, Alistair Francis
wrote:
> On Thu, Jun 4, 2015 at 8:52 AM, Peter Crosthwaite
> wrote:
>> On Wed, May 27, 2015 at 12:37 AM, Alistair Francis
>> wrote:
>>> Previously the stream_running() function didn't check
>>> if the DMA was halted. This caused hangs in recent ve
On 06/04/2015 06:20 PM, John Snow wrote:
> We need both a "source" and a "destination" bitmap name,
> so a new type is needed to share with the transactional
> system in a later patch.
>
> Signed-off-by: John Snow
> ---
> qapi/block-core.json | 14 ++
> 1 file changed, 14 insertions(
On Fri, Jun 5, 2015 at 12:51 PM, Alistair Francis
wrote:
> On Fri, Jun 5, 2015 at 10:42 AM, Edgar E. Iglesias
> wrote:
>> On Thu, Jun 04, 2015 at 11:23:19AM +1000, Alistair Francis wrote:
>>> Originally the version_mask PVR bits were manually set for each
>>> machine. This is a hassle and difficu
On 05/13/2015 02:40 PM, Fam Zheng wrote:
> On Wed, 05/13 13:17, Wen Congyang wrote:
>> On 05/13/2015 11:11 AM, Fam Zheng wrote:
>>> Before, we only yield after initializing dirty bitmap, where the QMP
>>> command would return. That may take very long, and guest IO will be
>>> blocked.
>>
>> Do you
On Fri, Jun 5, 2015 at 10:42 AM, Edgar E. Iglesias
wrote:
> On Thu, Jun 04, 2015 at 11:23:19AM +1000, Alistair Francis wrote:
>> Originally the version_mask PVR bits were manually set for each
>> machine. This is a hassle and difficult to read, instead set them
>> based on the CPU properties.
>>
>
On 2015/6/5 0:21, Michael S. Tsirkin wrote:
> Now that both i386 and arm use v2 tables,
> use common code for both.
>
> Warning: untested.
>
> Signed-off-by: Michael S. Tsirkin
> ---
> include/hw/acpi/aml-build.h | 2 ++
> hw/acpi/aml-build.c | 45
> +
On 2015/6/5 0:21, Michael S. Tsirkin wrote:
> XSDT support allows using ACPI 2 features while
> avoiding breaking legacy windows XP guests:
> ACPI 2 tables are linked from XSDT only,
> ACPI 1 tables from both RSDT and XSDT, this way
> XP does not see ACPI 2 tables.
>
> As a first step, this patc
On 06/04/2015 06:20 PM, John Snow wrote:
> One step up from hbitmap, we need a copy primitive for
> the BdrvDirtyBitmap type.
>
> Signed-off-by: John Snow
> ---
> block.c | 26 ++
> include/block/block.h | 4
> 2 files changed, 30 insertions(+)
>
Rev
On 2015/6/5 0:21, Michael S. Tsirkin wrote:
> Collecting these is useful for implementing the XSDT.
>
> Signed-off-by: Michael S. Tsirkin
> ---
> include/hw/acpi/aml-build.h | 3 ++-
> hw/acpi/aml-build.c | 13 ++---
> hw/arm/virt-acpi-build.c| 8
> hw/i386/acpi-
On 2015/6/5 0:21, Michael S. Tsirkin wrote:
> At the moment it mirrors RSDT exactly.
>
> Signed-off-by: Michael S. Tsirkin
> ---
> include/hw/acpi/acpi-defs.h | 15 ---
> include/hw/acpi/aml-build.h | 2 ++
> hw/acpi/aml-build.c | 41 ---
On 06/04/2015 06:20 PM, John Snow wrote:
> It would be nice to have the flexibility to decide that
> we would like multiple backup chains (perhaps of differing
> frequency, or stored at different sites -- who knows.)
>
> If the user didn't have the foresight to add all the requisite
> bitmaps befo
On 06/04/2015 06:20 PM, John Snow wrote:
> If we wish to make differential backups a feature that's easy to access,
> it might be pertinent to rename the "dirty-bitmap" mode to "incremental"
> to make it clear what /type/ of backup the dirty-bitmap is helping us
> perform.
>
> This is an API break
On Fri, Jun 5, 2015 at 10:40 AM, Edgar E. Iglesias
wrote:
> On Thu, Jun 04, 2015 at 11:22:42AM +1000, Alistair Francis wrote:
>> Originally the endi PVR bits were manually set for each machine. This
>> is a hassle and difficult to read, instead set them based on the CPU
>> properties.
>>
>> Signed
On Thu, Jun 4, 2015 at 8:52 AM, Peter Crosthwaite
wrote:
> On Wed, May 27, 2015 at 12:37 AM, Alistair Francis
> wrote:
>> Previously the stream_running() function didn't check
>> if the DMA was halted. This caused hangs in recent versions
>> of MicroBlaze u-boot. Correct stream_running() to check
** Changed in: qemu
Assignee: (unassigned) => kifast (kifast)
** Changed in: qemu
Assignee: kifast (kifast) => (unassigned)
** Changed in: qemu
Assignee: (unassigned) => kifast (kifast)
--
You received this bug notification because you are a member of qemu-
devel-ml, which is sub
On Thu, Jun 04, 2015 at 11:25:49AM +1000, Alistair Francis wrote:
> This code is already being run in the mb_cpu_realizefn()
> function. As PVR registers are preserved on reset this
> code is not required.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Alistair Francis
> ---
> target-micr
On Thu, Jun 04, 2015 at 11:25:11AM +1000, Alistair Francis wrote:
> Remove the hardcoded values from the machine specific reset
> function, as the same values are already set in the standard
> MicroBlaze reset.
>
> This also allows the entire reset function to be deleted, as
> PVR registers are no
On Thu, Jun 04, 2015 at 11:24:34AM +1000, Alistair Francis wrote:
> Move the hard coded register values to the init function.
> This also allows the entire reset function to be deleted, as
> PVR registers are now preserved on reset.
This looks OK but I assume that the remaining pvr settings will
g
On Thu, Jun 04, 2015 at 11:23:57AM +1000, Alistair Francis wrote:
> Originally the pvr-full PVR bits were manually set for each machine. This
> is a hassle and difficult to read, instead set them based on the CPU
> properties.
>
> Signed-off-by: Alistair Francis
> ---
> target-microblaze/cpu-qom
On Thu, Jun 04, 2015 at 11:23:19AM +1000, Alistair Francis wrote:
> Originally the version_mask PVR bits were manually set for each
> machine. This is a hassle and difficult to read, instead set them
> based on the CPU properties.
>
> Signed-off-by: Alistair Francis
> ---
> hw/microblaze/petalog
On Thu, Jun 04, 2015 at 11:22:42AM +1000, Alistair Francis wrote:
> Originally the endi PVR bits were manually set for each machine. This
> is a hassle and difficult to read, instead set them based on the CPU
> properties.
>
> Signed-off-by: Alistair Francis
> ---
> hw/microblaze/petalogix_ml605
On Thu, Jun 04, 2015 at 11:22:42AM +1000, Alistair Francis wrote:
> Originally the endi PVR bits were manually set for each machine. This
> is a hassle and difficult to read, instead set them based on the CPU
> properties.
>
> Signed-off-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
> -
Originally the dcache-writeback PVR bits were manually set for each machine.
This is a hassle and difficult to read, instead set them based on the CPU
properties.
Signed-off-by: Alistair Francis
---
hw/microblaze/petalogix_ml605_mmu.c |3 ++-
target-microblaze/cpu-qom.h |1 +
ta
On 06/04/2015 05:59 PM, Mark Cave-Ayland wrote:
> This patchset follows on from my recent work on fixing issues with the
> macio controller, and remodels the new pmac_dma_read() and pmac_dma_write()
> functions in a similar manner to the unaligned block functions.
>
> With this in place, long ch
Rekerjigger the helper functions to be able to tolerate
differential backups.
Signed-off-by: John Snow
---
tests/qemu-iotests/124 | 69 +++---
1 file changed, 43 insertions(+), 26 deletions(-)
diff --git a/tests/qemu-iotests/124 b/tests/qemu-iotests/1
Signed-off-by: John Snow
---
tests/qemu-iotests/124 | 14 ++
tests/qemu-iotests/124.out | 4 ++--
2 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/tests/qemu-iotests/124 b/tests/qemu-iotests/124
index c446c81..17e4e6c 100644
--- a/tests/qemu-iotests/124
+++ b/tests
Requires: 1433454372-16356-1-git-send-email-js...@redhat.com
[0/10] block: incremental backup transactions
It's entirely possible to use the incremental backup primitives to
achieve a differential backup mechanism, but in the interest of
ease of use, I am proposing the explicit addition
And then add the transaction that allows us to perform this
operation atomically.
Signed-off-by: John Snow
---
blockdev.c | 39 +++
qapi-schema.json | 4 +++-
2 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/blockdev.c b/blockdev.c
index 9
This is simple: instead of clearing the bitmap, just leave the bitmap
data intact even in case of success.
Signed-off-by: John Snow
---
block.c | 9 -
block/backup.c| 17 ++---
block/mirror.c| 9 +++--
include/block/block.h | 1 +
qapi/blo
Add the ability to copy one bitmap to a new bitmap.
Signed-off-by: John Snow
---
blockdev.c | 22 ++
qapi/block-core.json | 16
qmp-commands.hx | 30 ++
3 files changed, 68 insertions(+)
diff --git a/blockdev.c b/bl
We need both a "source" and a "destination" bitmap name,
so a new type is needed to share with the transactional
system in a later patch.
Signed-off-by: John Snow
---
qapi/block-core.json | 14 ++
1 file changed, 14 insertions(+)
diff --git a/qapi/block-core.json b/qapi/block-core.j
If we wish to make differential backups a feature that's easy to access,
it might be pertinent to rename the "dirty-bitmap" mode to "incremental"
to make it clear what /type/ of backup the dirty-bitmap is helping us
perform.
This is an API breaking change, but 2.4 has not yet gone live,
so we have
It would be nice to have the flexibility to decide that
we would like multiple backup chains (perhaps of differing
frequency, or stored at different sites -- who knows.)
If the user didn't have the foresight to add all the requisite
bitmaps before the drive was engaged, the copy function will
allo
One step up from hbitmap, we need a copy primitive for
the BdrvDirtyBitmap type.
Signed-off-by: John Snow
---
block.c | 26 ++
include/block/block.h | 4
2 files changed, 30 insertions(+)
diff --git a/block.c b/block.c
index 1eb81ac..5551f79 100644
--
From: Aurelien Jarno
This complete the general-instructions-extension facility, enable it.
Signed-off-by: Aurelien Jarno
[agraf: remove facility bit]
Signed-off-by: Alexander Graf
---
target-s390x/insn-data.def | 3 +++
target-s390x/translate.c | 35 +++
2 f
From: Aurelien Jarno
At the same time move the trap code from op_ct into gen_trap and use it
for all new functions. The value needs to be stored back to register
before the exception, but also before the brcond (as we don't use
temp locals). That's why we can't use wout helper.
Reviewed-by: Rich
From: Aurelien Jarno
Besides RISBHG and RISBLG, all high-word instructions are not
implemented. Fix that.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
Signed-off-by: Alexander Graf
---
target-s390x/insn-data.def | 47 ++
target-s390x/tr
From: Aurelien Jarno
s390_cpu_handle_mmu_fault currently looks at the current ASC mode
defined in PSW mask instead of the MMU index. This prevent emulating
easily instructions using a specific ASC mode. Fix that by using the
MMU index converted back to ASC using the just added cpu_mmu_idx_to_asc
From: Aurelien Jarno
STORE CLOCK FAST should be in the SCF facility.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
Signed-off-by: Alexander Graf
---
target-s390x/insn-data.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-s390x/insn-data.def b/targ
We allocate ram_size / PAGE_SIZE storage keys, so we need to make sure that
we only access that many. Unfortunately the code can overrun this array by
one, potentially overwriting unrelated memory.
Fix it by limiting storage keys to their scope.
Signed-off-by: Alexander Graf
Reviewed-by: Aurelie
From: Aurelien Jarno
This complete the floating point support sign handling facility.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
Signed-off-by: Alexander Graf
---
target-s390x/insn-data.def | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-s390x/insn-data.def b/t
From: Aurelien Jarno
It is part of the basic zArchitecture instructions.
Signed-off-by: Aurelien Jarno
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-s390x/helper.h | 1 +
target-s390x/insn-data.def | 2 ++
target-s390x/mem_helper.c | 39 +
From: Aurelien Jarno
This is needed to pass the gcc.c-torture/execute/ieee/20010114-2.c test
in the gcc testsuite.
Signed-off-by: Aurelien Jarno
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-s390x/fpu_helper.c | 31 +++
target-s390x/help
From: Aurelien Jarno
The COMPARE LOGICAL IMMEDIATE AND TRAP instruction should compare the
numbers as unsigned, as its name implies.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
Signed-off-by: Alexander Graf
---
target-s390x/insn-data.def | 2 +-
1 file changed, 1 insertion(+
From: Aurelien Jarno
mvcp and mvcs helper get access to the physical memory by a call to
mmu_translate for the virtual to real conversion and then using ldb_phys
and stb_phys to physically access the data. In practice this is quite
slow because it bypasses the QEMU softmmu TLB and because stb_phy
From: Aurelien Jarno
RISBGN is the same as RISBG, but without setting the condition code.
CLT and CLGT are the same as CLRT and CLGRT, but using memory for the
second operand.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
Signed-off-by: Alexander Graf
---
target-s390x/insn-dat
From: Aurelien Jarno
When consecutive memory locations are on page boundary a page fault
might occur when using the LOAD MULTIPLE instruction. In that case real
hardware doesn't load any register.
This is an important detail in case the base register is in the list
of registers to be loaded. If
From: Aurelien Jarno
When an operation code is not recognized (ie invalid instruction) an
operation exception should be generated instead of a specification
exception. The latter is for valid opcode, with invalid operands or
modifiers.
This give a very basic GDB support in the guest, as it uses
From: Aurelien Jarno
It belongs to the DFP rounding facility.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
Signed-off-by: Alexander Graf
---
target-s390x/insn-data.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-s390x/insn-data.def b/target-s390
From: Aurelien Jarno
The s390x floating point unit detects tininess before rounding, so set
the softfloat fp_status up appropriately.
Signed-off-by: Aurelien Jarno
Signed-off-by: Alexander Graf
---
target-s390x/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target-s390x/cpu
From: Aurelien Jarno
The MVC instruction and the memmove C funtion do not have the same
semantic when memory areas overlap:
MVC: When the operands overlap, the result is obtained as if the
operands were processed one byte at a time and each result byte were
stored immediately after fetching the
From: Aurelien Jarno
It is part of the basic zArchitecture instructions. Allow it to be call
from EXECUTE.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
Signed-off-by: Alexander Graf
---
target-s390x/helper.h | 1 +
target-s390x/insn-data.def | 2 ++
target-s390x/mem_he
From: Aurelien Jarno
Signed-off-by: Aurelien Jarno
Signed-off-by: Alexander Graf
---
fpu/softfloat-specialize.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index fa1214a..6dd41d8 100644
--- a/fpu/softfloat-
From: Aurelien Jarno
The cpu_mmu_index function wrongly looks at PSW P bit to determine the
MMU index, while this bit actually only control the use of priviledge
instructions. The addressing mode is detected by looking at the PSW ASC
bits instead.
This used to work more or less correctly up to k
From: Aurelien Jarno
Now that movcond exists, it's easy to write (negative-) absolute value
using TCG code instead of an helper.
Signed-off-by: Aurelien Jarno
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-s390x/helper.h | 2 --
target-s390x/int_helper.c | 22 --
From: Aurelien Jarno
Use constants to define the MMU indexes, and add a function to do
the reverse conversion of cpu_mmu_index.
Signed-off-by: Aurelien Jarno
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-s390x/cpu.h | 25 ++---
1 file changed, 22
From: Aurelien Jarno
Commit 7a6c7067f optimized CC computation by only saving cc_op before
calling helpers as they either don't touch the CC or generate a new
static value. This however doesn't work for the EX instruction as the
helper changes or not the CC value depending on the actual executed
From: Aurelien Jarno
Change to match the PoP. In practice both format RIL-a and RIL-b have
the same fields. They differ on the way we decode the fields, and it's
done correctly in QEMU.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
Signed-off-by: Alexander Graf
---
target-s390
From: Aurelien Jarno
Signed-off-by: Aurelien Jarno
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-s390x/helper.h | 2 --
target-s390x/int_helper.c | 20
2 files changed, 22 deletions(-)
diff --git a/target-s390x/helper.h b/target-s390x/helpe
From: Aurelien Jarno
runtime_exception computes the psw.addr value using the actual exception
address and the instruction length computed by calling the get_ilen
function. However as explained above the get_ilen code, it returns the
actual instruction length, and not the ILC. Therefore there is n
From: Aurelien Jarno
LY is part of the long-displacement facility.
RISBHG and RISBLG are part of the high-word facility.
STCMH is part of the z/Architecture.
Signed-off-by: Aurelien Jarno
Signed-off-by: Alexander Graf
---
target-s390x/insn-data.def | 8
1 file changed, 4 insertions(+
Hi Peter,
This is my current patch queue for s390. Please pull.
Alex
The following changes since commit 3b730f570c5872ceea2137848f1d4554d4847441:
Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream'
into staging (2015-06-04 14:04:14 +0100)
are available in the git rep
From: Aurelien Jarno
LOAD LENGTHENED and LOAD ROUNDED are considered as FP operations and
thus need to convert input sNaN into corresponding qNaN.
Signed-off-by: Aurelien Jarno
Signed-off-by: Alexander Graf
---
target-s390x/fpu_helper.c | 12 ++--
1 file changed, 6 insertions(+), 6 de
From: Aurelien Jarno
Save the timer target value in the SPT helper, so that the STPT helper
can compute the remaining time.
This allow the Linux kernel to correctly do time accounting.
Signed-off-by: Aurelien Jarno
Signed-off-by: Alexander Graf
---
target-s390x/misc_helper.c | 7 ---
1 f
From: Aurelien Jarno
The clock comparator and the QEMU timer work the same way, triggering
at a given time, they just differ by the origin and the scale. It is
therefore possible to go from one to another without using the current
clock value. This spares two calls to qemu_clock_get_ns, which pro
From: Aurelien Jarno
The STCKC instruction just returns the last written clock comparator
value and KVM already provides the corresponding variable.
Signed-off-by: Aurelien Jarno
Signed-off-by: Alexander Graf
---
target-s390x/misc_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletio
From: Aurelien Jarno
Now that clock_value is only used in one place, we can inline it in
the STCK helper.
Signed-off-by: Aurelien Jarno
Signed-off-by: Alexander Graf
---
target-s390x/misc_helper.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/target-s390x/misc_h
From: Aurelien Jarno
Add a tod2time function similar to the time2tod one, instead of open
coding the conversion.
Signed-off-by: Aurelien Jarno
Signed-off-by: Alexander Graf
---
target-s390x/cpu.h | 5 +
target-s390x/misc_helper.c | 4 ++--
2 files changed, 7 insertions(+), 2 delet
From: Aurelien Jarno
LOAD POSITIVE instructions (LPR, LPGR and LPGFR) set the following
condition code:
0: Result zero; no overflow
1: --
2: Result greater than zero; no overflow
3: Overflow
The current code wrongly returns 1 instead of 2 in case of a result
greater than 0. This patches
Subject: Re: [Qemu-devel] [Xen-devel] qemu mainline regression with
xen-unstable: unable to start QMP
Date: Thu, 04 Jun 2015 16:10:34 -0600
From: Eric Blake
Organization: Red Hat, Inc.
To: Don Slutz , Fabio Fantoni ,
qemu-devel@nongnu.org , xen-devel
, Stefano Stabellini
, Anthony PERARD ,
Ia
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 06/04/15 18:10, Eric Blake wrote:
> [adding Markus, as author of the regression]
>
> On 06/04/2015 03:59 PM, Don Slutz wrote:
>> On 06/04/15 11:04, Fabio Fantoni wrote:
>>> Today after trying xen-unstable build (tested many hours) of
>>> some days
Public bug reported:
On 06/04/15 11:04, Fabio Fantoni wrote:
> Today after trying xen-unstable build (tested many hours) of some days
> ago I tried update qemu to latest development version (from git master
> commit 6fa6b312765f698dc81b2c30e7eeb9683804a05b) and seems that there is
> a regression:
> On 05 Jun 2015, at 00:19, Peter Maydell wrote:
>
> ... systick should be fairly small and self contained.
>
> ... My strong initial impression is that we should do this by having
> the CPU object expose a MemoryRegion, which you can then map
> over the right range in the NVIC. I don't think i
On 2015-06-03 10:32, Leon Alrae wrote:
> Extend EntryLo0, EntryLo1, LLAddr and TagLo from 32 to 64 bits in MIPS32.
>
> Signed-off-by: Leon Alrae
> ---
> target-mips/cpu.h | 14 +++---
> target-mips/machine.c | 20 ++--
> target-mips/op_helper.c | 8
> ta
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