This patch allow to limit number of heads using qxl driver. By default
qxl driver is not limited on any kind on head use so can decide to use
as much heads.
libvirt has this as a video card parameter (actually set to 1 but not
used). This parameter will allow to limit setting a use can do (which
c
On Sun, Jul 5, 2015 at 5:05 PM, Jean-Christophe Dubois
wrote:
> Signed-off-by: Jean-Christophe Dubois
> ---
>
> Changes since v1:
> * not present on v1
>
> Changes since v2:
> * not present on v2
>
> Changes since v3:
> * not present on v3
>
> Changes since v4:
> * not present on
Also wondering what this prepares for, can it be deleted later from
its current form?
Regards,
Peter
On Sun, Jul 5, 2015 at 5:05 PM, Jean-Christophe Dubois
wrote:
> Signed-off-by: Jean-Christophe Dubois
> ---
>
> Changes since v1:
> * not present on v1
>
> Changes since v2:
> * not pres
On Sun, Jul 5, 2015 at 5:04 PM, Jean-Christophe Dubois
wrote:
> Signed-off-by: Jean-Christophe Dubois
> ---
>
> Changes since v1:
> * not present on v1
>
> Changes since v2:
> * not present on v2
>
> Changes since v3:
> * not present on v3
>
> Changes since v4:
> * not present on
On Sun, Jul 5, 2015 at 5:04 PM, Jean-Christophe Dubois
wrote:
> Move constructor to DeviceClass methods
> * imx_serial_init
> * imx_serial_realize
>
> imx32_serial_properties is renamed to imx_serial_properties.
>
> The Qdev construction helper is moved to an include file as an
> inline function
Implement pic32 Ethernet interface.
Signed-off-by: Serge Vakulenko
---
hw/mips/pic32_ethernet.c | 557 +++
1 file changed, 557 insertions(+)
create mode 100644 hw/mips/pic32_ethernet.c
diff --git a/hw/mips/pic32_ethernet.c b/hw/mips/pic32_ethernet.c
Hardware register definitions for PIC32MZ microcontroller family.
Signed-off-by: Serge Vakulenko
---
hw/mips/pic32mz.h | 2093 +
1 file changed, 2093 insertions(+)
create mode 100644 hw/mips/pic32mz.h
diff --git a/hw/mips/pic32mz.h b/hw/mips/
This file implements a platform for Microchip PIC32MX7 microcontroller,
with three boards (machine types) supported:
pic32mx7-explorer16 PIC32MX7 microcontroller on Microchip Explorer-16 board
pic32mx7-max32 PIC32MX7 microcontroller on chipKIT Max32 board
pic32mx7-maximitePIC32MX7 micro
Implement pic32 UART peripheral interface.
Signed-off-by: Serge Vakulenko
---
hw/mips/pic32_uart.c | 228 +++
1 file changed, 228 insertions(+)
create mode 100644 hw/mips/pic32_uart.c
diff --git a/hw/mips/pic32_uart.c b/hw/mips/pic32_uart.c
new f
Signed-off-by: Serge Vakulenko
---
default-configs/mipsel-softmmu.mak | 1 +
hw/mips/Makefile.objs | 3 +++
2 files changed, 4 insertions(+)
diff --git a/default-configs/mipsel-softmmu.mak
b/default-configs/mipsel-softmmu.mak
index 0162ef0..b300eff 100644
--- a/default-configs/mips
Implement access to SD card, attached to pic32 SPI port.
Signed-off-by: Serge Vakulenko
---
hw/mips/pic32_sdcard.c | 428 +
1 file changed, 428 insertions(+)
create mode 100644 hw/mips/pic32_sdcard.c
diff --git a/hw/mips/pic32_sdcard.c b/hw/mips/
Implement pic32 SPI peripheral interface.
Signed-off-by: Serge Vakulenko
---
hw/mips/pic32_spi.c | 121
1 file changed, 121 insertions(+)
create mode 100644 hw/mips/pic32_spi.c
diff --git a/hw/mips/pic32_spi.c b/hw/mips/pic32_spi.c
new file
It allows to load executables in Intel .hex or Motorola .srec format.
Signed-off-by: Serge Vakulenko
---
hw/mips/pic32_load_hex.c | 238 +++
1 file changed, 238 insertions(+)
create mode 100644 hw/mips/pic32_load_hex.c
diff --git a/hw/mips/pic32_load
This file implements a platform for Microchip PIC32MZ microcontroller,
with three boards (machine types) supported:
pic32mz-explorer16 PIC32MZ microcontroller on Microchip Explorer-16 board
pic32mz-meb2 PIC32MZ microcontroller on Microchip MEB-II board
pic32mz-wifire PIC32MZ microc
Data definitions and function declarations for simulation
of pic32 microcontrollers.
Signed-off-by: Serge Vakulenko
---
hw/mips/pic32_peripherals.h | 210
1 file changed, 210 insertions(+)
create mode 100644 hw/mips/pic32_peripherals.h
diff --git a/
Implement pic32 generic input/output ports.
Signed-off-by: Serge Vakulenko
---
hw/mips/pic32_gpio.c | 39 +++
1 file changed, 39 insertions(+)
create mode 100644 hw/mips/pic32_gpio.c
diff --git a/hw/mips/pic32_gpio.c b/hw/mips/pic32_gpio.c
new file mode 1006
Hardware register definitions for PIC32MX microcontroller family.
Signed-off-by: Serge Vakulenko
---
hw/mips/pic32mx.h | 1290 +
1 file changed, 1290 insertions(+)
create mode 100644 hw/mips/pic32mx.h
diff --git a/hw/mips/pic32mx.h b/hw/mips/
Needed for pic32mx (M4K) and pic32mz (microAptivUP) simulation.
Signed-off-by: Serge Vakulenko
---
target-mips/translate_init.c | 46
1 file changed, 46 insertions(+)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index ddfa
Please find below a set of patches, which allow to simulate Microchip PIC32
microcontrollers on QEMU. For examples of real PIC32 applications running
on QEMU, see page: https://github.com/sergev/qemu/wiki
(1) Make the CPU clock frequency configurable per platform.
Currently the clock rate for
The LFSR algorithm, used for generating random TLB indexes for TLBWR
instruction,
was inclined to produce a degenerate sequence in some cases.
For example, for 16-entry TLB size and Wired=1, it gives: 15, 6, 7, 2,
7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2...
When repla
EIC is required for pic32 microcontroller.
Signed-off-by: Serge Vakulenko
---
hw/mips/cputimer.c | 17 +++--
hw/mips/mips_int.c | 8 +++-
target-mips/cpu.h| 8 +++-
target-mips/helper.c | 18 --
4 files changed, 41 insertions(+), 10 deletions(-)
dif
Currently the clock rate for all MIPS platforms is fixed at 100MHz.
Need to make it 40MHz for pic32mx7.
Signed-off-by: Serge Vakulenko
---
hw/mips/cputimer.c| 15 +++
hw/mips/mips_fulong2e.c | 2 +-
hw/mips/mips_jazz.c | 2 +-
hw/mips/mips_malta.c | 4 ++--
hw
On (Tue) 16 Jun 2015 [11:26:16], Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> One of my patches used a loop that was based on host page size;
> it dies in qtest since qtest hadn't bothered init'ing it.
>
> Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Amit Shah
On 2015/7/4 1:51, Dr. David Alan Gilbert wrote:
* zhanghailiang (zhang.zhanghaili...@huawei.com) wrote:
configure --enable-colo/--disable-colo to switch COLO
support on/off.
COLO support is off by default.
Signed-off-by: zhanghailiang
Signed-off-by: Yang Hongyang
Signed-off-by: Gonglei
Signe
The following patch might fix this (I have not yet tested this patch
myself): https://lkml.org/lkml/2015/7/5/217
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1435359
Title:
Booting kernel 3.19.2
On Wed, Jul 1, 2015 at 10:56 PM, Antony Pavlov wrote:
> On Tue, 30 Jun 2015 21:12:34 -0700
> Serge Vakulenko wrote:
>
>> Signed-off-by: Serge Vakulenko
>> ---
>> hw/mips/Makefile.objs |3 +
>> hw/mips/mips_pic32mx7.c | 1652 +
>> hw/mips/mips_pic32mz.c
Cc: qemu-sta...@nongnu.org
Signed-off-by: Fam Zheng
---
block.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block.c b/block.c
index 7e130cc..42eb8e3 100644
--- a/block.c
+++ b/block.c
@@ -1271,7 +1271,7 @@ int bdrv_append_temp_snapshot(BlockDriverState *bs, int
flags, Err
On Wed, Jul 1, 2015 at 6:41 AM, Aurelien Jarno wrote:
> On 2015-06-30 21:12, Serge Vakulenko wrote:
>> Signed-off-by: Serge Vakulenko
>> ---
>> hw/mips/Makefile.objs |3 +
>> hw/mips/mips_pic32mx7.c | 1652 +
>> hw/mips/mips_pic32mz.c | 2840
>> +++
On Fri, Jul 3, 2015 at 3:04 PM, Maciej W. Rozycki wrote:
> On Wed, 1 Jul 2015, Aurelien Jarno wrote:
>
>> > diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
>> > index ddfaff8..430a547 100644
>> > --- a/target-mips/translate_init.c
>> > +++ b/target-mips/translate_init.c
>>
On Wed, Jul 1, 2015 at 6:37 AM, Aurelien Jarno wrote:
> On 2015-06-30 21:12, Serge Vakulenko wrote:
>> Signed-off-by: Serge Vakulenko
>> ---
>> target-mips/cpu.h| 2 ++
>> target-mips/translate_init.c | 46
>>
>> 2 files changed, 48 inse
On Thu, 07/02 17:24, Stefan Hajnoczi wrote:
> The doc comments for bdrv_drain_all() and bdrv_drain() are outdated:
>
> * The bdrv_drain() comment is a poor man's bdrv_lock()/bdrv_unlock()
>which Fam Zheng is currently developing. Unfortunately this warning
>was never really enough becaus
On 07/02/2015 08:46 PM, Stefan Hajnoczi wrote:
> On Tue, Jun 30, 2015 at 04:35:24PM +0800, Jason Wang wrote:
>> On 06/30/2015 11:06 AM, Fam Zheng wrote:
>>> virtio_net_receive still does the check by calling
>>> virtio_net_can_receive, if the device or driver is not ready, the packet
>>> is dropp
On Sun, Jul 5, 2015 at 8:05 PM, Serge Vakulenko
wrote:
> On Wed, Jul 1, 2015 at 4:07 AM, Aurelien Jarno wrote:
>> On 2015-06-30 21:12, Serge Vakulenko wrote:
>>> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
>>> index c476166..ab830ee 100644
>>> --- a/target-mips/cpu.h
>>> +++ b/target-mips/
block_job_sleep_ns is called by block job coroutines to yield the
execution to VCPU threads and monitor etc. It is pointless to sleep for
0 or a few nanoseconds, because that equals to a "yield + enter" with no
intermission in between (the timer fires immediately in the same
iteration of event loop
On Wed, Jul 1, 2015 at 4:07 AM, Aurelien Jarno wrote:
> On 2015-06-30 21:12, Serge Vakulenko wrote:
>> Signed-off-by: Serge Vakulenko
>> ---
>> hw/mips/cputimer.c | 17 +++--
>> hw/mips/mips_int.c | 12 ++--
>> target-mips/cpu.h| 9 -
>> target-mips/helper.c
Ping?
Regards,
Ting
On 2015-6-26 17:37, Ting Wang wrote:
> There is job resource leak in function mirror_start_job,
> although bdrv_create_dirty_bitmap is unlikely failed.
> Add block_job_release for each release when needed.
>
> Signed-off-by: Ting Wang
> ---
> block/mirror.c | 2 +
On 2015-7-3 20:43, Markus Armbruster wrote:
> Copying the HMP maintainer Luiz. You can feed your patch to
> scripts/get_maintainer to find people to cc yourself.
OK, thanks.
Ting
>
> Ting Wang writes:
>
>> Make "info iothreads" available on the HMP monitor.
>>
>> For example, the results are as
On systems with guest visible IOMMU, adding a new memory region onto
PCI bus calls vfio_listener_region_add() for every DMA window. This
installs a notifier for IOMMU memory regions. The notifier is supposed
to be removed by vfio_listener_region_del(), however in the case of mixed
PHB (emulated + V
This adds support for Dynamic DMA Windows (DDW) option defined by
the SPAPR specification which allows to have additional DMA window(s)
This implements DDW for emulated and VFIO devices. As all TCE root regions
are mapped at 0 and 64bit long (and actual tables are child regions),
this replaces mem
sPAPRTCETable is handling 2 TCE tables already:
1) guest view of the TCE table - emulated devices use only this table;
2) hardware IOMMU table - VFIO PCI devices use it for actual work but
it does not replace 1) and it is not visible to the guest.
The initialization of this table is driven by vfi
sPAPR IOMMU is managing two copies of an TCE table:
1) a guest view of the table - this is what emulated devices use and
this is where H_GET_TCE reads from;
2) a hardware TCE table - only present if there is at least one vfio-pci
device on a PHB; it is updated via a memory listener on a PHB address
Currently TCE tables are created once at start and their size never
changes. We are going to change that by introducing a Dynamic DMA windows
support where DMA configuration may change during the guest execution.
This changes spapr_tce_new_table() to create an empty stub object. Only
LIOBN is assi
This updates linux-headers against master 4.2-rc1 (commit
d770e558e21961ad6cfdf0ff7df0eb5d7d4f0754). This is the result of
./scripts/update-linux-headers.sh work.
Cc: Paolo Bonzini
Cc: Michael S. Tsirkin
Signed-off-by: Alexey Kardashevskiy
---
This is for DDW support on sPAPR.
---
include/sta
sPAPRTCETable has a vfio_accel flag which is passed to
kvmppc_create_spapr_tce() and controls whether to create a guest view
table in KVM as this depends on the host kernel ability to accelerate
H_PUT_TCE for VFIO devices. We would set this flag at the moment
when sPAPRTCETable is created in spapr_
This enables multiple IOMMU groups in one VFIO container which means
that multiple devices from different groups can share the same IOMMU
table (or tables if DDW).
This removes a group id from vfio_container_ioctl(). The kernel support
is required for this; if the host kernel does not have the sup
This makes use of the new "memory registering" feature. The idea is
to provide the userspace ability to notify the host kernel about pages
which are going to be used for DMA. Having this information, the host
kernel can pin them all once per user process, do locked pages
accounting (once) and not s
This reworks finish_realize() which used to finalize DMA setup with
an assumption that it will not change later.
New callbacks supports various window parameters such as page and
windows sizes. The new callback return error code rather than Error**.
This is a mechanical change so no change in beh
(cut-n-paste from kernel patchset)
Each Partitionable Endpoint (IOMMU group) has an address range on a PCI bus
where devices are allowed to do DMA. These ranges are called DMA windows.
By default, there is a single DMA window, 1 or 2GB big, mapped at zero
on a PCI bus.
PAPR defines a DDW RTAS AP
At the moment presence of vfio-pci devices on a bus affect the way
the guest view table is allocated. If there is no vfio-pci on a PHB
and the host kernel supports KVM acceleration of H_PUT_TCE, a table
is allocated in KVM. However, if there is vfio-pci and we do yet not
KVM acceleration for these,
On a system reset, DMA configuration has to reset too. At the moment
it clears the table content. This is enough for the single table case
but with DDW, we will also have to disable all DMA windows except
the default one. Furthermore according to sPAPR, if the guest removed
the default window and c
We are going to have multiple DMA windows at different offsets on
a PCI bus. For the sake of migration, we will have as many TCE table
objects pre-created as many windows supported.
So we need a way to map windows dynamically onto a PCI bus
when migration of a table is completed but at this stage a
This allows dynamic allocation for migrating arrays.
Already existing VMSTATE_VARRAY_UINT32 requires an array to be
pre-allocated, however there are cases when the size is not known in
advance and there is no real need to enforce it.
This defines another variant of VMSTATE_VARRAY_UINT32 with WMS_
On 7/5/2015 2:25, Michael S. Tsirkin wrote:
On Fri, Jul 03, 2015 at 07:09:59PM +0800, Hong Bo Li wrote:
But I would like to note that pci device drivers require driver handshake
before device goes away.
IIUC s390 hotplug is immediate, which is a problem.
Maybe doing the change will help make s
On Sat, 07/04 10:47, Max Filippov wrote:
> Hello,
>
> I'm using QEMU with TAP network and after the commit
> 0a2df857a703 "Merge remote-tracking branch
> 'remotes/stefanha/tags/net-pull-request' into staging"
> I've noticed that activation of debugger connected to QEMU's
> gdbstub during network I
The timer should fire the interrupt only if the IT (interrupt enable) bit
state of the control register is enabled.
Signed-off-by: Dmitry Osipenko
Reviewed-by: Peter Crosthwaite
---
v2: Added missed IRQ status update on control register write as per
Peter Crosthwaite comment.
v3: No code c
v2: Added missed IRQ status update on control register write as per
Peter Crosthwaite comment.
Oh, no! Turned out, that is wrong. I wasn't testing that case properly on HW, V1
is correct. Quote from ARM doc "If the timer interrupt is enabled, Interrupt ID
29 is set as Pending in the Inter
On 07/04/2015 11:12 AM, Alexey Kardashevskiy wrote:
On 05/27/2015 05:05 PM, Paolo Bonzini wrote:
On 27/05/2015 01:55, Alexey Kardashevskiy wrote:
One step back :) Whole dance is what here? There are:
1) del+set_size(0)
2) set_size(not zero)+add
Then no need for begin/commit. :)
I got a ne
On Wed, Jul 1, 2015 at 10:31 PM, Antony Pavlov wrote:
> On Tue, 30 Jun 2015 21:12:29 -0700
> Serge Vakulenko wrote:
>
>> Please find below a set of patches, which allow to simulate Microchip PIC32
>> microcontrollers on QEMU. For examples of real PIC32 applications running
>> on QEMU, see page: h
Signed-off-by: Jean-Christophe Dubois
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
* not present on v
Signed-off-by: Jean-Christophe Dubois
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
* not present on v
On Fri, Jul 3, 2015 at 2:39 PM, Maciej W. Rozycki wrote:
> On Wed, 1 Jul 2015, Aurelien Jarno wrote:
>
>> Secondly, I don't think calling random() is the correct thing to do.
>> It's an expensive function that is not thread safe. Quoting the
>> specification:
>>
>> "Within the required constrain
Signed-off-by: Jean-Christophe Dubois
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
* not present on v
Signed-off-by: Jean-Christophe Dubois
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
* not present on v
Signed-off-by: Jean-Christophe Dubois
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
* not present on v
On Thu, Jul 2, 2015 at 12:52 AM, Antony Pavlov wrote:
> On Tue, 30 Jun 2015 21:12:31 -0700
> Serge Vakulenko wrote:
>
>> Signed-off-by: Serge Vakulenko
>> ---
>> hw/mips/cputimer.c | 18 +-
>> 1 file changed, 5 insertions(+), 13 deletions(-)
>>
>> diff --git a/hw/mips/cputimer.c
Signed-off-by: Jean-Christophe Dubois
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
* not present on v
Signed-off-by: Jean-Christophe Dubois
---
Changes since v1:
* Added a ds1338 I2C device for qtest purpose.
Changes since v2:
* none
Changes since v3:
* Rework GPL header
* use I2C constructor helper.
Changes since v4:
* use sysbus_create_simple() instead of I2C c
This is using a ds1338 RTC chip on the I2C bus. This RTC chip is
not present on the real 3DS PDK board.
Signed-off-by: Jean-Christophe Dubois
---
Changes since v1:
* not present on v1
Changes since v2:
* use a common header file for I2C regs definition
Changes since v3:
* rework GP
This is based on mcf_fec.c FEC implementation for Coldfire
* A generic PHY was added (borrowwed from LAN9118)
* The buffer management is also modified as buffers are
slightly different between Coldfire and i.MX
Signed-off-by: Jean-Christophe Dubois
Reviewed-by: Peter Crosthwaite
---
Ch
Signed-off-by: Jean-Christophe Dubois
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
* not present on v
The slave mode is not implemented.
Signed-off-by: Jean-Christophe Dubois
Reviewed-by: Peter Crosthwaite
---
Changes since v1:
* none
Changes since v2:
* use QOM cast
* reworked debug printf
* use CamelCase for state type
* warn with qemu_log_mask(LOG_GUEST_ERROR) or qemu_lo
Tested by booting a minimal linux system on the emulated plateform
Note: Qdev construction helper functions are removed with this patch.
Signed-off-by: Jean-Christophe Dubois
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not pr
Signed-off-by: Jean-Christophe Dubois
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
* not present on v
Signed-off-by: Jean-Christophe Dubois
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
* not present on v
Move constructor to DeviceClass methods
* imx_serial_init
* imx_serial_realize
imx32_serial_properties is renamed to imx_serial_properties.
The Qdev construction helper is moved to an include file as an
inline function. This function is going to be removed soon.
Signed-off-by: Jean-Christophe
Signed-off-by: Jean-Christophe Dubois
Reviewed-by: Peter Crosthwaite
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes
Signed-off-by: Jean-Christophe Dubois
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
* not present on v
Signed-off-by: Jean-Christophe Dubois
Reviewed-by: Peter Crosthwaite
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes
Signed-off-by: Jean-Christophe Dubois
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
* not present on v
Signed-off-by: Jean-Christophe Dubois
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
* not present on v
Signed-off-by: Jean-Christophe Dubois
Reviewed-by: Peter Crosthwaite
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes
This series of patches add the support for the i.MX25 processor through the
Freescale 3DS evaluation board.
For now a limited set of devices are supported.
* GPT timers (from i.MX31)
* EPIT timers (from i.MX31)
* Serial ports (from i.MX31)
* Ethernet FEC port
* I2C controller
On Wed, Jul 1, 2015 at 3:11 AM, Aurelien Jarno wrote:
> On 2015-06-30 21:12, Serge Vakulenko wrote:
>> Signed-off-by: Serge Vakulenko
>> ---
>> hw/mips/cputimer.c | 18 +-
>> 1 file changed, 5 insertions(+), 13 deletions(-)
>>
>> diff --git a/hw/mips/cputimer.c b/hw/mips/cputimer
On Wed, Jul 1, 2015 at 3:02 AM, Aurelien Jarno wrote:
> On 2015-06-30 21:12, Serge Vakulenko wrote:
>> @@ -153,5 +153,6 @@ void cpu_mips_clock_init (CPUMIPSState *env)
>> */
>> if (!kvm_enabled()) {
>> env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &mips_timer_cb, env);
>> +
The timer should fire interrupt only if IT(interrupt enable) bit state of
control register is enabled and the timer should update IRQ status on IT
bit change as it would mask/unmask the interrupt line.
Signed-off-by: Dmitry Osipenko
Reviewed-by: Peter Crosthwaite
---
v2: Added missed IRQ status
Hello, this is V3 of arm_mptimer patch series. No code changes here, just
grammar fixes for "shutdown and mode change" patch and general re-send, as
V2 was screwed for patchtracker.
Dmitry Osipenko (2):
arm_mptimer: Fix timer shutdown and mode change
arm_mptimer: Respect IT bit state
hw/time
The running timer can't be stopped because timer control code just
doesn't handle disabling the timer. Fix it by deleting the timer if
the enable bit is cleared.
The timer won't start periodic ticking if a ONE-SHOT -> PERIODIC mode
change happens after a one-shot tick was completed. Fix it by
re-s
IOW, add a line like this below the line added by the above patch:
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c,
quirk_no_bus_reset);
Double check that vendor:device ID against 'lspci -nn', that's
168c:003c.
--
You received this bug notification because you are a member of qemu-
devel
It probably needs a quirk like this to avoid bus resets:
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/drivers/pci/quirks.c?id=c3e59ee4e76686b0c84ca8faa1011d10cd4ca1b8
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to
06.07.2015 00:19, Peter Crosthwaite пишет:
On Sun, Jul 5, 2015 at 8:39 AM, Dmitry Osipenko wrote:
Timer, running in periodic mode, can't be stopped or coming one-shot
tick won't be canceled because timer control code just doesn't handle
timer disabling. Fix it by deleting the timer if enable bi
06.07.2015 00:06, Peter Maydell пишет:
On 5 July 2015 at 22:01, Peter Crosthwaite wrote:
On Sun, Jul 5, 2015 at 1:58 PM, Peter Crosthwaite
wrote:
On Sun, Jul 5, 2015 at 1:47 PM, Dmitry Osipenko wrote:
Hi Peter, thanks a lot! Generally, I don't have any trouble with currently
missed function
On Sun, Jul 5, 2015 at 8:39 AM, Dmitry Osipenko wrote:
> Timer, running in periodic mode, can't be stopped or coming one-shot
> tick won't be canceled because timer control code just doesn't handle
> timer disabling. Fix it by deleting the timer if enable bit isn't set.
>
You don't need to itemize
On Sun, Jul 5, 2015 at 2:06 PM, Peter Maydell wrote:
> On 5 July 2015 at 22:01, Peter Crosthwaite
> wrote:
>> On Sun, Jul 5, 2015 at 1:58 PM, Peter Crosthwaite
>> wrote:
>>> On Sun, Jul 5, 2015 at 1:47 PM, Dmitry Osipenko wrote:
Hi Peter, thanks a lot! Generally, I don't have any trouble
There was a complicated subtractive arithmetic for determining the
padding on the CPUTLBEntry structure. Simplify this with a union.
Signed-off-by: Peter Crosthwaite
---
include/exec/cpu-defs.h | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/include/
Public bug reported:
CPU: Intel(R) Xeon(R) CPU E3-1265L v3 @ 2.50GHz
KVM: qemu-kvm-1.5.3-86.el7_1.2.x86_64
Kernel: 4.1.1-1.el7.elrepo.x86_64, and kernel-3.10.0-229.7.2.el7.x86_64
Host & Guest: CentOS 7.1
Using virt-manager-1.1.0-12.el7.noarch to create, configure, and start guest
I am trying t
On 5 July 2015 at 22:01, Peter Crosthwaite wrote:
> On Sun, Jul 5, 2015 at 1:58 PM, Peter Crosthwaite
> wrote:
>> On Sun, Jul 5, 2015 at 1:47 PM, Dmitry Osipenko wrote:
>>> Hi Peter, thanks a lot! Generally, I don't have any trouble with currently
>>> missed functionality, just noticed it while
On 4 July 2015 at 07:06, John Snow wrote:
> The following changes since commit 35360642d043c2a5366e8a04a10e5545e7353bd5:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/pull-input-20150703-1'
> into staging (2015-07-03 12:05:31 +0100)
>
> are available in the git repository at:
>
> http
On Sun, Jul 5, 2015 at 1:58 PM, Peter Crosthwaite
wrote:
> On Sun, Jul 5, 2015 at 1:47 PM, Dmitry Osipenko wrote:
>> 05.07.2015 23:26, Peter Crosthwaite пишет:
>>
>>> Hi Dmitry,
>>>
>>> Based on my comment earlier, this is what I came up with RE consolidation
>>> of
>>> those arm_mptimer code pat
On Sun, Jul 5, 2015 at 1:47 PM, Dmitry Osipenko wrote:
> 05.07.2015 23:26, Peter Crosthwaite пишет:
>
>> Hi Dmitry,
>>
>> Based on my comment earlier, this is what I came up with RE consolidation
>> of
>> those arm_mptimer code paths that were giving you problems. I have not
>> done the
>> interru
It does not work in multi-arch as it requires the CPU specific
TARGET_VIRT_ADDR_SPACE_BITS global define. Just use the generic
version that does no masking. Targets should be responsible for
passing in a sane virtual address.
Signed-off-by: Peter Crosthwaite
---
Depends on "Unify and QOMify (targ
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