Re: [Qemu-devel] [PATCH v9 11/37] qapi: Consolidate visitor small integer callbacks

Eric Blake writes: > On 01/20/2016 10:34 AM, Markus Armbruster wrote: >> Eric Blake writes: >> >>> Commit 4e27e819 introduced optional visitor callbacks for all >>> sorts of int types, but no visitor has supplied any of the >>> callbacks for sizes less

Re: [Qemu-devel] [PATCH v2] pc: allow raising low memory via max-ram-below-4g option

On Thu, Jan 21, 2016 at 08:48:53AM +0100, Gerd Hoffmann wrote: > On Mi, 2016-01-20 at 19:25 +0200, Michael S. Tsirkin wrote: > > On Wed, Jan 20, 2016 at 03:15:04PM -0200, Eduardo Habkost wrote: > > > On Wed, Jan 20, 2016 at 01:34:29PM -0200, Eduardo Habkost wrote: > > > [...] > > > > Considering

Re: [Qemu-devel] [PATCH v9 18/37] qapi: Drop unused error argument for list and implicit struct

Eric Blake writes: > On 01/20/2016 12:03 PM, Markus Armbruster wrote: >> Eric Blake writes: >> >>> No backend was setting an error when ending the visit of a list >>> or implicit struct. >> >> That's a lie: qmp_input_end_list() does. But it shouldn't, as

Re: [Qemu-devel] [PATCH v9 15/37] qom: Swap 'name' next to visitor in ObjectPropertyAccessor

Am 21.01.2016 um 10:18 hat Markus Armbruster geschrieben: > Eric Blake writes: > > On 01/20/2016 11:49 AM, Markus Armbruster wrote: > >> Eric Blake writes: > >> > >> However, the actual match is looser! For instance, it also matches > >> > >> void

[Qemu-devel] [PULL 10/36] exec-all.h: Document tlb_set_page_with_attrs, tlb_set_page

Add documentation comments for tlb_set_page_with_attrs() and tlb_set_page(). Signed-off-by: Peter Maydell Acked-by: Edgar E. Iglesias --- include/exec/exec-all.h | 34 +++--- 1 file changed, 31 insertions(+), 3

[Qemu-devel] [PULL 00/36] target-arm queue

/for-upstream' into staging (2016-01-21 13:09:47 +) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160121 for you to fetch changes up to 03fbf20f4da58f41998dc10ec7542f65d37ba759: target-arm: Implement FPEXC32_EL2 system

[Qemu-devel] [PULL 13/36] cputlb.c: Use correct address space when looking up MemoryRegionSection

When looking up the MemoryRegionSection for the new TLB entry in tlb_set_page_with_attrs(), use cpu_asidx_from_attrs() to determine the correct address space index for the lookup, and pass it into address_space_translate_for_iotlb(). Signed-off-by: Peter Maydell

[Qemu-devel] [PULL 19/36] qom/cpu: Add MemoryRegion property

From: Peter Crosthwaite Add a MemoryRegion property, which if set is used to construct the CPU's initial (default) AddressSpace. Signed-off-by: Peter Crosthwaite [PMM: code is moved from qom/cpu.c to exec.c to avoid having to make

[Qemu-devel] [PULL 01/12] target-i386: Rename optimize_flags_init()

Rename the function so that the reason for its existence is clearer: it does x86-specific initialization of TCG structures. Reviewed-by: Igor Mammedov Signed-off-by: Eduardo Habkost --- target-i386/cpu.c | 2 +- target-i386/cpu.h | 2 +-

[Qemu-devel] [PULL 07/12] target-i386: Define MMREG_UNION macro

This will simplify the definitions of ZMMReg and MMXReg. Reviewed-by: Richard Henderson Signed-off-by: Eduardo Habkost --- target-i386/cpu.h | 27 +++ 1 file changed, 11 insertions(+), 16 deletions(-) diff --git

Re: [Qemu-devel] [PATCH v2 2/3] target-arm: Make pamax an argument to check_s2_startlevel

Edgar E. Iglesias writes: > From: "Edgar E. Iglesias" > > Make pamax an argument to check_s2_startlevel in preparation > for future reuse. > > No functional change. > > Signed-off-by: Edgar E. Iglesias > --- >

Re: [Qemu-devel] [PATCH v6 01/15] block: Add "file" output parameter to block status query functions

On 08.01.2016 03:08, Fam Zheng wrote: > The added parameter can be used to return the BDS pointer which the > valid offset is referring to. Its value should be ignored unless > BDRV_BLOCK_OFFSET_VALID in ret is set. > > Until block drivers fill in the right value, let's clear it explicitly >

[Qemu-devel] [PULL 32/36] target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target

The entry offset when taking an exception to AArch64 from a lower exception level may be 0x400 or 0x600. 0x400 is used if the implemented exception level immediately lower than the target level is using AArch64, and 0x600 if it is using AArch32. We were incorrectly implementing this as checking

[Qemu-devel] [PULL 35/36] target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode

The architecture requires that for an exception return to AArch32 the low bits of ELR_ELx are ignored when the PC is set from them: * if returning to Thumb mode, ignore ELR_ELx[0] * if returning to ARM mode, ignore ELR_ELx[1:0] We were only squashing bit 0; also squash bit 1 if the SPSR T bit

[Qemu-devel] [PULL 20/36] target-arm: Add QOM property for Secure memory region

Add QOM property to the ARM CPU which boards can use to tell us what memory region to use for secure accesses. Nonsecure accesses go via the memory region specified with the base CPU class 'memory' property. By default, if no secure region is specified it is the same as the nonsecure region, and

[Qemu-devel] [PULL 07/36] misc: zynq-xadc: Fix off-by-one

From: Peter Crosthwaite This bounds check was off-by-one. Fix. Reported-by: Paolo Bonzini Signed-off-by: Peter Crosthwaite Message-id: 1453101737-11255-1-git-send-email-crosthwaite.pe...@gmail.com Reviewed-by: Peter

[Qemu-devel] [PULL 06/36] xlnx-ep108: Connect the SPI Flash

From: Alistair Francis Connect the sst25wf080 SPI flash to the EP108 board. Signed-off-by: Alistair Francis Reviewed-by: Peter Crosthwaite Signed-off-by: Peter Crosthwaite

[Qemu-devel] [PULL 21/36] target-arm: Implement asidx_from_attrs

Implement the asidx_from_attrs CPU method to return the Secure or NonSecure address space as appropriate. (The function is inline so we can use it directly in target-arm code to be added in later patches.) Signed-off-by: Peter Maydell Acked-by: Edgar E. Iglesias

[Qemu-devel] [PULL 11/36] cpu: Add new get_phys_page_attrs_debug() method

Add a new optional method get_phys_page_attrs_debug() to CPUClass. This is like the existing get_phys_page_debug(), but also returns the memory transaction attributes to use for the access. This will be necessary for CPUs which have multiple address spaces and use the attributes to select the

[Qemu-devel] [PULL 04/36] xilinx_spips: Separate the state struct into a header

From: Alistair Francis Separate out the XilinxSPIPS struct into a separate header file. Signed-off-by: Alistair Francis Reviewed-by: Peter Crosthwaite Signed-off-by: Peter Crosthwaite

[Qemu-devel] [PULL 22/36] target-arm: Implement cpu_get_phys_page_attrs_debug

Implement cpu_get_phys_page_attrs_debug instead of cpu_get_phys_page_debug. Signed-off-by: Peter Maydell Acked-by: Edgar E. Iglesias --- target-arm/cpu-qom.h | 3 ++- target-arm/cpu.c | 2 +- target-arm/helper.c | 9 + 3 files

Re: [Qemu-devel] [PATCH v1 2/3] target-arm: Make pamax an argument to check_s2_startlevel

On Thu, Jan 21, 2016 at 12:26:47PM +, Alex Bennée wrote: > > Edgar E. Iglesias writes: > > > From: "Edgar E. Iglesias" > > > > Make pamax an argument to check_s2_startlevel in preparation > > for future reuse. > > > > No functional

Re: [Qemu-devel] [RFC PATCH] vfio: Add sysfsdev property for pci & platform

On Thu, 2016-01-21 at 07:51 +, Tian, Kevin wrote: > > From: Alex Williamson [mailto:alex.william...@redhat.com] > > Sent: Thursday, January 21, 2016 2:07 AM > > > > vfio-pci currently requires a host= parameter, which comes in the > > form of a PCI address in [domain:] notation.  We > >

[Qemu-devel] [PULL 12/12] target-i386: Add PKU and and OSPKE support

From: Huaitong Han Add PKU and OSPKE CPUID features, including xsave state and migration support. Signed-off-by: Huaitong Han Reviewed-by: Eduardo Habkost [ehabkost: squashed 3 patches together, edited patch description]

Re: [Qemu-devel] [Qemu-block] [PATCH v4 00/12] fdc: fix 2.88mb floppy diskette support

On Thu, Jan 21, 2016 at 09:59:09AM -0500, John Snow wrote: > > Now that is a bit trickier: the currently submitted code queries the > > floppy properties at SSDT build time, and sticks static objects into > > AML; if that really needs updating at runtime it'll require certain > > refactoring. > >

Re: [Qemu-devel] virtio ring layout changes for optimal single-stream performance

On Thu, 21 Jan 2016 15:39:26 +0200 "Michael S. Tsirkin" wrote: > Hi all! > I have been experimenting with alternative virtio ring layouts, > in order to speed up single stream performance. > > I have just posted a benchmark I wrote for the purpose, and a (partial) > alternative

Re: [Qemu-devel] [PATCH v2] xen-pvdevice: convert to realize()

Yes, it is in my "next" branch, I am waiting for your larger series to be fully acked to commit it, then I'll send a pull request with everything outstanding in it. On Thu, 21 Jan 2016, Cao jin wrote: > Hi Stefano, > > just want to make sure: is this picked up? > > On 12/22/2015 07:51 PM,

Re: [Qemu-devel] [PULL 00/36] target-arm queue

he following changes since commit 3c9331c47f4118d5019b0af8eac704824d8d: > > Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging > (2016-01-21 13:09:47 +) > > are available in the git repository at: > > > git://git.linaro.org/people/pmaydell/

[Qemu-devel] [PATCH v4 3/3] iscsi: add support for getting CHAP password via QCryptoSecret API

The iSCSI driver currently accepts the CHAP password in plain text as a block driver property. This change adds a new "password-secret" property that accepts the ID of a QCryptoSecret instance. $QEMU \ -object secret,id=sec0,filename=/home/berrange/example.pw \ -drive

[Qemu-devel] [PATCH v4 1/3] rbd: add support for getting password from QCryptoSecret object

Currently RBD passwords must be provided on the command line via $QEMU -drive file=rbd:pool/image:id=myname:\ key=QVFDVm41aE82SHpGQWhBQXEwTkN2OGp0SmNJY0UrSE9CbE1RMUE=:\ auth_supported=cephx This is insecure because the key is visible in the OS process listing.

[Qemu-devel] [PATCH v4 0/3] Use QCryptoSecret for block device passwords

This series was previously posted: v1: https://lists.gnu.org/archive/html/qemu-devel/2015-10/msg04365.html v2: https://lists.gnu.org/archive/html/qemu-devel/2015-12/msg03809.html v3: https://lists.gnu.org/archive/html/qemu-devel/2016-01/msg03461.html The RBD, Curl and iSCSI block device

[Qemu-devel] [PULL 26/36] hw/arm/virt: Add always-on property to the virt board timer

From: Christoffer Dall The virt board has an arch timer, which is always on. Emit the "always-on" property to indicate to Linux that it can switch off the periodic timer and reduces the amount of interrupts injected into a guest. Signed-off-by: Christoffer Dall

Re: [Qemu-devel] [PATCH v5 0/4] Extend TPM support with a QEMU-external TPM

* Stefan Berger (stef...@us.ibm.com) wrote: > "Dr. David Alan Gilbert" wrote on 01/21/2016 > 06:40:35 AM: > > > > > * Stefan Berger (stef...@us.ibm.com) wrote: > > > Stefan Berger/Watson/IBM wrote on 01/20/2016 02:51:58 PM: > > > > > > > "Daniel P. Berrange"

[Qemu-devel] [PULL 25/36] hw/arm/virt: add secure memory region and UART

Add a secure memory region to the virt board, which is the same as the nonsecure memory region except that it also has a secure-only UART in it. This is only created if the board is started with the '-machine secure=on' property. Signed-off-by: Peter Maydell Acked-by:

[Qemu-devel] [PULL 36/36] target-arm: Implement FPEXC32_EL2 system register

The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3, and allows those exception levels to read and write the FPEXC register for a lower exception level that is using AArch32. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias

[Qemu-devel] [PULL 01/36] qdev: get_child_bus(): Use QOM lookup if available

From: Peter Crosthwaite qbus_realize() adds busses as a QOM child of the device in addition to adding it to the qdev bus list. Change get_child_bus() to use the QOM child if it is available. This takes priority over the bus-list, but the child object is checked for

[Qemu-devel] [PULL 00/12] X86 queue, 2016-01-21

The following changes since commit 3c9331c47f4118d5019b0af8eac704824d8d: Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2016-01-21 13:09:47 +) are available in the git repository at: git://github.com/ehabkost/qemu.git tags/x86-pull-request for you to

[Qemu-devel] [PULL 03/12] target-i386: Use a _q array on MMXReg too

Make MMXReg use the same field names used on XMMReg, so we can try to reuse macros and other code later. Signed-off-by: Eduardo Habkost --- target-i386/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index

Re: [Qemu-devel] [PATCH v3 09/13] nbd: pick first exported volume if no export name is requested

On Thu, Jan 21, 2016 at 11:30:35AM +0100, Paolo Bonzini wrote: > > > On 19/01/2016 17:44, Daniel P. Berrange wrote: > >> > As a first reaction, I would really avoid magic unless the server > >> > provides a single exports. But even in that case, I would prefer to > >> > have some

[Qemu-devel] [PULL 28/36] target-arm: Properly support EL2 and EL3 in arm_el_is_aa64()

Support EL2 and EL3 in arm_el_is_aa64() by implementing the logic for checking the SCR_EL3 and HCR_EL2 register-width bits as appropriate to determine the register width of lower exception levels. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias

[Qemu-devel] [PULL 30/36] target-arm: Use a single entry point for AArch64 and AArch32 exceptions

If EL2 or EL3 is present on an AArch64 CPU, then exceptions can be taken to an exception level which is running AArch32 (if only EL0 and EL1 are present then EL1 must be AArch64 and all exceptions are taken to AArch64). To support this we need to have a single implementation of the CPU

[Qemu-devel] [PULL 33/36] target-arm: Handle exception return from AArch64 to non-EL0 AArch32

Remove the assumptions that the AArch64 exception return code was making about a return to AArch32 always being a return to EL0. This includes pulling out the illegal-SPSR checks so we can apply them for return to 32 bit as well as return to 64-bit. Signed-off-by: Peter Maydell

[Qemu-devel] [PULL 24/36] hw/arm/virt: Wire up memory region to CPUs explicitly

Wire up the system memory region to the CPUs explicitly by setting the QOM property. This doesn't change anything over letting it default, but will be needed for adding a secure memory region later. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias

[Qemu-devel] [PULL 12/36] cpu: Add new asidx_from_attrs() method

Add a new method to CPUClass which the memory system core can use to obtain the correct address space index to use for a memory access with a given set of transaction attributes, together with the wrapper function cpu_asidx_from_attrs() which implements the default behaviour ("always use asidx 0")

[Qemu-devel] [PULL 18/36] memory: Add address_space_init_shareable()

From: Peter Crosthwaite This will either create a new AS or return a pointer to an already existing equivalent one, if we have already created an AS for the specified root memory region. The motivation is to reuse address spaces as much as possible. It's going to

[Qemu-devel] [PULL 29/36] target-arm: Move aarch64_cpu_do_interrupt() to helper.c

Move the aarch64_cpu_do_interrupt() function to helper.c. We want to be able to call this from code that isn't AArch64-only, and the move allows us to avoid awkward #ifdeffery at the callsite. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias

[Qemu-devel] [PULL 05/36] xlnx-zynqmp: Connect the SPI devices

From: Alistair Francis Connect the Xilinx SPI devices to the ZynqMP model. Signed-off-by: Alistair Francis Reviewed-by: Peter Crosthwaite [ PC changes * Use QOM alias for bus connectivity on SoC level ]

[Qemu-devel] [PULL 04/12] target-i386: Rename struct XMMReg to ZMMReg

The struct represents a 512-bit register, so name it accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost --- target-i386/cpu.h| 6 ++-- target-i386/machine.c| 40 ++---

Re: [Qemu-devel] [Qemu-block] [PATCH v4 00/12] fdc: fix 2.88mb floppy diskette support

On 01/21/2016 05:53 AM, Roman Kagan wrote: > On Wed, Jan 20, 2016 at 02:40:14PM -0500, John Snow wrote: >> On 01/20/2016 02:55 AM, Denis V. Lunev wrote: >>> should we recreate ACPI tables after geometry switch? >>> This would be especially interesting for the case of >>> Win2k12 (or Win8.1 if

[Qemu-devel] [PULL 17/36] exec.c: Use correct AddressSpace in watch_mem_read and watch_mem_write

In the watchpoint access routines watch_mem_read and watch_mem_write, find the correct AddressSpace to use from current_cpu and the memory transaction attributes, rather than always assuming address_space_memory. Signed-off-by: Peter Maydell Acked-by: Edgar E. Iglesias

[Qemu-devel] [PULL 08/12] target-i386: Add suffixes to MMReg struct fields

This will ensure we never use the MMX_* and ZMM_* macros with the wrong struct type. Reviewed-by: Richard Henderson Signed-off-by: Eduardo Habkost --- target-i386/cpu.h | 66 +++ 1 file changed, 33

[Qemu-devel] [PULL 02/12] target-i386/ops_sse.h: Use MMX_Q macro

We have a MMX_Q macro in addition to MMX_{B,W,L}. Use it. Signed-off-by: Eduardo Habkost --- target-i386/ops_sse.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-i386/ops_sse.h b/target-i386/ops_sse.h index 1780d1d..52ec0b0 100644 ---

Re: [Qemu-devel] [PATCH v2 00/19] ISA DMA controllers cleanup (i8257, i82374)

On 01/21/2016 05:21 AM, Paolo Bonzini wrote: > On 20/01/2016 21:31, Hervé Poussineau wrote: >> Ping. >> >> Hervé >> >> Le 10/01/2016 16:24, Hervé Poussineau a écrit : >>> Hi, >>> >>> This patchset is a cleanup of the i8257/i82374 ISA DMA controllers. >>> Global DMA_* functions will be obsoleted

[Qemu-devel] [PULL 27/36] arm_gic: Update ID registers based on revision

From: Alistair Francis Update the GIC ID registers (registers above 0xfe0) based on the GIC revision instead of using the sames values for all GIC implementations. Signed-off-by: Alistair Francis Tested-by: Sören Brinkmann

[Qemu-devel] [PULL 34/36] target-arm: Implement remaining illegal return event checks

We already implement almost all the checks for the illegal return events from AArch64 state described in the ARM ARM section D1.11.2. Add the two missing ones: * return to EL2 when EL3 is implemented and SCR_EL3.NS is 0 * return to Non-secure EL1 when EL2 is implemented and HCR_EL2.TGE is 1 (We

[Qemu-devel] [PULL 08/36] exec.c: Don't set cpu->as until cpu_address_space_init

Rather than setting cpu->as unconditionally in cpu_exec_init (and then having target-i386 override this later), don't set it until the first call to cpu_address_space_init. This requires us to initialise the address space for both TCG and KVM (KVM doesn't need the AS listener but it does require

[Qemu-devel] [PULL 16/36] exec.c: Use cpu_get_phys_page_attrs_debug

Use cpu_get_phys_page_attrs_debug() when doing virtual-to-physical conversions in debug related code, so that we can obtain the right address space index and thus select the correct AddressSpace, rather than always using cpu->as. Signed-off-by: Peter Maydell Acked-by:

[Qemu-devel] [PULL 02/36] m25p80.c: Add sst25wf080 SPI flash device

From: Alistair Francis Add the sst25wf080 SPI flash device. Signed-off-by: Alistair Francis Reviewed-by: Peter Crosthwaite Signed-off-by: Peter Crosthwaite Signed-off-by: Peter

Re: [Qemu-devel] [PATCH v2 0/4] blockdev: Fix 'change' for slot devices

On 20 January 2016 at 18:29, Max Reitz wrote: > The series "BlockBackend and media" intended all block devices with > removable media to implement a tray model; if the devices does not have > a tray, it should emulate one. > Patches 1 and 2 are CC'd to qemu-stable because they

[Qemu-devel] [PATCH v4 2/3] curl: add support for HTTP authentication parameters

If connecting to a web server which has authentication turned on, QEMU gets a 401 as curl has not been configured with any authentication credentials. This adds 4 new parameters to the curl block driver options 'username', 'password-secret', 'proxy-username' and 'proxy-password-secret'. Passwords

[Qemu-devel] [PULL 14/36] exec.c: Pass MemTxAttrs to iotlb_to_region so it uses the right AS

Pass the MemTxAttrs for the memory access to iotlb_to_region(); this allows it to determine the correct AddressSpace to use for the lookup. Signed-off-by: Peter Maydell Acked-by: Edgar E. Iglesias --- cputlb.c| 6 --

[Qemu-devel] [PULL 15/36] exec.c: Add cpu_get_address_space()

Add a function to return the AddressSpace for a CPU based on its numerical index. (Callers outside exec.c don't have access to the CPUAddressSpace struct so can't just fish it out of the CPUState struct directly.) Signed-off-by: Peter Maydell Acked-by: Edgar E. Iglesias

[Qemu-devel] [PULL 09/36] exec.c: Allow target CPUs to define multiple AddressSpaces

Allow multiple calls to cpu_address_space_init(); each call adds an entry to the cpu->ases array at the specified index. It is up to the target-specific CPU code to actually use these extra address spaces. Since this multiple AddressSpace support won't work with KVM, add an assertion to avoid

[Qemu-devel] [PULL 10/12] target-i386: Reorganize TSC rate setting code

From: Haozhong Zhang Following changes are made to the TSC rate setting code in kvm_arch_init_vcpu(): * The code is moved to a new function kvm_arch_set_tsc_khz(). * If kvm_arch_set_tsc_khz() fails, i.e. following two conditions are both satisfied: * KVM does

Re: [Qemu-devel] [PATCH v1 3/3] target-arm: Implement the S2 MMU inputsize < pamax check

On Thu, Jan 21, 2016 at 12:52:54PM +, Alex Bennée wrote: > > Edgar E. Iglesias writes: > > > On Wed, Jan 20, 2016 at 02:49:40PM +0100, Edgar E. Iglesias wrote: > >> From: "Edgar E. Iglesias" > >> > >> Implement the inputsize < pamax

[Qemu-devel] [PULL 11/12] target-i386: Add support to migrate vcpu's TSC rate

From: Haozhong Zhang This patch enables migrating vcpu's TSC rate. If KVM on the destination machine supports TSC scaling, guest programs will observe a consistent TSC rate across the migration. If TSC scaling is not supported on the destination machine, the migration

Re: [Qemu-devel] [PATCH v6 0/6] Xen PCI passthru: Convert to realize()

Hi Cao, I appreciate the reminder, but it looks like Eric hasn't reviewed patch 3/5. Am I wrong? On Thu, 21 Jan 2016, Cao jin wrote: > Hi Stefano, > > Just FYI: The series have been reviewed by Eric, I guess it could be > picked up;) > > On 01/17/2016 08:13 PM, Cao jin wrote: > > v6

[Qemu-devel] [PULL 23/36] target-arm: Support multiple address spaces in page table walks

If we have a secure address space, use it in page table walks: when doing the physical accesses to read descriptors, make them through the correct address space. (The descriptor reads are the only direct physical accesses made in target-arm/ for CPUs which might have TrustZone.) Signed-off-by:

[Qemu-devel] [PULL 31/36] target-arm: Pull semihosting handling out to arm_cpu_do_interrupt()

Handling of semihosting calls should depend on the register width of the calling code, not on that of any higher exception level, so we need to identify and handle semihosting calls before we decide whether to deliver the exception as an entry to AArch32 or AArch64. (EXCP_SEMIHOST is also an

[Qemu-devel] [PULL 05/12] target-i386: Rename XMM_[BWLSDQ] helpers to ZMM_*

They are helpers for the ZMMReg fields, so name them accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost --- target-i386/cpu.h| 24 ++-- target-i386/fpu_helper.c | 8 +- target-i386/gdbstub.c

[Qemu-devel] [PULL 03/36] ssi: Move ssi.h into a separate directory

From: Alistair Francis Move the ssi.h include file into the ssi directory. While touching the code also fix the typdef lines as checkpatch complains. Signed-off-by: Alistair Francis Reviewed-by: Peter Crosthwaite

[Qemu-devel] [PULL 06/12] target-i386: Define MMXReg._d field

Add a new field and reorder MMXReg fields, to make MMXReg and ZMMReg field lists look the same (except for the array sizes). Signed-off-by: Eduardo Habkost --- target-i386/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target-i386/cpu.h

[Qemu-devel] [PULL 09/12] target-i386: Fallback vcpu's TSC rate to value returned by KVM

From: Haozhong Zhang If no user-specified TSC rate is present, we will try to set env->tsc_khz to the value returned by KVM_GET_TSC_KHZ. This patch does not change the current functionality of QEMU and just prepares for later patches to enable migrating vcpu's TSC rate.

[Qemu-devel] [PATCH v4 01/14] nbd: convert block client to use I/O channels for connection setup

This converts the NBD block driver client to use the QIOChannelSocket class for initial connection setup. The NbdClientSession struct has two pointers, one to the master QIOChannelSocket providing the raw data channel, and one to a QIOChannel which is the current channel used for I/O. Initially

[Qemu-devel] [PATCH v4 08/14] nbd: allow setting of an export name for qemu-nbd server

The qemu-nbd server currently always uses the old style protocol since it never sets any export name. This is a problem because future TLS support will require use of the new style protocol negotiation. This adds "--exportname NAME" / "-x NAME" arguments to qemu-nbd which allow the user to set an

[Qemu-devel] [PULL 06/11] Change xen_host_pci_sysfs_path() to return void

From: Cao jin And assert the snprintf() error, because user can do nothing in case of snprintf() fail. Signed-off-by: Cao jin Reviewed-by: Stefano Stabellini Reviewed-by: Eric Blake ---

[Qemu-devel] [PULL 10/11] Add Error **errp for xen_pt_config_init()

From: Cao jin To catch the error message. Also modify the caller Signed-off-by: Cao jin Reviewed-by: Eric Blake Reviewed-by: Stefano Stabellini --- hw/xen/xen_pt.c |8

[Qemu-devel] [PULL 03/11] xen-hvm: Clean up xen_hvm_init() error handling

From: Markus Armbruster xen_hvm_init() returns -1 without cleaning up on some errors (harmless long as the caller exit()s on error), dies with hw_error() on others. hw_error() isn't approprate here. Clean up to exit() on all errors. Signed-off-by: Markus Armbruster

[Qemu-devel] [PATCH v2 5/9] ipmi: fix SDR length value

The IPMI BMC simulator populates the SDR table with a set of initial SDRs. The length of each SDR is taken from the record itself (byte 4) which does not include the size of the header. But, the full length (header + data) is required by the sdr_add_entry() routine. Signed-off-by: Cédric Le

[Qemu-devel] [PATCH v2 2/9] ipmi: replace goto by a return statement

Each routine using the IPMI_ADD_RSP_DATA, IPMI_CHECK_CMD_LEN or IPMI_CHECK_RESERVATION macros needs to define a goto label 'out' to handle hidden errors. Using directly a return statement as the same effect and it removes the fact that 'out' needs to be defined. The code exits in

Re: [Qemu-devel] [PATCH v6 3/6] Add Error **errp for xen_host_pci_device_get()

On 01/17/2016 05:13 AM, Cao jin wrote: > To catch the error message. Also modify the caller > > Signed-off-by: Cao jin > --- > hw/xen/xen-host-pci-device.c | 102 > --- > hw/xen/xen-host-pci-device.h | 5 ++- > hw/xen/xen_pt.c

Re: [Qemu-devel] [PATCH v6 0/6] Xen PCI passthru: Convert to realize()

On Thu, 21 Jan 2016, Eric Blake wrote: > On 01/21/2016 08:41 AM, Stefano Stabellini wrote: > > Hi Cao, > > > > I appreciate the reminder, but it looks like Eric hasn't reviewed patch > > 3/5. Am I wrong? > > I've done it now. Thanks for your patience, and for letting me jump in > with a late

Re: [Qemu-devel] [PATCH v9 2/3] quorum: implement bdrv_add_child() and bdrv_del_child()

On 01/21/2016 06:05 AM, Alberto Garcia wrote: > On Thu 21 Jan 2016 02:54:10 AM CET, Wen Congyang wrote: > @@ -875,9 +878,9 @@ static int quorum_open(BlockDriverState *bs, QDict *options, int flags, ret = -EINVAL; goto exit; }

[Qemu-devel] [PULL 09/11] Add Error **errp for xen_pt_setup_vga()

From: Cao jin To catch the error message. Also modify the caller Signed-off-by: Cao jin Reviewed-by: Eric Blake Reviewed-by: Stefano Stabellini --- hw/xen/xen_pt.c |7

[Qemu-devel] [PULL 02/11] xenfb.c: avoid expensive loops when prod <= out_cons

If the frontend sets out_cons to a value higher than out_prod, it will cause xenfb_handle_events to loop about 2^32 times. Avoid that by using better checks at the beginning of the function. Signed-off-by: Stefano Stabellini Reported-by: Ling Liu

[Qemu-devel] [PATCH v2 0/9] ipmi: a couple of enhancements to the BMC simulator

Hi, Here are a few patches adding a couple of IPMI commands to the BMC simulator. Changes since v1: - Added IPMI to ppc. We will need it for the future powernv platform. - Added some initial cleanups - Kept FRU, the API extensions to expose SDR and generate events for later, may be

[Qemu-devel] [PATCH v2 1/9] ppc: add IPMI support

Open PowerNV systems use a BT device to communicate with the BMC. Provide support for it. Signed-off-by: Cédric Le Goater --- default-configs/ppc64-softmmu.mak | 4 1 file changed, 4 insertions(+) diff --git a/default-configs/ppc64-softmmu.mak

[Qemu-devel] [PATCH v2 7/9] ipmi: add GET_SYS_RESTART_CAUSE chassis command

This is a simulator. Just return an unknown cause (0). Signed-off-by: Cédric Le Goater Acked-by: Corey Minyard --- hw/ipmi/ipmi_bmc_sim.c | 16 +++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/hw/ipmi/ipmi_bmc_sim.c

[Qemu-devel] [PATCH v2 3/9] ipmi: replace *_MAXCMD defines

ARRAY_SIZE() is simple to use and removes the need to pre-define the size of the command arrays. Signed-off-by: Cédric Le Goater --- hw/ipmi/ipmi_bmc_sim.c | 21 - 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/hw/ipmi/ipmi_bmc_sim.c

Re: [Qemu-devel] [PATCH v6 12/15] block: Use returned *file in bdrv_co_get_block_status

On 08.01.2016 03:08, Fam Zheng wrote: > Now that all drivers return the right "file" pointer, we can use it. > > Signed-off-by: Fam Zheng > --- > block/io.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Max Reitz signature.asc

[Qemu-devel] [PATCH v4 04/14] nbd: convert to using I/O channels for actual socket I/O

Now that all callers are converted to use I/O channels for initial connection setup, it is possible to switch the core NBD protocol handling core over to use QIOChannel APIs for actual sockets I/O. Signed-off-by: Daniel P. Berrange --- block/nbd-client.c | 19 +++

[Qemu-devel] [PATCH v4 07/14] nbd: make client request fixed new style if advertized

If the server advertizes support for the fixed new style negotiation, the client should in turn enable new style. This will allow the client to negotiate further NBD options besides the export name. Signed-off-by: Daniel P. Berrange --- nbd/client.c | 27

[Qemu-devel] [PULL 01/11] MAINTAINERS: update Xen files

Add the PV block backend, the Xen mapcache, and hw/i386/xen to the list of Xen related files maintained by me. Signed-off-by: Stefano Stabellini Reviewed-by: Markus Armbruster --- MAINTAINERS |3 +++ 1 file changed, 3 insertions(+) diff

[Qemu-devel] [PULL 05/11] xen-pvdevice: convert to realize()

From: Cao jin Signed-off-by: Cao jin Reviewed-by: Stefano Stabellini --- hw/i386/xen/xen_pvdevice.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git

[Qemu-devel] [PULL 0/11] xen-20160121

/xen-20160121 for you to fetch changes up to 5a11d0f7549e24a10e178a9dc8ff5e698031d9a6: Xen PCI passthru: convert to realize() (2016-01-21 16:45:54 +) Xen 2016/01/21

[Qemu-devel] [PULL 08/11] Add Error **errp for xen_host_pci_device_get()

From: Cao jin To catch the error message. Also modify the caller Signed-off-by: Cao jin Reviewed-by: Stefano Stabellini Reviewed-by: Eric Blake --- hw/xen/xen-host-pci-device.c | 102

[Qemu-devel] [PATCH v2 9/9] ipmi: add SET_SENSOR_READING command (tentative try)

SET_SENSOR_READING is a complex IPMI command (IPMI spec : "35.17 Set Sensor Reading And Event Status Command"). Here is a very minimum framework fitting the Open PowerNV platform needs. This command is used on this platform to set the "System Firmware Progress" sensor and the "Boot Count" sensor.

Re: [Qemu-devel] [PATCH v9 10/37] qapi: Make all visitors supply uint64 callbacks

On 01/21/2016 01:56 AM, Markus Armbruster wrote: >>> Before: nobody implements type_uint64(), and the core falls back to >>> type_int64(), casting negative values to large positive ones. With an >>> implementation of type_int64() that parses large positive values as >>> negative, the two casts

[Qemu-devel] [PULL 11/11] Xen PCI passthru: convert to realize()

From: Cao jin Signed-off-by: Cao jin Reviewed-by: Eric Blake Reviewed-by: Stefano Stabellini --- hw/xen/xen_pt.c | 53 - 1 file

Re: [Qemu-devel] [PATCH v3 02/10] qemu-img: add support for --object command line arg

On Tue, Jan 19, 2016 at 10:37:04AM +, Daniel P. Berrange wrote: > Allow creation of user creatable object types with qemu-img > via a new --object command line arg. This will be used to supply > passwords and/or encryption keys to the various block driver > backends via the recently added

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