The previously missing registers are now present in QEMU.
Signed-off-by: Christopher Covington
Signed-off-by: Alistair Francis
---
target-arm/helper.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index b4bf6fa..1775768 1006
This patch adds the following registers including read and write functions:
PMSELR, PMSELR_EL0, PMXEVCNTR, PMXEVCNTR_EL0, PMXEVTYPER and PMXEVTYPER_EL0.
Signed-off-by: Aaron Lindsay
Signed-off-by: Alistair Francis
Tested-by: Nathan Rossi
---
target-arm/cpu.h| 6
target-arm/helper.c
The Linux kernel accesses this register early in its setup.
Signed-off-by: Christopher Covington
Signed-off-by: Alistair Francis
---
target-arm/helper.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 8d401c6..b4bf6fa 100644
--- a/targe
Signed-off-by: Aaron Lindsay
Signed-off-by: Alistair Francis
Tested-by: Nathan Rossi
---
target-arm/cpu-qom.h | 2 ++
target-arm/cpu.c | 2 ++
target-arm/cpu64.c | 2 ++
target-arm/helper.c | 8
4 files changed, 14 insertions(+)
diff --git a/target-arm/cpu-qom.h b/target-arm/c
Signed-off-by: Aaron Lindsay
Signed-off-by: Alistair Francis
Tested-by: Nathan Rossi
---
target-arm/helper.c | 12
1 file changed, 12 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 164853f..8d401c6 100644
--- a/target-arm/helper.c
+++ b/target-arm/help
This patch set is based on the patch sent by Christopher Covington and
written by Aaron Lindsay which was sent as an RFC (Implement remaining
PMU functionality).
It adds a few performance monitoring related registers.
V2:
- Add Aaron to the signed off lines
- Add the tested-by lines from Nathan
On 01/27/2016 05:17 AM, Peter Maydell wrote:
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 0ed10a9..8467d5d 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -10,6 +10,7 @@
* See the COPYING file in the top-level directory for details.
*/
+#in
On 01/27/2016 05:17 AM, Peter Maydell wrote:
Clean up includes so that osdep.h is included first and headers
which it implies are not included manually.
This commit was created with scripts/clean-includes.
Signed-off-by: Peter Maydell
---
disas/alpha.c | 2 +-
hw/alpha/dp264.c
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index ee3e9dd..38b0883 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1749,10 +1749,9 @@ static void temp_sync(TCGCont
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 55 ---
1 file changed, 28 insertions(+), 27 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index bd3707b..ee3e9dd 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1722,29
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 113 ++
tcg/tcg.h | 6 ++--
2 files changed, 57 insertions(+), 62 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index a20b730..baa8a14 100644
--- a/tcg/tc
Thus, use cpu_env as the parameter, not TCG_AREG0 directly.
Update all uses in the translators.
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Henderson
---
target-alpha/translate.c | 8 ++---
target-arm/translate-a64.c| 6 ++--
target-arm/translate.c| 18 +-
targ
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 26 +++---
tcg/tcg.h | 8
2 files changed, 19 insertions(+), 15 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 9a836c9..b50919a 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -448,7 +448
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 48 +++-
1 file changed, 23 insertions(+), 25 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index baa8a14..bd3707b 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1708,20 +1708,
Chain the temporaries together via pointers intstead of indices.
The mem_reg value is now mem_base->reg. This will be important later.
This does require that the frame pointer have a global temporary
allocated for it. This is simple bar the existing reserved_regs check.
Reviewed-by: Aurelien Ja
Unify all of the places that realize a temporary into a register.
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 116 --
1 file changed, 52 insertions(+), 64 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.
Three in comments and one in code in the stub tcg_liveness_analysis.
Signed-off-by: Richard Henderson
---
target-arm/translate.c | 3 +--
target-i386/translate.c | 3 +--
target-unicore32/translate.c | 3 +--
tcg/tcg.c| 3 +--
4 files changed, 4 insertions(+), 8 de
In particular, make sure the memory is memset before use.
Continues the increased use of TCGTemp pointers instead of
integer indices where appropriate.
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 123 --
Undo the workaround at b17a6d3390f87620735f7efb03bb1c96682ff449.
If there are lots of memory operations in a TB, the slow path code
can exceed the highwater reservation. Add a check within the loop.
Tested-by: Aurelien Jarno
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Henderson
---
tc
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 10 --
tcg/tcg.h | 5 -
2 files changed, 15 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index b50919a..a20b730 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -923,16 +923,6 @@ static char *tcg_get_arg_str_i
This contains two patches from December, and the portion that
has been reviewed of my tcg-indirect-register series for sparc.
The latter is mostly cleanup to tcg.c and so is nice to have
regardless of the rest of the patch set.
r~
The following changes since commit ee8e8f92a730afc17ab8be6e86df6
On 01/20/2016 10:38 AM, Daniel P. Berrange wrote:
> Instead of requiring separate input/output buffers for
> encrypting data, change qcow2_encrypt_sectors() to assume
> use of a single buffer, encrypting in place. The current
> callers all used the same buffer for input/output already.
>
> Signed-
On 01/20/2016 10:38 AM, Daniel P. Berrange wrote:
> Add a block driver that is capable of supporting any full disk
> encryption format. This utilizes the previously added block
> encryption code, and at this time supports the LUKS format.
>
> The driver code is capable of supporting any format sup
n .travis.yml -- probably easy enough to fix up but
>> since I don't know anything about the travis syntax or how to test it,
>> could you rebase and fix up the conflict, please?
>
> I've pushed a signed tags/pull-build-test-20160205 but I'm still waiting
> for t
getrandom() has been introduced in kernel 3.17 and is now used during
the boot sequence of Debian unstable (stretch/sid).
Signed-off-by: Laurent Vivier
---
linux-user/syscall.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index da
On 02/05/2016 11:12 AM, John Snow wrote:
> Commit 16b0d555 introduced an issue where we are not initializing
> has_filename for the 'next' MapEntry object, which leads to interesting
> errors in Valgrind and Clang -fsanitize=undefined both.
grammar:
errors in both Valgrind and Clang -fsanitize=un
On 01/20/2016 10:38 AM, Daniel P. Berrange wrote:
> The qemu-img/qemu-io tools prompt for disk encryption passwords
> regardless of whether any are actually required. Adding a check
> on bdrv_key_required() avoids this prompt for disk formats which
> have been converted to the QCryptoSecret APIs.
>
On 01/22/2016 12:07 PM, Vladimir Sementsov-Ogievskiy wrote:
> Hi all.
>
> This is the early begin of the series which aims to add external backup
> api. This is needed to allow backup software use our dirty bitmaps.
>
> Vmware and Parallels Cloud Server have this feature.
>
Have a link to the
On Thu, 4 Feb 2016 23:54:13 +0200
"Michael S. Tsirkin" wrote:
> From: Roman Kagan
>
> On x86-based systems Linux determines the presence
> and the type of floppy drives via a query of a CMOS field.
> So does SeaBIOS when populating the return data for
> int 0x13 function 0x08.
>
> However Wind
On Fri, 5 Feb 2016 15:03:55 +
Peter Maydell wrote:
> On 4 February 2016 at 21:50, Michael S. Tsirkin wrote:
> > The following changes since commit 382d34ff9fcc534db32d54eb82590de7c04f9b33:
> >
> > Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request'
> > into staging (
When APIC IDs are sparse*, in addition to valid LAPIC
antries the SRAT is also filled invalid ones for non
posiible APIC IDs.
Fix it by asking machine for all possible APIC IDs
instead of wrongly assuming that all APIC IDs in
range 0..apic_id_limit are possible.
* sparse lapic topology CLI:
-
On 01/20/2016 10:38 AM, Daniel P. Berrange wrote:
> When opening an image it is useful to know whether the caller
> intends to perform I/O on the image or not. In the case of
> encrypted images this will allow the block driver to avoid
> having to prompt for decryption keys when we merely want to
>
On 02/05/2016 05:43 AM, Daniel P. Berrange wrote:
> On Thu, Feb 04, 2016 at 05:23:32PM -0700, Eric Blake wrote:
>> On 01/20/2016 10:38 AM, Daniel P. Berrange wrote:
>>> Add a generic framework for support different block encryption
>>> formats. Upon instantiating a QCryptoBlock object, it will read
* Daniel P. Berrange (berra...@redhat.com) wrote:
> Now that the memory buffer based QEMUFile impl is gone, there
> is no need for any backend to be accessing internals of the
> QEMUFile struct, so it can be moved back into qemu-file.c
>
> Signed-off-by: Daniel P. Berrange
Reviewed-by: Dr. David
On 01/20/2016 10:38 AM, Daniel P. Berrange wrote:
> Provide a block encryption implementation that follows the
> LUKS/dm-crypt specification.
>
> This supports all combinations of hash, cipher algorithm,
> cipher mode and iv generator that are implemented by the
> current crypto layer.
>
> The no
cpu->found_cpus bitmap is used for setting present
flag in CPON AML package. But it takes a bunch of code
to fill bitmap and could be simplified by getting
presense info from possible CPUs list directly.
So move found_cpus bitmap to the only place that uses
it for building sparse CPON AML package.
Signed-off-by: Igor Mammedov
---
hw/i386/pc.c | 45 +++--
1 file changed, 19 insertions(+), 26 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 548ec64..b863265 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -700,18 +700,6 @@ static uint32_t x8
call qdev_get_machine() once at acpi_build() and
pass its result to child functions that need it.
Signed-off-by: Igor Mammedov
Reviewed-by: Marcel Apfelbaum
---
hw/i386/acpi-build.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/
Commit 16b0d555 introduced an issue where we are not initializing
has_filename for the 'next' MapEntry object, which leads to interesting
errors in Valgrind and Clang -fsanitize=undefined both.
Zero the stack object at allocation AND make sure the utility to
populate the fields properly marks has_
Signed-off-by: Igor Mammedov
---
hw/i386/acpi-build.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 5fc8019..7ac46f4 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -2426,7 +2426,6 @@ build_srat(GArray *table_data, GArray *lin
do not assume that all lapics in range 0..apic_id_limit
are valid and do not create Processor and Notify objects
for not possible lapics.
Signed-off-by: Igor Mammedov
Reviewed-by: Eduardo Habkost
---
hw/i386/acpi-build.c | 41 ++---
1 file changed, 26 inserti
do not assume that all lapics in range 0..apic_id_limit
are valid and do not create lapic entries for not
possible lapics in MADT.
Signed-off-by: Igor Mammedov
---
hw/i386/acpi-build.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/hw/i386/acpi-build.c b
Changes since v1:
- rebased on top of PCI tree that contains
Eduardo's guest_info removel series
- fix ^2 times present CPU lookup when creating CPON
package (spotted-by: Eduardo Habkost )
It's mostly clean up series that removes invalid CPU
entries from MADT/DSDT/SRAT tables when APIC ID
on x86 currently range 0..max_cpus is used to generate
architecture-dependent CPU ID (APIC Id) for each present
and possible CPUs. However architecture-dependent CPU IDs
list could be sparse and code that needs to enumerate
all IDs (ACPI) ended up doing guess work enumerating all
possible and impos
Signed-off-by: Igor Mammedov
Reviewed-by: Eduardo Habkost
---
hw/i386/acpi-build.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 6ac05b3..5fc8019 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -363,6 +363,12 @@ build_
cpu_exists() already does CPU lookup but
discards found CPU and returns boolean instead.
Make it more useful by returning a found CPU
and also rename it more descriptive name.
Signed-off-by: Igor Mammedov
Reviewed-by: Eduardo Habkost
---
hw/i386/pc.c | 2 +-
include/qom/cpu.h | 10 +--
Implement the traps to EL2 and EL3 controlled by the bits
MDCR_EL2.TDOSA MDCR_EL3.TDOSA. These can configurably trap
accesses to the "powerdown debug" registers.
Signed-off-by: Peter Maydell
---
target-arm/cpu.h| 12
target-arm/helper.c | 23 ++-
2 files chan
gt; I had a momentary panic when I saw the email messages still had ---
>> history on them but the tag is clean and can be pulled.
>
> Merge conflict in .travis.yml -- probably easy enough to fix up but
> since I don't know anything about the travis syntax or how to test it,
>
This patchset fixes or implements a lot of traps to EL3 as
listed in the ARM ARM section D1.15.4 "EL3 configurable controls".
Most of the rest we already had implemented.
NB: where the trap I was implementing for EL3 had an
obvious equivalent in EL2 I included the EL2 check in this
series, but I h
On Fri, 5 Feb 2016 17:19:50 +0100
Igor Mammedov wrote:
> On Fri, 5 Feb 2016 13:39:07 -0200
> Eduardo Habkost wrote:
>
> > On Thu, Feb 04, 2016 at 12:47:33PM +0100, Igor Mammedov wrote:
> > > cpu->found_cpus bitmap is used for setting present
> > > flag in CPON AML package at start up. But it
Correct some corner cases we were getting wrong for
CNTFRQ access rights:
* should UNDEF from 32-bit Secure EL1
* only writable from the highest implemented exception level,
which might not be EL1 now
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 31 ---
We weren't quite implementing the handling of SCR.SMD correctly.
The condition governing whether the SMD bit should apply only
for NS state is "is EL3 is AArch32", not "is the current EL AArch32".
Fix the condition, and clarify the comment both to reflect this and
to expand slightly on what's going
Implement the debug register traps controlled by MDCR_EL2.TDA
and MDCR_EL3.TDA.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 39 ++-
1 file changed, 30 insertions(+), 9 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 8c2adb
Implement trapping of the "debug ROM" registers, which are controlled
by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 27 ---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/targe
On 5 February 2016 at 16:55, Aurelio Remonda
wrote:
> Im making something like this:
>
> if (ram_size == 0x800) /* default value, means whitout -m flag */
>{
> sram_size = ((board->dc0 >> 18) + * 1024;
> }
> else if (ram_size >= UINT_MAX) /* more than 4GB */
> sram_size =
El 5 feb. 2016 1:24 PM, "Peter Maydell" escribió:
> On 5 February 2016 at 16:09, Aurelio Remonda
> wrote:
> > Hello, im working on this feature right now.
> > i have a working patch but maybe I can make some changes to make it look
> better:
> > for example in some point i check ram_size like th
If access to FPEXC32_EL2 is trapped by CPTR_EL2.TFP or CPTR_EL3.TFP,
this should be reported with a syndrome register indicating an
FP access trap, not one indicating a system register access trap.
Signed-off-by: Peter Maydell
---
target-arm/cpu.h | 5 +
target-arm/helper.c| 4 ++
On 5 February 2016 at 16:17, Alex Bennée wrote:
>
> Peter Maydell writes:
>> I haven't measured, no, but since there are only 3 arguments the
>> third argument is going to be in a register on any host architecture
>> we care about, which means the overhead is just going to be a single
>> "load co
On 05.02.2016 17:55, Igor Mammedov wrote:
On Fri, 5 Feb 2016 17:09:58 +0300
Vladimir Sementsov-Ogievskiy wrote:
On 05.02.2016 15:58, Igor Mammedov wrote:
On Fri, 5 Feb 2016 11:19:01 +0300
Vladimir Sementsov-Ogievskiy wrote:
For now there are only two dimm's: pc-dimm and nvdimm. This pat
Peter Maydell writes:
> On 5 February 2016 at 16:17, Alex Bennée wrote:
>>
>> Peter Maydell writes:
>>> I haven't measured, no, but since there are only 3 arguments the
>>> third argument is going to be in a register on any host architecture
>>> we care about, which means the overhead is just
Peter Maydell writes:
> On 5 February 2016 at 16:27, Alex Bennée wrote:
>>
>> Alex Bennée writes:
>>
>>> The following changes since commit 357e81c7e880f868833edf9f53cce1f3b09ea8ec:
>>>
>>> Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20160128' into
>>> staging (2016-01-28 11:46:
On 5 February 2016 at 16:26, Alex Bennée wrote:
>
> Fam Zheng writes:
>> Can be a separate patch, though.
>
> As I've already submitted the pull I'll clean it up on the next round.
You told me this morning you were going to resubmit the pull
anyway, so you could fix it up if you wanted.
thanks
Fam Zheng writes:
> On Thu, 02/04 17:12, Alex Bennée wrote:
>> Signed-off-by: Alex Bennée
>> Reviewed-by: David Gibson
>>
>> ---
>> pr: added r-b tags
>> ---
>> MAINTAINERS | 5 +
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index b6ed87a..426a735 100
Alex Bennée writes:
> The following changes since commit 357e81c7e880f868833edf9f53cce1f3b09ea8ec:
>
> Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20160128' into
> staging (2016-01-28 11:46:34 +)
>
> are available in the git repository at:
>
> https://github.com/stsquad/qemu
On Fri, 5 Feb 2016 13:50:05 -0200
Eduardo Habkost wrote:
> On Fri, Feb 05, 2016 at 04:39:46PM +0100, Igor Mammedov wrote:
> > On Fri, 5 Feb 2016 13:04:26 -0200
> > Eduardo Habkost wrote:
> >
> > > On Thu, Feb 04, 2016 at 12:47:28PM +0100, Igor Mammedov wrote:
> > > > on x86 currently range
On 5 February 2016 at 16:07, Alex Bennée wrote:
>
> Peter Maydell writes:
>
>> Implement some corner cases of the behaviour of the NSACR
>> register on ARMv8:
>> * if EL3 is AArch64 then accessing the NSACR from Secure EL1
>>with AArch32 should trap to EL3
>> * if EL3 is not present or is A
On 5 February 2016 at 16:09, Aurelio Remonda
wrote:
> Hello, im working on this feature right now.
> i have a working patch but maybe I can make some changes to make it look
> better:
> for example in some point i check ram_size like this:
> if (ram_size == 0x800)
> Maybe if i make ram_addr_t
On 5 February 2016 at 16:27, Alex Bennée wrote:
>
> Alex Bennée writes:
>
>> The following changes since commit 357e81c7e880f868833edf9f53cce1f3b09ea8ec:
>>
>> Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20160128' into
>> staging (2016-01-28 11:46:34 +)
>>
>> are available in t
On Fri, 5 Feb 2016 13:39:07 -0200
Eduardo Habkost wrote:
> On Thu, Feb 04, 2016 at 12:47:33PM +0100, Igor Mammedov wrote:
> > cpu->found_cpus bitmap is used for setting present
> > flag in CPON AML package at start up. But it takes
> > a bunch of code to fill bitmap and cloud be simplified
> > by
Peter Maydell writes:
> On 5 February 2016 at 14:20, Alex Bennée wrote:
>>
>> Peter Maydell writes:
>>> -typedef CPAccessResult CPAccessFn(CPUARMState *env, const ARMCPRegInfo
>>> *opaque);
>>> +typedef CPAccessResult CPAccessFn(CPUARMState *env,
>>> + const A
On Fri, 5 Feb 2016 13:28:31 -0200
Eduardo Habkost wrote:
> On Thu, Feb 04, 2016 at 12:47:32PM +0100, Igor Mammedov wrote:
> > do not assume that all lapics in range 0..apic_id_limit
> > are valid and do not create lapic entries for not
> > possible lapics in MADT.
> >
> > Signed-off-by: Igor Mam
Hello, im working on this feature right now.
i have a working patch but maybe I can make some changes to make it look better:
for example in some point i check ram_size like this:
if (ram_size == 0x800)
Maybe if i make ram_addr_t default_ram_size global (is a local
variable of set_memory_option
Peter Maydell writes:
> Enable EL3 support for our Cortex-A53 and Cortex-A57 CPU models.
> We have enough implemented now to be able to run real world code
> at least to some extent (I can boot ARM Trusted Firmware to the
> point where it pulls in OP-TEE and then falls over because it
> doesn't
Peter Maydell writes:
> Implement some corner cases of the behaviour of the NSACR
> register on ARMv8:
> * if EL3 is AArch64 then accessing the NSACR from Secure EL1
>with AArch32 should trap to EL3
> * if EL3 is not present or is AArch64 then reads from NS EL1 and
>NS EL2 return const
On 5 February 2016 at 14:09, Alex Bennée wrote:
>
> Peter Maydell writes:
>> @@ -1767,6 +1765,14 @@ static inline int arm_debug_target_el(CPUARMState
>> *env)
>>
>> static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
>> {
>> +if (arm_is_secure(env)) {
>> +/* MDCR_EL
Am 04.02.2016 um 17:35 hat Daniel P. Berrange geschrieben:
> On Thu, Feb 04, 2016 at 05:06:06PM +0100, Kevin Wolf wrote:
> > Am 04.02.2016 um 16:47 hat Daniel P. Berrange geschrieben:
> > > On Thu, Feb 04, 2016 at 04:42:06PM +0100, Kevin Wolf wrote:
> > > > Am 02.02.2016 um 13:57 hat Daniel P. Berr
On Fri, Feb 05, 2016 at 04:39:46PM +0100, Igor Mammedov wrote:
> On Fri, 5 Feb 2016 13:04:26 -0200
> Eduardo Habkost wrote:
>
> > On Thu, Feb 04, 2016 at 12:47:28PM +0100, Igor Mammedov wrote:
> > > on x86 currently range 0..max_cpus is used to generate
> > > architecture-dependent CPU ID (APIC I
Am 05.02.2016 um 14:28 hat Alberto Garcia geschrieben:
> On Fri 05 Feb 2016 03:25:22 AM CET, Changlong Xie
> wrote:
> > Signed-off-by: Wen Congyang
> > Signed-off-by: Changlong Xie
>
> Reviewed-by: Alberto Garcia
Thanks, applied to the block branch.
Kevin
On 02/04/2016 07:25 PM, Changlong Xie wrote:
> Signed-off-by: Wen Congyang
> Signed-off-by: Changlong Xie
> ---
> block/quorum.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/block/quorum.c b/block/quorum.c
> index a5ae4b8..11cc60b 100644
> --- a/block/quorum.c
> ++
On Fri, 5 Feb 2016 13:17:14 -0200
Eduardo Habkost wrote:
> On Thu, Feb 04, 2016 at 12:47:31PM +0100, Igor Mammedov wrote:
> > do not assume that all lapics in range 0..apic_id_limit
> > are valid and do not create Processor and Notify objects
> > for not possible lapics.
> >
> > Signed-off-by: I
On Fri, 5 Feb 2016 12:33:44 +0100
Cornelia Huck wrote:
> On Fri, 05 Feb 2016 11:43:11 +0100
> Greg Kurz wrote:
>
> > +static bool virtio_net_set_vnet_endian(VirtIODevice *vdev, NetClientState
> > *ncs,
> > + int queues, bool enable)
>
> You might consid
On Fri, 5 Feb 2016 13:04:26 -0200
Eduardo Habkost wrote:
> On Thu, Feb 04, 2016 at 12:47:28PM +0100, Igor Mammedov wrote:
> > on x86 currently range 0..max_cpus is used to generate
> > architecture-dependent CPU ID (APIC Id) for each present
> > and possible CPUs. However architecture-dependent C
On Thu, Feb 04, 2016 at 12:47:35PM +0100, Igor Mammedov wrote:
> Signed-off-by: Igor Mammedov
Reviewed-by: Eduardo Habkost
--
Eduardo
On Thu, Feb 04, 2016 at 12:47:33PM +0100, Igor Mammedov wrote:
> cpu->found_cpus bitmap is used for setting present
> flag in CPON AML package at start up. But it takes
> a bunch of code to fill bitmap and cloud be simplified
> by calling qemu_get_cpu_by_arch_id(apic_id) directly.
>
> Hence do so
On Thu, Feb 04, 2016 at 12:47:32PM +0100, Igor Mammedov wrote:
> do not assume that all lapics in range 0..apic_id_limit
> are valid and do not create lapic entries for not
> possible lapics in MADT.
>
> Signed-off-by: Igor Mammedov
Reviewed-by: Eduardo Habkost
But there's one minor suggestion
On Thu, Feb 04, 2016 at 12:47:31PM +0100, Igor Mammedov wrote:
> do not assume that all lapics in range 0..apic_id_limit
> are valid and do not create Processor and Notify objects
> for not possible lapics.
>
> Signed-off-by: Igor Mammedov
Any specific reason you split the Processor/Notify chang
On 4 February 2016 at 21:50, Michael S. Tsirkin wrote:
> The following changes since commit 382d34ff9fcc534db32d54eb82590de7c04f9b33:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request'
> into staging (2016-02-03 19:00:33 +)
>
> are available in the git repository
On Thu, Feb 04, 2016 at 12:47:30PM +0100, Igor Mammedov wrote:
> When APIC IDs are sparse*, in addition to valid LAPIC
> antries the SRAT is also filled invalid ones for non
> posiible APIC IDs.
> Fix it by asking machine for all possible APIC IDs
> instead of wrongly assuming that all APIC IDs in
On 5 February 2016 at 13:56, Amit Shah wrote:
> The following changes since commit d38ea87ac54af64ef611de434d07c12dc0399216:
>
> all: Clean up includes (2016-02-04 17:41:30 +)
>
> are available in the git repository at:
>
> https://git.kernel.org/pub/scm/virt/qemu/amit/migration.git
> tag
On Thu, Feb 04, 2016 at 12:47:28PM +0100, Igor Mammedov wrote:
> on x86 currently range 0..max_cpus is used to generate
> architecture-dependent CPU ID (APIC Id) for each present
> and possible CPUs. However architecture-dependent CPU IDs
> list could be sparse and code that needs to enumerate
> al
On Fri, 5 Feb 2016 17:09:58 +0300
Vladimir Sementsov-Ogievskiy wrote:
> On 05.02.2016 15:58, Igor Mammedov wrote:
> > On Fri, 5 Feb 2016 11:19:01 +0300
> > Vladimir Sementsov-Ogievskiy wrote:
> >
> >> For now there are only two dimm's: pc-dimm and nvdimm. This patch is
> >> actually needed to
On Fri, 5 Feb 2016 17:12:55 +0300
Vladimir Sementsov-Ogievskiy wrote:
> On 05.02.2016 15:57, Igor Mammedov wrote:
> > On Fri, 5 Feb 2016 11:19:00 +0300
> > Vladimir Sementsov-Ogievskiy wrote:
> >
> >> Use pc_dimm_built_list() instead of qmp_pc_dimm_device_list()
> >>
> >> Actually, Qapi is no
On Fri, 5 Feb 2016 12:13:58 -0200
Eduardo Habkost wrote:
> On Thu, Feb 04, 2016 at 02:36:59PM +0100, Igor Mammedov wrote:
> > On Thu, 4 Feb 2016 14:18:10 +0200
> > Marcel Apfelbaum wrote:
> >
> > > On 02/04/2016 01:47 PM, Igor Mammedov wrote:
> > > > on x86 currently range 0..max_cpus is us
On 5 February 2016 at 09:15, Gilar Dwitresna wrote:
> Dear,
> My name is Gilar Dwitresna, from Telkom University, Indonesia.
> i'm interested with live migration on qemu kvm 1.4.0 release, but i have a
> problems in the installation of qemu kvm 1.4.0.
> can i get the tutorial of installing kvm qem
On Fri, Feb 05, 2016 at 12:14:16AM +0200, Michael S. Tsirkin wrote:
> On Thu, Feb 04, 2016 at 05:09:44PM -0200, Eduardo Habkost wrote:
> > On Thu, Feb 04, 2016 at 08:02:30PM +0200, Michael S. Tsirkin wrote:
> > > On Thu, Feb 04, 2016 at 03:16:17PM -0200, Eduardo Habkost wrote:
> > > > On Thu, Feb 0
In syndrome register values, the IL bit indicates the instruction
length, and is 1 for 4-byte instructions and 0 for 2-byte
instructions. All A64 and A32 instructions are 4-byte, but
Thumb instructions may be either 2 or 4 bytes long. Unfortunately
we named the parameter to the syn_* functions for
All Thumb coprocessor instructions are 32 bits, so the IL
bit in the syndrome register should be set. Pass false to the
syn_* function's is_16bit argument rather than s->thumb
so we report the correct IL bit.
Signed-off-by: Peter Maydell
---
target-arm/translate.c | 8
1 file changed, 4
This series corrects a bug I noticed while reading the code.
In syndrome register values, the IL bit indicates the instruction
length, and is 1 for 4-byte instructions and 0 for 2-byte
instructions. All A64 and A32 instructions are 4-byte, but Thumb
instructions may be either 2 or 4 bytes long.
All Thumb Neon and VFP instructions are 32 bits, so the IL
bit in the syndrome register should be set. Pass false to the
syn_* function's is_16bit argument rather than s->thumb
so we report the correct IL bit.
Signed-off-by: Peter Maydell
---
target-arm/translate.c | 6 +++---
1 file changed, 3
Dear,
My name is Gilar Dwitresna, from Telkom University, Indonesia.
i'm interested with live migration on qemu kvm 1.4.0 release, but i have a
problems in the installation of qemu kvm 1.4.0.
can i get the tutorial of installing kvm qemu 1.4.0? and what version of
ubuntu that i can install qemu kvm
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