On Fri, 5 Feb 2016 17:12:55 +0300
Vladimir Sementsov-Ogievskiy wrote:
> On 05.02.2016 15:57, Igor Mammedov wrote:
> > On Fri, 5 Feb 2016 11:19:00 +0300
> > Vladimir Sementsov-Ogievskiy wrote:
> >
> >> Use pc_dimm_built_list() instead of
On Thu, Feb 04, 2016 at 12:47:33PM +0100, Igor Mammedov wrote:
> cpu->found_cpus bitmap is used for setting present
> flag in CPON AML package at start up. But it takes
> a bunch of code to fill bitmap and cloud be simplified
> by calling qemu_get_cpu_by_arch_id(apic_id) directly.
>
> Hence do so
Peter Maydell writes:
> On 5 February 2016 at 16:17, Alex Bennée wrote:
>>
>> Peter Maydell writes:
>>> I haven't measured, no, but since there are only 3 arguments the
>>> third argument is going to be in a register
We weren't quite implementing the handling of SCR.SMD correctly.
The condition governing whether the SMD bit should apply only
for NS state is "is EL3 is AArch32", not "is the current EL AArch32".
Fix the condition, and clarify the comment both to reflect this and
to expand slightly on what's
Am 05.02.2016 um 14:28 hat Alberto Garcia geschrieben:
> On Fri 05 Feb 2016 03:25:22 AM CET, Changlong Xie
> wrote:
> > Signed-off-by: Wen Congyang
> > Signed-off-by: Changlong Xie
>
> Reviewed-by: Alberto Garcia
On 5 February 2016 at 14:09, Alex Bennée wrote:
>
> Peter Maydell writes:
>> @@ -1767,6 +1765,14 @@ static inline int arm_debug_target_el(CPUARMState
>> *env)
>>
>> static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
>> {
>> +
Peter Maydell writes:
> Implement some corner cases of the behaviour of the NSACR
> register on ARMv8:
> * if EL3 is AArch64 then accessing the NSACR from Secure EL1
>with AArch32 should trap to EL3
> * if EL3 is not present or is AArch64 then reads from NS EL1
Peter Maydell writes:
> On 5 February 2016 at 16:27, Alex Bennée wrote:
>>
>> Alex Bennée writes:
>>
>>> The following changes since commit 357e81c7e880f868833edf9f53cce1f3b09ea8ec:
>>>
>>> Merge remote-tracking
Implement the debug register traps controlled by MDCR_EL2.TDA
and MDCR_EL3.TDA.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 39 ++-
1 file changed, 30 insertions(+), 9 deletions(-)
diff --git a/target-arm/helper.c
On Fri, 5 Feb 2016 12:33:44 +0100
Cornelia Huck wrote:
> On Fri, 05 Feb 2016 11:43:11 +0100
> Greg Kurz wrote:
>
> > +static bool virtio_net_set_vnet_endian(VirtIODevice *vdev, NetClientState
> > *ncs,
> > +
Am 04.02.2016 um 17:35 hat Daniel P. Berrange geschrieben:
> On Thu, Feb 04, 2016 at 05:06:06PM +0100, Kevin Wolf wrote:
> > Am 04.02.2016 um 16:47 hat Daniel P. Berrange geschrieben:
> > > On Thu, Feb 04, 2016 at 04:42:06PM +0100, Kevin Wolf wrote:
> > > > Am 02.02.2016 um 13:57 hat Daniel P.
On Fri, 5 Feb 2016 13:28:31 -0200
Eduardo Habkost wrote:
> On Thu, Feb 04, 2016 at 12:47:32PM +0100, Igor Mammedov wrote:
> > do not assume that all lapics in range 0..apic_id_limit
> > are valid and do not create lapic entries for not
> > possible lapics in MADT.
> >
> >
On Fri, 5 Feb 2016 13:50:05 -0200
Eduardo Habkost wrote:
> On Fri, Feb 05, 2016 at 04:39:46PM +0100, Igor Mammedov wrote:
> > On Fri, 5 Feb 2016 13:04:26 -0200
> > Eduardo Habkost wrote:
> >
> > > On Thu, Feb 04, 2016 at 12:47:28PM +0100, Igor
On 5 February 2016 at 16:07, Alex Bennée wrote:
>
> Peter Maydell writes:
>
>> Implement some corner cases of the behaviour of the NSACR
>> register on ARMv8:
>> * if EL3 is AArch64 then accessing the NSACR from Secure EL1
>>with AArch32
On 5 February 2016 at 16:09, Aurelio Remonda
wrote:
> Hello, im working on this feature right now.
> i have a working patch but maybe I can make some changes to make it look
> better:
> for example in some point i check ram_size like this:
> if (ram_size
On 5 February 2016 at 16:27, Alex Bennée wrote:
>
> Alex Bennée writes:
>
>> The following changes since commit 357e81c7e880f868833edf9f53cce1f3b09ea8ec:
>>
>> Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20160128' into
>> staging
Alex Bennée writes:
> The following changes since commit 357e81c7e880f868833edf9f53cce1f3b09ea8ec:
>
> Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20160128' into
> staging (2016-01-28 11:46:34 +)
>
> are available in the git repository at:
>
>
Implement trapping of the "debug ROM" registers, which are controlled
by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 27 ---
1 file changed, 24 insertions(+), 3
On Fri, 5 Feb 2016 12:13:58 -0200
Eduardo Habkost wrote:
> On Thu, Feb 04, 2016 at 02:36:59PM +0100, Igor Mammedov wrote:
> > On Thu, 4 Feb 2016 14:18:10 +0200
> > Marcel Apfelbaum wrote:
> >
> > > On 02/04/2016 01:47 PM, Igor Mammedov wrote:
On Thu, Feb 04, 2016 at 12:47:31PM +0100, Igor Mammedov wrote:
> do not assume that all lapics in range 0..apic_id_limit
> are valid and do not create Processor and Notify objects
> for not possible lapics.
>
> Signed-off-by: Igor Mammedov
Any specific reason you split the
On Fri, 5 Feb 2016 13:04:26 -0200
Eduardo Habkost wrote:
> On Thu, Feb 04, 2016 at 12:47:28PM +0100, Igor Mammedov wrote:
> > on x86 currently range 0..max_cpus is used to generate
> > architecture-dependent CPU ID (APIC Id) for each present
> > and possible CPUs. However
On Fri, Feb 05, 2016 at 04:39:46PM +0100, Igor Mammedov wrote:
> On Fri, 5 Feb 2016 13:04:26 -0200
> Eduardo Habkost wrote:
>
> > On Thu, Feb 04, 2016 at 12:47:28PM +0100, Igor Mammedov wrote:
> > > on x86 currently range 0..max_cpus is used to generate
> > >
Peter Maydell writes:
> On 5 February 2016 at 14:20, Alex Bennée wrote:
>>
>> Peter Maydell writes:
>>> -typedef CPAccessResult CPAccessFn(CPUARMState *env, const ARMCPRegInfo
>>> *opaque);
>>> +typedef
On Thu, Feb 04, 2016 at 12:47:30PM +0100, Igor Mammedov wrote:
> When APIC IDs are sparse*, in addition to valid LAPIC
> antries the SRAT is also filled invalid ones for non
> posiible APIC IDs.
> Fix it by asking machine for all possible APIC IDs
> instead of wrongly assuming that all APIC IDs in
On Fri, 5 Feb 2016 13:17:14 -0200
Eduardo Habkost wrote:
> On Thu, Feb 04, 2016 at 12:47:31PM +0100, Igor Mammedov wrote:
> > do not assume that all lapics in range 0..apic_id_limit
> > are valid and do not create Processor and Notify objects
> > for not possible lapics.
> >
On 4 February 2016 at 21:50, Michael S. Tsirkin wrote:
> The following changes since commit 382d34ff9fcc534db32d54eb82590de7c04f9b33:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request'
> into staging (2016-02-03 19:00:33 +)
>
> are available in
On Thu, Feb 04, 2016 at 12:47:32PM +0100, Igor Mammedov wrote:
> do not assume that all lapics in range 0..apic_id_limit
> are valid and do not create lapic entries for not
> possible lapics in MADT.
>
> Signed-off-by: Igor Mammedov
Reviewed-by: Eduardo Habkost
On 02/04/2016 07:25 PM, Changlong Xie wrote:
> Signed-off-by: Wen Congyang
> Signed-off-by: Changlong Xie
> ---
> block/quorum.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/block/quorum.c b/block/quorum.c
> index
Hello, im working on this feature right now.
i have a working patch but maybe I can make some changes to make it look better:
for example in some point i check ram_size like this:
if (ram_size == 0x800)
Maybe if i make ram_addr_t default_ram_size global (is a local
variable of
On Fri, 5 Feb 2016 13:39:07 -0200
Eduardo Habkost wrote:
> On Thu, Feb 04, 2016 at 12:47:33PM +0100, Igor Mammedov wrote:
> > cpu->found_cpus bitmap is used for setting present
> > flag in CPON AML package at start up. But it takes
> > a bunch of code to fill bitmap and
On 05.02.2016 17:55, Igor Mammedov wrote:
On Fri, 5 Feb 2016 17:09:58 +0300
Vladimir Sementsov-Ogievskiy wrote:
On 05.02.2016 15:58, Igor Mammedov wrote:
On Fri, 5 Feb 2016 11:19:01 +0300
Vladimir Sementsov-Ogievskiy wrote:
For now
Correct some corner cases we were getting wrong for
CNTFRQ access rights:
* should UNDEF from 32-bit Secure EL1
* only writable from the highest implemented exception level,
which might not be EL1 now
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 31
On Thu, Feb 04, 2016 at 12:47:28PM +0100, Igor Mammedov wrote:
> on x86 currently range 0..max_cpus is used to generate
> architecture-dependent CPU ID (APIC Id) for each present
> and possible CPUs. However architecture-dependent CPU IDs
> list could be sparse and code that needs to enumerate
>
On 5 February 2016 at 16:26, Alex Bennée wrote:
>
> Fam Zheng writes:
>> Can be a separate patch, though.
>
> As I've already submitted the pull I'll clean it up on the next round.
You told me this morning you were going to resubmit the pull
anyway, so
Fam Zheng writes:
> On Thu, 02/04 17:12, Alex Bennée wrote:
>> Signed-off-by: Alex Bennée
>> Reviewed-by: David Gibson
>>
>> ---
>> pr: added r-b tags
>> ---
>> MAINTAINERS | 5 +
>> 1 file changed, 5 insertions(+)
>>
If access to FPEXC32_EL2 is trapped by CPTR_EL2.TFP or CPTR_EL3.TFP,
this should be reported with a syndrome register indicating an
FP access trap, not one indicating a system register access trap.
Signed-off-by: Peter Maydell
---
target-arm/cpu.h | 5 +
On 5 February 2016 at 16:55, Aurelio Remonda
wrote:
> Im making something like this:
>
> if (ram_size == 0x800) /* default value, means whitout -m flag */
>{
> sram_size = ((board->dc0 >> 18) + * 1024;
> }
> else if (ram_size >=
El 5 feb. 2016 1:24 PM, "Peter Maydell" escribió:
> On 5 February 2016 at 16:09, Aurelio Remonda
> wrote:
> > Hello, im working on this feature right now.
> > i have a working patch but maybe I can make some changes to make it
This patchset fixes or implements a lot of traps to EL3 as
listed in the ARM ARM section D1.15.4 "EL3 configurable controls".
Most of the rest we already had implemented.
NB: where the trap I was implementing for EL3 had an
obvious equivalent in EL2 I included the EL2 check in this
series, but I
do not assume that all lapics in range 0..apic_id_limit
are valid and do not create lapic entries for not
possible lapics in MADT.
Signed-off-by: Igor Mammedov
---
hw/i386/acpi-build.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git
do not assume that all lapics in range 0..apic_id_limit
are valid and do not create Processor and Notify objects
for not possible lapics.
Signed-off-by: Igor Mammedov
Reviewed-by: Eduardo Habkost
---
hw/i386/acpi-build.c | 41
On Fri, 5 Feb 2016 17:19:50 +0100
Igor Mammedov wrote:
> On Fri, 5 Feb 2016 13:39:07 -0200
> Eduardo Habkost wrote:
>
> > On Thu, Feb 04, 2016 at 12:47:33PM +0100, Igor Mammedov wrote:
> > > cpu->found_cpus bitmap is used for setting present
> > >
cpu_exists() already does CPU lookup but
discards found CPU and returns boolean instead.
Make it more useful by returning a found CPU
and also rename it more descriptive name.
Signed-off-by: Igor Mammedov
Reviewed-by: Eduardo Habkost
---
hw/i386/pc.c
Signed-off-by: Igor Mammedov
Reviewed-by: Eduardo Habkost
---
hw/i386/acpi-build.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 6ac05b3..5fc8019 100644
--- a/hw/i386/acpi-build.c
+++
Changes since v1:
- rebased on top of PCI tree that contains
Eduardo's guest_info removel series
- fix ^2 times present CPU lookup when creating CPON
package (spotted-by: Eduardo Habkost )
It's mostly clean up series that removes invalid CPU
entries from
on x86 currently range 0..max_cpus is used to generate
architecture-dependent CPU ID (APIC Id) for each present
and possible CPUs. However architecture-dependent CPU IDs
list could be sparse and code that needs to enumerate
all IDs (ACPI) ended up doing guess work enumerating all
possible and
Commit 16b0d555 introduced an issue where we are not initializing
has_filename for the 'next' MapEntry object, which leads to interesting
errors in Valgrind and Clang -fsanitize=undefined both.
Zero the stack object at allocation AND make sure the utility to
populate the fields properly marks
Signed-off-by: Igor Mammedov
---
hw/i386/pc.c | 45 +++--
1 file changed, 19 insertions(+), 26 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 548ec64..b863265 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -700,18 +700,6
On 01/20/2016 10:38 AM, Daniel P. Berrange wrote:
> Provide a block encryption implementation that follows the
> LUKS/dm-crypt specification.
>
> This supports all combinations of hash, cipher algorithm,
> cipher mode and iv generator that are implemented by the
> current crypto layer.
>
> The
Signed-off-by: Igor Mammedov
---
hw/i386/acpi-build.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 5fc8019..7ac46f4 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -2426,7 +2426,6 @@ build_srat(GArray
Implement the traps to EL2 and EL3 controlled by the bits
MDCR_EL2.TDOSA MDCR_EL3.TDOSA. These can configurably trap
accesses to the "powerdown debug" registers.
Signed-off-by: Peter Maydell
---
target-arm/cpu.h| 12
target-arm/helper.c | 23
t; since I don't know anything about the travis syntax or how to test it,
> could you rebase and fix up the conflict, please?
I've pushed a signed tags/pull-build-test-20160205 but I'm still waiting
for the job to finish and I'm about to sign off. If your around for a
bit longer you can w
call qdev_get_machine() once at acpi_build() and
pass its result to child functions that need it.
Signed-off-by: Igor Mammedov
Reviewed-by: Marcel Apfelbaum
---
hw/i386/acpi-build.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
cpu->found_cpus bitmap is used for setting present
flag in CPON AML package. But it takes a bunch of code
to fill bitmap and could be simplified by getting
presense info from possible CPUs list directly.
So move found_cpus bitmap to the only place that uses
it for building sparse CPON AML
* Daniel P. Berrange (berra...@redhat.com) wrote:
> Now that the memory buffer based QEMUFile impl is gone, there
> is no need for any backend to be accessing internals of the
> QEMUFile struct, so it can be moved back into qemu-file.c
>
> Signed-off-by: Daniel P. Berrange
Lluís Vilanova writes:
> Markus Armbruster writes:
>
>> Lluís Vilanova writes:
>>> Markus Armbruster writes:
>>>
This overlaps with parts of Lluís's "[RFC][PATCH v6 0/5] utils:
Improve and document error reporting". Lluís, feel free to
On 2016/2/5 15:40, Jason Wang wrote:
On 02/05/2016 03:01 PM, Hailiang Zhang wrote:
On 2016/2/5 14:19, Jason Wang wrote:
On 02/01/2016 06:40 PM, Hailiang Zhang wrote:
On 2016/2/1 17:42, Jason Wang wrote:
On 02/01/2016 05:22 PM, Hailiang Zhang wrote:
On 2016/2/1 17:04, Jason Wang wrote:
On 02/04/2016 01:23 PM, marcin.krzemin...@nokia.com wrote:
> From: Marcin Krzeminski
>
> This patch handles dummy cycles.
>
> Signed-off-by: Marcin Krzeminski
> ---
> hw/block/m25p80.c | 6 ++
> 1 file changed, 6 insertions(+)
>
>
v6:
add stubbed pc_dimm_build_list, fix compilation for
!CONFIG_MEM_HOTPLUG targets - thx to Cornelia.
v5: do not use qapi
0002-0004: new patches
0005: white list instead of black list
v4:
0001: Reviewed-by: Eric Blake
second patch is splitted to 0002 and 0003
0002:
For now there are only two dimm's: pc-dimm and nvdimm. This patch is
actually needed to disable ballooning on nvdimm. But, to avoid future
bugs, instead of disallowing nvdimm, we allow only pc-dimm. So, if
someone adds new dimm which should be balloon-able, then this ability
should be explicitly
Sorry for subject, it should be
[PATCH v6 0/5] don't use NVDIMM for balooning
On 05.02.2016 11:18, Vladimir Sementsov-Ogievskiy wrote:
v6:
add stubbed pc_dimm_build_list, fix compilation for
!CONFIG_MEM_HOTPLUG targets - thx to Cornelia.
v5: do not use qapi
0002-0004: new patches
0005:
state->name does not contain a terminating '\0' and you may get:
Machine type received is 'pseries-2.3y�?' and local is 'pseries-2.4'
load of migration failed: Invalid argument
Let's add a precision modifier to fix this.
Reviewed-by: Amit Shah
Signed-off-by: Greg Kurz
get_current_ram_size() is used only in virtio-balloon.c
This patch moves it into virtio-balloon and make it static, to allow
some balloon-specific tuning.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Denis V. Lunev
Reviewed-by: Eric Blake
Like pc_dimm_build_list_sorted but not sorted - for cases where sorting
is not necessary. Add stubbed version too - for targets without
CONFIG_MEM_HOTPLUG.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
hw/mem/pc-dimm.c| 15 +++
Use pc_dimm_built_list() instead of qmp_pc_dimm_device_list()
Actually, Qapi is not related to this internal helper.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
hw/virtio/virtio-balloon.c | 23 ++-
1 file changed, 6 insertions(+), 17
s/pc_dimm_built_list/pc_dimm_build_list_sorted
- need for add pc_dimm_build_list (not sorted) in the next patch
- fix typo (built -> build)
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
hw/mem/pc-dimm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
>>> It is already migrated as part of virtio_rng_save's call to virtio_save.
>>> On the loading side, virtio_rng_process condenses all requests into one
>>> and chr_read fills in as many virtqueue buffers as possible from the
>>> single request.
>>
>> Thanks! So this looks broken. The contract
On Fri, 5 Feb 2016 17:09:58 +0300
Vladimir Sementsov-Ogievskiy wrote:
> On 05.02.2016 15:58, Igor Mammedov wrote:
> > On Fri, 5 Feb 2016 11:19:01 +0300
> > Vladimir Sementsov-Ogievskiy wrote:
> >
> >> For now there are only two dimm's:
On 5 February 2016 at 13:56, Amit Shah wrote:
> The following changes since commit d38ea87ac54af64ef611de434d07c12dc0399216:
>
> all: Clean up includes (2016-02-04 17:41:30 +)
>
> are available in the git repository at:
>
>
On Thu, Feb 04, 2016 at 12:47:35PM +0100, Igor Mammedov wrote:
> Signed-off-by: Igor Mammedov
Reviewed-by: Eduardo Habkost
--
Eduardo
Peter Maydell writes:
> Enable EL3 support for our Cortex-A53 and Cortex-A57 CPU models.
> We have enough implemented now to be able to run real world code
> at least to some extent (I can boot ARM Trusted Firmware to the
> point where it pulls in OP-TEE and then falls
On 5 February 2016 at 16:17, Alex Bennée wrote:
>
> Peter Maydell writes:
>> I haven't measured, no, but since there are only 3 arguments the
>> third argument is going to be in a register on any host architecture
>> we care about, which means
On Fri, 5 Feb 2016 15:03:55 +
Peter Maydell wrote:
> On 4 February 2016 at 21:50, Michael S. Tsirkin wrote:
> > The following changes since commit 382d34ff9fcc534db32d54eb82590de7c04f9b33:
> >
> > Merge remote-tracking branch
On 01/20/2016 10:38 AM, Daniel P. Berrange wrote:
> The qemu-img/qemu-io tools prompt for disk encryption passwords
> regardless of whether any are actually required. Adding a check
> on bdrv_key_required() avoids this prompt for disk formats which
> have been converted to the QCryptoSecret APIs.
On 01/20/2016 10:38 AM, Daniel P. Berrange wrote:
> Add a block driver that is capable of supporting any full disk
> encryption format. This utilizes the previously added block
> encryption code, and at this time supports the LUKS format.
>
> The driver code is capable of supporting any format
On 01/20/2016 10:38 AM, Daniel P. Berrange wrote:
> Instead of requiring separate input/output buffers for
> encrypting data, change qcow2_encrypt_sectors() to assume
> use of a single buffer, encrypting in place. The current
> callers all used the same buffer for input/output already.
>
>
On 02/05/2016 05:43 AM, Daniel P. Berrange wrote:
> On Thu, Feb 04, 2016 at 05:23:32PM -0700, Eric Blake wrote:
>> On 01/20/2016 10:38 AM, Daniel P. Berrange wrote:
>>> Add a generic framework for support different block encryption
>>> formats. Upon instantiating a QCryptoBlock object, it will
getrandom() has been introduced in kernel 3.17 and is now used during
the boot sequence of Debian unstable (stretch/sid).
Signed-off-by: Laurent Vivier
---
linux-user/syscall.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/linux-user/syscall.c
till had ---
>>> history on them but the tag is clean and can be pulled.
>>
>> Merge conflict in .travis.yml -- probably easy enough to fix up but
>> since I don't know anything about the travis syntax or how to test it,
>> could you rebase and fix up the conflict, p
When APIC IDs are sparse*, in addition to valid LAPIC
antries the SRAT is also filled invalid ones for non
posiible APIC IDs.
Fix it by asking machine for all possible APIC IDs
instead of wrongly assuming that all APIC IDs in
range 0..apic_id_limit are possible.
* sparse lapic topology CLI:
On 01/22/2016 12:07 PM, Vladimir Sementsov-Ogievskiy wrote:
> Hi all.
>
> This is the early begin of the series which aims to add external backup
> api. This is needed to allow backup software use our dirty bitmaps.
>
> Vmware and Parallels Cloud Server have this feature.
>
Have a link to
On Thu, 4 Feb 2016 23:54:13 +0200
"Michael S. Tsirkin" wrote:
> From: Roman Kagan
>
> On x86-based systems Linux determines the presence
> and the type of floppy drives via a query of a CMOS field.
> So does SeaBIOS when populating the return data for
>
On 02/05/2016 11:12 AM, John Snow wrote:
> Commit 16b0d555 introduced an issue where we are not initializing
> has_filename for the 'next' MapEntry object, which leads to interesting
> errors in Valgrind and Clang -fsanitize=undefined both.
grammar:
errors in both Valgrind and Clang
On 01/20/2016 10:38 AM, Daniel P. Berrange wrote:
> When opening an image it is useful to know whether the caller
> intends to perform I/O on the image or not. In the case of
> encrypted images this will allow the block driver to avoid
> having to prompt for decryption keys when we merely want to
The new feature for qcow2: storing bitmaps.
This patch adds new header extension to qcow2 - Bitmaps Extension. It
provides an ability to store virtual disk related bitmaps in a qcow2
image. For now there is only one type of such bitmaps: Dirty Tracking
Bitmap, which just tracks virtual disk
On 02/02/2016 10:29 PM, P J P wrote:
> From: Prasad J Pandit
>
> Ne2000 NIC uses ring buffer of NE2000_MEM_SIZE(49152)
> bytes to process network packets. Four registers PSTART,
> PSTOP, CURPAGE and BOUNDARY are used to control ring buffer
> access. Setting these
On Do, 2016-02-04 at 16:03 -0300, Daniel Serpell wrote:
> This key is present in international keyboards, between left shift and
> the 'Z' key, ant is described in the HID usage tables as "Keyboard
> Non-US \ and |": http://www.usb.org/developers/hidpage/Hut1_12v2.pdf
>
> This patch fixes the
The configure options are suggested by John Snow .
Signed-off-by: Fam Zheng
---
tests/docker/test-clang.sh | 26 ++
1 file changed, 26 insertions(+)
create mode 100755 tests/docker/test-clang.sh
diff --git a/tests/docker/test-clang.sh
Signed-off-by: Fam Zheng
---
tests/docker/test-mingw.sh | 34 ++
1 file changed, 34 insertions(+)
create mode 100755 tests/docker/test-mingw.sh
diff --git a/tests/docker/test-mingw.sh b/tests/docker/test-mingw.sh
new file mode 100755
index
Peter Maydell writes:
> Fix a typo where "EL2" was written but "EL3" intended.
>
> Signed-off-by: Peter Maydell
> ---
> target-arm/cpu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-arm/cpu.h
Hello,
> -Original Message-
> From: EXT Cédric Le Goater [mailto:c...@fr.ibm.com]
> Sent: Friday, February 05, 2016 8:53 AM
> To: Krzeminski, Marcin (Nokia - PL/Wroclaw); qemu-devel@nongnu.org
> Cc: crosthwaitepe...@gmail.com; pawel.len...@itlen.com
> Subject: Re: [PATCH v2 05/11] block:
On Thu, Feb 04, 2016 at 03:57:33PM -0700, Eric Blake wrote:
> On 01/20/2016 10:38 AM, Daniel P. Berrange wrote:
> > There are a number of different algorithms that can be used
> > to generate initialization vectors for disk encryption. This
> > introduces a simple internal QCryptoBlockIV object to
Current implementation for netmap backend does not really probe the netmap
kernel module to know whether virtio-net header is supported for a specific
netmap port. This is only correct for VALE ports, but it is not correct for
hardware ports, pipes, etc.
This patch properly implements the missing
Previous implementation of has_ufo, has_vnet_hdr, has_vnet_hdr_len, etc.
did not really probe for virtio-net header support for the netmap
interface attached to the backend. These callbacks were correct for
VALE ports, but incorrect for hardware NICs, pipes, monitors, etc.
This patch fixes the
This series brings some improvements to the cross-endian support in the
virtio and vhost code:
- use qemu_set_vnet_be() and qemu_set_vnet_le() directly from virtio-net,
so that backend cross-endian capabilities benefit to both emulated and
vhost accelerated devices
- optimize
When running a fully emulated device in cross-endian conditions, including
a virtio 1.0 device offered to a big endian guest, we need to fix the vnet
headers. This is currently handled by the virtio_net_hdr_swap() function
in the core virtio-net code but it should actually be handled by the net
When testing the ranges of valid values, set_cfg_value() creates
sometimes invalid throttling configurations by setting bucket.max
while leaving bucket.avg uninitialized.
While this doesn't break the current tests, it will as soon as
we unify all functions that check the validity of the
The caller does not need to set it, and this will allow us to refactor
this function later.
Signed-off-by: Alberto Garcia
---
blockdev.c | 4 +---
include/qemu/throttle.h | 2 +-
tests/test-throttle.c | 2 +-
util/throttle.c | 5 -
4 files changed, 7
The caller does not need to set it, and this will allow us to refactor
this function later.
Signed-off-by: Alberto Garcia
---
blockdev.c | 4 +---
include/qemu/throttle.h | 2 +-
tests/test-throttle.c | 12 ++--
util/throttle.c | 11 +--
The caller does not need to set it, and this will allow us to refactor
this function later.
Signed-off-by: Alberto Garcia
---
blockdev.c | 4 +---
include/qemu/throttle.h | 2 +-
tests/test-throttle.c | 6 +++---
util/throttle.c | 5 -
4 files
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