[Qemu-devel] [Bug 1563887] Re: qemu-system-ppc64 freezes on starting image on ppc64le

Hm - I can boot a wily cloud image, just not a xenial one. ** Also affects: linux (Ubuntu) Importance: Undecided Status: New ** Changed in: qemu (Ubuntu) Status: Incomplete => Confirmed -- You received this bug notification because you are a member of qemu- devel-ml, which is

[Qemu-devel] [Bug 1563887] Re: qemu-system-ppc64 freezes on starting image on ppc64le

** Changed in: qemu (Ubuntu) Status: New => Incomplete -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1563887 Title: qemu-system-ppc64 freezes on starting image on ppc64le Status in QEMU:

[Qemu-devel] [Bug 1565395] [NEW] qemu-2.4.1 fails when compiled against pulseaudio

Public bug reported: If I compile qemu-2.4.1 like this: CC="gcc -mtune=generic -Os -pipe" CXX="g++ -mtune=generic -Os -pipe -fno-exceptions -fno-rtti" ./configure --prefix=/usr/local --localstatedir=/var --libexecdir=/usr/local/lib/qemu --interp-prefix=/usr/local/share/qemu

[Qemu-devel] segmentation fault in object.c:type_initialize_interface() if interface not defined

I just updated GNU ARM Eclipse QEMU to 2.5.1 and initially I had some problems, main() failed quite early, in the first call to `find_default_machine()`. After several debug sessions, I identified the problem to be a null pointer when a referred interface is not defined. In my Cortex-M specific

Re: [Qemu-devel] [PATCH] tcg/mips: Fix type of tcg_target_reg_alloc_order[]

On Apr 1, 2016 14:38, Aurelien Jarno wrote: > Richard, do you have a pending TCG pull request in which you can include > this one? Nothing pending at the moment, no.  I was going to do one special for this, but it looks as if I won't get to it before Sunday at minimum.  If

Re: [Qemu-devel] [PATCH] acpi: Fix TPM ACPI description to make TPM usable on Windows

On Fri, 1 Apr 2016 14:50:43 -0400 Stefan Berger wrote: > On 03/31/2016 10:07 AM, Igor Mammedov wrote: > > On Thu, 31 Mar 2016 00:03:57 -0400 > > Stefan Berger wrote: > > > >> On 03/30/2016 09:33 AM, Igor Mammedov wrote: > >>> On Mon, 21

Re: [Qemu-devel] [PATCH] ui/cocoa.m: fix sending mouse event to guest

On Apr 2, 2016, at 1:35 PM, Peter Maydell wrote: > On 2 April 2016 at 18:25, Programmingkid wrote: >> >> On Apr 2, 2016, at 1:07 PM, Peter Maydell wrote: >> >>> On 2 April 2016 at 17:56, Programmingkid wrote: The mouse down event

Re: [Qemu-devel] [PATCH] ui/cocoa.m: fix sending mouse event to guest

On 2 April 2016 at 18:25, Programmingkid wrote: > > On Apr 2, 2016, at 1:07 PM, Peter Maydell wrote: > >> On 2 April 2016 at 17:56, Programmingkid wrote: >>> The mouse down event should not be sent to the guest if the mouse down event >>>

Re: [Qemu-devel] [PATCH] ui/cocoa.m: fix sending mouse event to guest

On Apr 2, 2016, at 1:07 PM, Peter Maydell wrote: > On 2 April 2016 at 17:56, Programmingkid wrote: >> The mouse down event should not be sent to the guest if the mouse down event >> causes an activation of QEMU. This patch prevents activation clicks from >> going >>

Re: [Qemu-devel] [PATCH] ui/cocoa.m: fix sending mouse event to guest

On 2 April 2016 at 17:56, Programmingkid wrote: > The mouse down event should not be sent to the guest if the mouse down event > causes an activation of QEMU. This patch prevents activation clicks from going > to the guest. > > Signed-off-by: John Arbuckle

[Qemu-devel] [PATCH] ui/cocoa.m: fix sending mouse event to guest

The mouse down event should not be sent to the guest if the mouse down event causes an activation of QEMU. This patch prevents activation clicks from going to the guest. Signed-off-by: John Arbuckle --- ui/cocoa.m | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[Qemu-devel] [PATCH v7 5/6] i.MX: Add i.MX6 SOC implementation.

For now we only support the following devices: * up to 4 Cortex A9 cores * A9 MPCORE (SCU, GIC, TWD) * 5 i.MX UARTs * 2 EPIT timers * 1 GPT timer * 3 I2C controllers * 7 GPIO controllers * 6 SDHC controllers * 5 SPI controllers * 1 CCM device * 1 SRC device * various ROM/RAM areas. Reviewed-by:

Re: [Qemu-devel] [Bug 1563887] Re: qemu-system-ppc64 freezes on starting image on ppc64le

Quoting Serge Hallyn (2016-04-01 11:56:29) > Hi, > > I've redeployed my test box with 14.04 with kilo-staging archive, but i > get a core dump when i try to run kvm the same way you did. What does `ppc64_cpu --info` report? The original bug had some output that suggested SMT was enabled: >

[Qemu-devel] [PATCH v7 6/6] i.MX: Add sabrelite i.MX6 emulation.

The sabrelite supports one SPI FLASH memory on SPI1 Signed-off-by: Jean-Christophe Dubois --- Changes since V1: * Output a message and exit if RAM size is unsupported. Changes since V2: * Added include "qemu/osdep.h" * Added access to controllers through properties.

[Qemu-devel] [PATCH v7 3/6] FIFO: Add a FIFO32 implementation

This one is build on top of the existing FIFO8 Reviewed-by: Peter Maydell Signed-off-by: Jean-Christophe Dubois --- Changes since V1: * None Changes since V2: * Added copyright * define Fifo32 as a struct containing Fifo8 * remove

[Qemu-devel] [PATCH v7 1/6] ARM: Factor out ARM on/off PSCI control functions

Split ARM on/off function from PSCI support code. This will allow to reuse these functions in other code. Signed-off-by: Jean-Christophe Dubois --- Changes since V1: * Not present on V1 Changes since V2: * Not present on V2 Changes since V3: * Move to a more

[Qemu-devel] [PATCH v7 2/6] i.MX: Add i.MX6 System Reset Controller device.

This controller is also present in i.MX5X devices but they are not yet emulated by QEMU. Reviewed-by: Peter Maydell Signed-off-by: Jean-Christophe Dubois --- Changes since V1: * Change "reset" sematic to mean full power cyvle. Changes since V2:

[Qemu-devel] [PATCH v7 0/6] Add i.MX6 (Single/Dual/Quad) support

This patch series adds support for the Freescale i.MX6 processor. For now we only support the following devices: * up to 4 Cortex A9 cores * A9 MPCORE (SCU, GIC, TWD) * 5 i.MX UARTs * 2 EPIT timers * 1 GPT timer * 7 GPIO controllers * 6 SDHC controllers * 5 SPI controllers * 1 CCM device * 1 SRC

[Qemu-devel] [PATCH v7 4/6] i.MX: Add the Freescale SPI Controller

Signed-off-by: Jean-Christophe Dubois --- Changes since V1: * Access SPI slave only at a byte level. * rework the CS activation to avoid to reset access to SPI slaves. Changes since V2: * Added #include "qemu/osdep.h" * remove previous_level from state struct * save

Re: [Qemu-devel] [PATCH v6 0/6] Add i.MX6 (Single/Dual/Quad) support

This will not compile on "target-arm.next" as I need to rework a bit the header file included. I am fixing it and will send a v7. Sorry for the noise. JC Le 02/04/2016 14:46, Jean-Christophe Dubois a écrit : This patch series adds support for the Freescale i.MX6 processor. For now we only

Re: [Qemu-devel] [Nbd] [PATCHv2] Improve documentation of FUA and FLUSH

Wouter, On 2 Apr 2016, at 13:57, Wouter Verhelst wrote: > On Fri, Apr 01, 2016 at 10:54:42AM +0100, Alex Bligh wrote: >> Improve the documentation of NBD_CMD_FLUSH and NBD_CMD_FLAG_FUA. Specifically >> the latter may be set on any command, and its semantics on commands other >>

[Qemu-devel] [PATCH v6 6/6] i.MX: Add sabrelite i.MX6 emulation.

The sabrelite supports one SPI FLASH memory on SPI1 Signed-off-by: Jean-Christophe Dubois --- Changes since V1: * Output a message and exit if RAM size is unsupported. Changes since V2: * Added include "qemu/osdep.h" * Added access to controllers through properties.

Re: [Qemu-devel] [Nbd] [PATCHv2] Improve documentation of FUA and FLUSH

On Fri, Apr 01, 2016 at 10:54:42AM +0100, Alex Bligh wrote: > Improve the documentation of NBD_CMD_FLUSH and NBD_CMD_FLAG_FUA. Specifically > the latter may be set on any command, and its semantics on commands other > than NBD_CMD_WRITE need explaining. Further, explain how these relate to >

[Qemu-devel] [PATCH v6 5/6] i.MX: Add i.MX6 SOC implementation.

For now we only support the following devices: * up to 4 Cortex A9 cores * A9 MPCORE (SCU, GIC, TWD) * 5 i.MX UARTs * 2 EPIT timers * 1 GPT timer * 3 I2C controllers * 7 GPIO controllers * 6 SDHC controllers * 5 SPI controllers * 1 CCM device * 1 SRC device * various ROM/RAM areas. Reviewed-by:

[Qemu-devel] [PATCH v6 2/6] i.MX: Add i.MX6 System Reset Controller device.

This controller is also present in i.MX5X devices but they are not yet emulated by QEMU. Reviewed-by: Peter Maydell Signed-off-by: Jean-Christophe Dubois --- Changes since V1: * Change "reset" sematic to mean full power cyvle. Changes since V2:

[Qemu-devel] [PATCH v6 4/6] i.MX: Add the Freescale SPI Controller

Signed-off-by: Jean-Christophe Dubois --- Changes since V1: * Access SPI slave only at a byte level. * rework the CS activation to avoid to reset access to SPI slaves. Changes since V2: * Added #include "qemu/osdep.h" * remove previous_level from state struct * save

[Qemu-devel] [PATCH v6 3/6] FIFO: Add a FIFO32 implementation

This one is build on top of the existing FIFO8 Reviewed-by: Peter Maydell Signed-off-by: Jean-Christophe Dubois --- Changes since V1: * None Changes since V2: * Added copyright * define Fifo32 as a struct containing Fifo8 * remove

[Qemu-devel] [PATCH v6 1/6] ARM: Factor out ARM on/off PSCI control functions

Split ARM on/off function from PSCI support code. This will allow to reuse these functions in other code. Signed-off-by: Jean-Christophe Dubois --- Changes since V1: * Not present on V1 Changes since V2: * Not present on V2 Changes since V3: * Move to a more

[Qemu-devel] [PATCH v6 0/6] Add i.MX6 (Single/Dual/Quad) support

This patch series adds support for the Freescale i.MX6 processor. For now we only support the following devices: * up to 4 Cortex A9 cores * A9 MPCORE (SCU, GIC, TWD) * 5 i.MX UARTs * 2 EPIT timers * 1 GPT timer * 7 GPIO controllers * 6 SDHC controllers * 5 SPI controllers * 1 CCM device * 1 SRC

Re: [Qemu-devel] Why is SeaBIOS used with -kernel?

On Fri, Apr 01, 2016 at 06:25:24PM -0400, Kevin O'Connor wrote: > I'm getting different results. When you have time we should probably > track down the discrepancy. Some of the difference is likely due to > different hardware (I'm using kvm on an old AMD machine) and some is > likely due to

Re: [Qemu-devel] [PATCH] doc: Flip bit sense for allowing trim during WRITE_ZEROES

On 04/02/2016 12:29 AM, Eric Blake wrote: Rather than requiring allocation by default and allowing trims only on request during WRITE_ZEROES, it seems like a better default is to allow server optimizations by default and require full allocation by specific request. Since WRITE_ZEROES is