From: Benjamin Herrenschmidt
This adds proper support for translating real mode addresses based
on the combination of HV and LPCR bits. This handles HRMOR offset
for hypervisor real mode, and both RMA and VRMA modes for guest
real mode. PAPR mode adjusts the offsets appropriately to match the
RMA
Hello,
Here are two more patches which are prereq for PowerNV.
I have modified the code to fit the modifications done early 2016 on
the mmu. I haven't seen any breakage in the tests but this clearly
needs a closer look by experts.
Thanks,
C.
Benjamin Herrenschmidt (2):
ppc: Add proper real
From: Benjamin Herrenschmidt
We were always advertising only 4K & 16M. Additionally the code wasn't
properly matching the page size with the PTE content, which meant we
could potentially hit an incorrect PTE if the guest used multiple sizes.
Finally, honor the CPU capabilities when decoding the
On Thu, Jun 23, 2016 at 12:46:46AM +0800, Wei Xu wrote:
> On 2016年06月22日 23:39, Eric Blake wrote:
> > On 06/22/2016 09:25 AM, Wei Xu wrote:
> > > There have been comments on this patch, but i forgot adding this patch to
> > > the list, just forward it again.
> > >
> > > When manage VMs via libvirt
On Mon, 27 Jun 2016 14:55:24 -0300
Eduardo Habkost wrote:
> On Thu, Jun 23, 2016 at 04:54:23PM +0200, Igor Mammedov wrote:
> > custom apic-id setter/getter doesn't do any property specific
> > checks anymorer, so clean it up and use more compact static
> > property DEFINE_PROP_UINT32 instead.
> >
Dear all,
On 24/11/2015 11:13, Pavel Fedin wrote:
> This series introduces support for in-kernel GICv3 ITS emulation.
> It is based on kernel API which is not released yet, therefore i post
> it as an RFC.
>
> Kernel patch sets which implement this functionality are:
> - [PATCH v3 00/16] KVM: arm
On Tue, Jun 28, 2016 at 10:36:23AM +0530, Nikunj A Dadhania wrote:
> David Gibson writes:
>
> > [ Unknown signature status ]
> > On Mon, Jun 27, 2016 at 03:41:06PM +0530, Nikunj A Dadhania wrote:
> >> Nikunj A Dadhania writes:
> >>
> >> > David Gibson writes:
> >> >
> >> >> [ Unknown signature
On Tue, Jun 28, 2016 at 07:24:16AM +0200, Greg Kurz wrote:
> On Tue, 28 Jun 2016 12:55:07 +1000
> David Gibson wrote:
>
> > On Mon, Jun 27, 2016 at 06:28:15PM +0200, Greg Kurz wrote:
> > > This fixes a potential QEMU crash introduced by commit 3b542549661.
> > >
> > > Signed-off-by: Greg Kurz
>
On 06/24/2016 02:08 PM, Jason Wang wrote:
On 2016年06月23日 18:48, Zhang Chen wrote:
On 06/22/2016 02:34 PM, Jason Wang wrote:
On 2016年06月22日 11:12, Zhang Chen wrote:
On 06/20/2016 08:14 PM, Dr. David Alan Gilbert wrote:
* Jason Wang (jasow...@redhat.com) wrote:
On 2016年06月14日 19:15,
Am 27.06.2016 um 17:09 schrieb Cornelia Huck:
On Mon, 27 Jun 2016 11:44:47 +0200
Peter Lieven wrote:
Hi, with the above patch applied:
commit 9f06e71a567ba5ee8b727e65a2d5347fd331d2aa
Author: Cornelia Huck
Date: Fri Jun 10 11:04:12 2016 +0200
virtio-pci: convert to ioeventfd callback
On Mon, Jun 27, 2016 at 07:48:23AM +0100, Mark Cave-Ayland wrote:
> On 21/06/16 14:48, Mark Cave-Ayland wrote:
>
> > On 21/06/16 11:28, Stefan Hajnoczi wrote:
> >
> >> On Tue, Jun 21, 2016 at 01:40:42AM -0400, Jeff Cody wrote:
> >>> This update should preserve git history, and allow seamless swit
On Sun, Jun 26, 2016 at 03:27:50PM +0200, Jan Kiszka wrote:
> On 2016-06-26 03:48, Peter Xu wrote:
> > On Sat, Jun 25, 2016 at 05:18:40PM +0200, Jan Kiszka wrote:
> >> On 2016-06-25 15:18, Peter Xu wrote:
> >>> On Sat, Jun 25, 2016 at 10:08:10AM +0200, Jan Kiszka wrote:
> >
> > [...]
> >
> >>> I
I'm running qemu-2.5.0 on ARM, and wine (wine-1.7, 1.8, wine-staging)
all seem to behave similarly; rename the winepreloader and you'll be
able to run winecfg, notepad run, a few installers do run and the
software runs. But Windows software LOVES using threads so you rapidly
end up with some other
On 06/27/2016 06:43 PM, Cédric Le Goater wrote:
> This test uses the palmetto platform and the AST2400 SPI controller to
> test the m25p80 flash module device model. The flash model is defined
> by the platform (n25q256a) and it would be nice to find way to control
> it, using a property probably.
On Mon, Jun 27, 2016 at 08:55:13AM +0200, Cédric Le Goater wrote:
> Hello,
>
> Here are a couple more patches on the exception model and LPCR which
> are surrounding the pnv core patches. The first is a prereq for all
> the patches to apply, and it did not seem too much of a problem adding
> it.
On Mon, Jun 27, 2016 at 01:25:03PM +0200, Thomas Huth wrote:
> Add "hcall-sprg0" (for H_SET_SPRG0), "hcall-copy" (for H_PAGE_INIT)
> and "hcall-debug" (for H_LOGICAL_CI_LOAD/STORE) to the property
> "ibm,hypertas-functions" to indicate that we support these hypercalls.
>
> Signed-off-by: Thomas Hu
Hi Alex,
On 2016/6/28 11:58, Alex Williamson wrote:
On Tue, 28 Jun 2016 11:26:33 +0800
Zhou Jie wrote:
Hi Alex,
The INTx/MSI part needs further definition for the user. Are we
actually completely tearing down interrupts with the expectation that
the user will re-enable them or are we just
On Tue, 28 Jun 2016 12:55:07 +1000
David Gibson wrote:
> On Mon, Jun 27, 2016 at 06:28:15PM +0200, Greg Kurz wrote:
> > This fixes a potential QEMU crash introduced by commit 3b542549661.
> >
> > Signed-off-by: Greg Kurz
> > ---
> > hw/ppc/spapr_cpu_core.c |3 +--
> > 1 file changed, 1 ins
David Gibson writes:
> [ Unknown signature status ]
> On Mon, Jun 27, 2016 at 03:41:06PM +0530, Nikunj A Dadhania wrote:
>> Nikunj A Dadhania writes:
>>
>> > David Gibson writes:
>> >
>> >> [ Unknown signature status ]
>> >> On Thu, Jun 23, 2016 at 11:17:28PM +0530, Nikunj A Dadhania wrote:
>>
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1131757
Title:
QEMU 1.4.0 fails to boot sparc64 linux image
Status in QEMU:
New
Bug description:
Hi!
I tried to boot sparc64 linux image
(htt
Hi all,
Thanks for the patch. I just tried, it seems to be not able to find the
disk when it try to start the installation. :(
...
Please specify the media from which you will install the Solaris Operating
Environment.
Media:
1. CD/DVD
2. Network File System
3. HTTP (Flash archive only)
4. FTP
On Tue, 28 Jun 2016 11:26:33 +0800
Zhou Jie wrote:
> Hi Alex,
>
> > The INTx/MSI part needs further definition for the user. Are we
> > actually completely tearing down interrupts with the expectation that
> > the user will re-enable them or are we just masking them such that the
> > user needs
On Mon, Jun 27, 2016 at 03:23:13PM +0530, Nikunj A Dadhania wrote:
> David Gibson writes:
>
> > [ Unknown signature status ]
> > On Thu, Jun 23, 2016 at 11:17:29PM +0530, Nikunj A Dadhania wrote:
> >> From: Benjamin Herrenschmidt
> >>
> >> This provides MMIO based ICP access as found on POWER8
On Mon, Jun 27, 2016 at 10:55:03AM -0500, alar...@ddci.com wrote:
> David Gibson wrote on 06/27/2016 12:32:13
> AM:
>
> > From: David Gibson
> > To: alar...@ddci.com
> > Cc: ag...@suse.de, qemu-devel@nongnu.org, qemu-...@nongnu.org
> > Date: 06/27/2016 12:30 AM
> > Subject: Re: [PATCH] target-p
On Mon, Jun 27, 2016 at 03:41:06PM +0530, Nikunj A Dadhania wrote:
> Nikunj A Dadhania writes:
>
> > David Gibson writes:
> >
> >> [ Unknown signature status ]
> >> On Thu, Jun 23, 2016 at 11:17:28PM +0530, Nikunj A Dadhania wrote:
> >>> From: Benjamin Herrenschmidt
> >>>
> >>> The existing im
From: Peter Lieven
commit fefe2a78 accidently dropped the code path for injecting
raw packets. This feature is needed for sending gratuitous ARPs
after an incoming migration has completed. The result is increased
network downtime for vservers where the network card is not virtio-net
with the VIRT
From: Ashijeet Acharya
Use socket_*() functions from include/qemu/sockets.h instead of
listen()/bind()/connect()/parse_host_port(). socket_*() fucntions are
QAPI based and this patch performs this api conversion since
everything will be using QAPI based sockets in the future. Also add a
helper f
From: KarimAllah Ahmed
When a PCI device lives behind an IOMMU, it should use 'pci_dma_*' family of
functions when any transfer from/to guest memory is required while
'cpu_physical_memory_*' family of functions completely bypass any MMU/IOMMU in
the system.
vmxnet3 in some places was using 'cpu_
From: David Vrabel
Commit 9d29cdeaaca3a0383af764000b71492c4fc67c6e (rtl8139: port
TallyCounters to vmstate) introduced in incompatibility in the v4
format as it omitted the RxOkMul counter.
There are presumably no users that were impacted by the v4 to v4'
breakage, so increase the save version t
The following changes since commit 14e60aaece20a1cfc059a69f6491b0899f9257a8:
hw/net/e1000: Don't use *_to_cpup() (2016-06-27 16:39:56 +0100)
are available in the git repository at:
https://github.com/jasowang/qemu.git tags/net-pull-request
for you to fetch changes up to c508277335e3b6b20cf1
From: Prasad J Pandit
When processing MIPSnet I/O port write operation, it uses a
transmit buffer tx_buffer[MAX_ETH_FRAME_SIZE=1514]. Two indices
's->tx_written' and 's->tx_count' are used to control data written
to this buffer. If the two were to be equal before writing, it'd
lead to an OOB writ
Hi Alex,
The INTx/MSI part needs further definition for the user. Are we
actually completely tearing down interrupts with the expectation that
the user will re-enable them or are we just masking them such that the
user needs to unmask? Also note that not all devices support DisINTx.
After re
On 06/16/2016 06:25 AM, Markus Armbruster wrote:
> Markus Armbruster writes:
>
>> Eric Blake writes:
>>
>>> When an event has data that is not boxed, we are exposing all of
>>> its members alongside our local variables. So far, we haven't
>>> hit a collision, but it may be a matter of time befo
On Mon, Jun 27, 2016 at 06:38:35PM +0300, Marcel Apfelbaum wrote:
> Since iommu devices can be created with '-device' there is
> no need to keep iommu as machine and mch property.
Doesn't this break backwards compatibility?
>
> Signed-off-by: Marcel Apfelbaum
> ---
> hw/core/machine.c
On Mon, Jun 27, 2016 at 06:38:31PM +0300, Marcel Apfelbaum wrote:
> Mac99's PCI root bus is not part of a host bridge,
> realize it manually.
Um.. how did this ever work?
>
> Signed-off-by: Marcel Apfelbaum
> ---
> hw/ppc/mac_newworld.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a
On Mon, Jun 27, 2016 at 06:28:15PM +0200, Greg Kurz wrote:
> This fixes a potential QEMU crash introduced by commit 3b542549661.
>
> Signed-off-by: Greg Kurz
> ---
> hw/ppc/spapr_cpu_core.c |3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
Ugh. The existing code is wrong in the case
On 06/14/2016 07:46 AM, Eric Blake wrote:
> On 06/14/2016 07:24 AM, Markus Armbruster wrote:
>> Eric Blake writes:
>>
>>> We were previously enforcing that all flat union branches were
>>> found in the corresponding enum, but not that all enum values
>>> were covered by branches. The resulting ge
This was the only exceptional module init function that does something
else than a simple list of bdrv_register() calls, in all the block
drivers.
The qcrypto_hash_supports is actually a static check, determined at
compile time. Follow the block-job-$(CONFIG_FOO) convention for
consistency.
Sign
On Mon, 06/27 17:47, Denis V. Lunev wrote:
> From: Evgeny Yakovlev
>
> Some guests (win2008 server for example) do a lot of unnecessary
> flushing when underlying media has not changed. This adds additional
> overhead on host when calling fsync/fdatasync.
>
> This change introduces a dirty flag
On Mon, Jun 27, 2016 at 3:04 PM, wrote:
> From: Corey Minyard
>
> Change 2293c27faddf (i2c: implement broadcast write) added broadcast
> capability to the I2C bus, but it broke SMBus read transactions.
> An SMBus read transaction does two i2c_start_transaction() calls
> without an intervening i2
This avoids needing to save state before every FP operation.
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/fop_helper.c | 17 +
target-sparc/translate.c | 6 +-
2 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/target-sparc/f
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 45 +++--
1 file changed, 27 insertions(+), 18 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 590a58d..e7691e4 100644
--- a/
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 122 +++
1 file changed, 122 insertions(+)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 2ea6964..cee1e5c 100644
--- a/target-sparc/
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index ed0853a..dea1b5f 100644
--- a/target-sparc/translate.c
+++ b/target-spa
Reduces the argument count for helper_ld_asi; do helper_st_asi
for consistency.
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/helper.h | 4 +--
target-sparc/ldst_helper.c | 73 ++
target-sparc/translate.c | 58
By arranging for explicit writes to cpu_fsr after floating point
operations, we are able to mark the helpers as not writing to
tcg globals, which means that we don't need to invalidate the
integer register set across said calls.
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
Also implement a few more twinx asis.
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/helper.h | 2 +-
target-sparc/ldst_helper.c | 156 -
target-sparc/translate.c | 12 +++-
3 files changed, 120 insertions(+)
We've now implemented all fp asis inline, except for the no-fault
memory reads. The latter can be passed directly to helper_ld_asi.
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/helper.h | 2 -
target-sparc/ldst_helper.c | 148 --
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/ldst_helper.c | 459 +++--
target-sparc/translate.c | 6 +-
2 files changed, 235 insertions(+), 230 deletions(-)
diff --git a/target-sparc/ldst_helper.c b/target-sparc/lds
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/ldst_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 23840db..3700ca1 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sp
We now have a single copy of gen_ld_asi, gen_st_asi,
gen_swap_asi, and everything uses gen_get_asi.
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 285 ++-
1 file changed, 131 insertions(+), 154 deletions
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 45 +
1 file changed, 45 insertions(+)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 0b29aff..2ea6964 100644
--- a/target-sparc/tran
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 48 +---
1 file changed, 13 insertions(+), 35 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 885fa58..e7120f8 100644
---
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 115 ++-
1 file changed, 103 insertions(+), 12 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index e7120f8..0d5149d 100644
--
Copied from tag v4.2, 64291f7db5bd8150a74ad2036f1037e6a0428df2.
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/asi.h | 297 +
1 file changed, 297 insertions(+)
create mode 100644 target-sparc/asi.h
diff --git
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 104 ---
1 file changed, 90 insertions(+), 14 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 8865864..55364ad 100644
---
Knowing the value of %asi at translation time means that we
can handle the common settings without a function call.
The steady state appears to be %asi == ASI_P, so that sparcv9
code can use offset forms of lda/sta. The %asi register gets
pushed and popped on entry to certain functions, but it ra
Replace gen_get_asi, and use it for both 32-bit and 64-bit.
For v8, do supervisor and immediate checks here.
Also, move save_state and TB ending into the respective
subroutines, out of disas_sparc_insn.
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/translate.c
Doing this instead of saving the raw PS_PRIV and TL. This means
that all nucleus mode TBs (TL > 0) can be shared. This fixes a
bug in that we didn't include HS_PRIV in the TB flags, and so could
produce incorrect TB matches for hypervisor state.
The LSU and DMMU states were unused by the transla
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/asi.h | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/target-sparc/asi.h b/target-sparc/asi.h
index aace6f3..c9a1849 100644
--- a/target-sparc/asi.h
+++ b/target-sparc/asi.
The primary focus of this patch set is to reduce the number of
helpers that modify TCG globals, and thus increase the lifetime
of those globals within each TB, and thus decrease the number
of times that tcg must spill and fill them from backing store.
As a byproduct, I also implement the bulk of t
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 532ad3e..886e132 100644
--- a/target-sparc/
The global is only ever read for one insn; we can just as well
use a load from env instead and generate the same code. This
also allows us to indicate the the associated helpers do not
touch TCG globals.
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/helper.h
Quite a few helpers do not modify tcg globals but did not so indicate.
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/helper.h | 48
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/target-sparc/hel
This unifies quite a few duplicate code fragments.
Reviewed-By: Artyom Tarasenko
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 75 +---
1 file changed, 20 insertions(+), 55 deletions(-)
diff --git a/target-sparc/translate.c b/target
On 06/27/2016 10:47 AM, Denis V. Lunev wrote:
> From: Evgeny Yakovlev
>
> Due to changes in flush behaviour clean disks stopped generating
> flush_to_disk events and IDE and AHCI tests that test flush commands
> started to fail.
>
> This change adds additional DMA writes to affected tests befo
On Mon, 2016-06-27 at 17:53 -0400, Pranith Kumar wrote:
> Tracing configurations error out currently as follows:
>
> /home/travis/build/pranith/qemu/hw/misc/aspeed_scu.c: In function
> ‘aspeed_scu_read’:
> /home/travis/build/pranith/qemu/hw/misc/aspeed_scu.c:130:9: error: implicit
> declaration
On 06/27/2016 04:12 PM, Thomas Huth wrote:
> event_notifier_init() can fail in real life, for example when there
> are not enough open file handles available (EMFILE) when using a lot
> of devices. So instead of leaving the average user with a cryptic
> error number only, print out a proper error m
event_notifier_init() can fail in real life, for example when there
are not enough open file handles available (EMFILE) when using a lot
of devices. So instead of leaving the average user with a cryptic
error number only, print out a proper error message with strerror()
instead, so that the user ha
From: Corey Minyard
Change 2293c27faddf (i2c: implement broadcast write) added broadcast
capability to the I2C bus, but it broke SMBus read transactions.
An SMBus read transaction does two i2c_start_transaction() calls
without an intervening i2c_end_transfer() call. This will
result in i2c_start
On 06/27/2016 02:48 PM, Peter Maydell wrote:
On 27 June 2016 at 22:43, Richard Henderson wrote:
All you need to do is byte-reverse the data.
bswap(a + b) == bswap(a) + bswap(b).
?
0xFF + 0xFF == 0x1FE, bswap(0x1FE) == 0xFE01
bswap(0xFF) + bswap(0xFF) == 0xFF00 + 0xFF00 == 0x1F
Tracing configurations error out currently as follows:
/home/travis/build/pranith/qemu/hw/misc/aspeed_scu.c: In function
‘aspeed_scu_read’:
/home/travis/build/pranith/qemu/hw/misc/aspeed_scu.c:130:9: error: implicit
declaration of function ‘qemu_log_mask’ [-Werror=implicit-function-declaration]
Hi All,
I want to count number of host instructions (only for guest code) executed
when qemu emulates an application. I wonder if helper functions are
supported with tcg back end as well, which can be a possible solution for
the mentioned problem ? If not, is there any other solution in someone's
On 27 June 2016 at 22:43, Richard Henderson wrote:
> All you need to do is byte-reverse the data.
>
> bswap(a + b) == bswap(a) + bswap(b).
?
0xFF + 0xFF == 0x1FE, bswap(0x1FE) == 0xFE01
bswap(0xFF) + bswap(0xFF) == 0xFF00 + 0xFF00 == 0x1FE00
(or 0xFE00 with truncate to 32-b
On 06/27/2016 02:19 PM, Emilio G. Cota wrote:
Host endian operation?
I forgot to add byte ordering in the cover letter under "why this is
an RFC" -- I admit I'm confused by all the macro trickery done for
regular loads and stores.
We store data in memory as per the guests' byte ordering, right
By all means, feel free to provide me instructions on how to debug this
myself, so I can help others in the future, although I understand that
can be more time consuming. If anyone would rather prefer talking on
IRC, just let me know the network and channel. Thanks
--
You received this bug notifi
On Mon, Jun 27, 2016 at 13:27:35 -0700, Richard Henderson wrote:
> On 06/27/2016 12:01 PM, Emilio G. Cota wrote:
> >This patch only adds the helpers. Functions to invoke the helpers
> >from translated code are generated in subsequent patches.
> >
> >Signed-off-by: Emilio G. Cota
> >---
> > target-
** Changed in: qemu
Status: Fix Committed => Fix Released
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1252270
Title:
installing NT4 on MIPS Magnum/Jazz asserts
Status in QEMU:
Fix Relea
** Changed in: qemu
Status: Fix Committed => Fix Released
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1263747
Title:
Arm64 fails to run a binary which runs OK on real hardware
Status in Q
** Changed in: qemu
Status: Fix Committed => Fix Released
--
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devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1288385
Title:
VFIO passthrough causes assertation failure
Status in QEMU:
Fix Rele
** Changed in: qemu
Status: Fix Committed => Fix Released
--
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devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1328996
Title:
[AArch64] - blr x30 is handled incorrectly
Status in QEMU:
Fix Relea
On 03/06/16 23:40, Alex Bennée wrote:
> diff --git a/cpus.c b/cpus.c
> index 1694ce9..12e04c9 100644
> --- a/cpus.c
> +++ b/cpus.c
> @@ -1208,9 +1208,29 @@ static int tcg_cpu_exec(CPUState *cpu)
> return ret;
> }
>
> +/* Single-threaded TCG
> + *
> + * In the single-threaded case each vCPU
On Mon, Jun 27, 2016 at 13:11:28 -0700, Richard Henderson wrote:
> On 06/27/2016 12:01 PM, Emilio G. Cota wrote:
> >Signed-off-by: Emilio G. Cota
> >---
> > softmmu_template.h | 58
> > ++
> > tcg/tcg.h | 16 +++
> > 2 files c
On 03/06/16 23:40, Alex Bennée wrote:
> diff --git a/cpus.c b/cpus.c
> index 4cc2ce6..1694ce9 100644
> --- a/cpus.c
> +++ b/cpus.c
> @@ -25,6 +25,7 @@
> /* Needed early for CONFIG_BSD etc. */
> #include "qemu/osdep.h"
> #include "qemu-common.h"
> +#include "qemu/config-file.h"
> #include "cpu.h
On 06/27/2016 01:41 PM, Emilio G. Cota wrote:
Supporting 64-bit hosts on 32-bit guests has the problem of non-atomicity
of 64-bit accesses, however.
It does. It would be possible to do something with armv7 and i686 hosts, as
64-bit atomic ops exist, but it's probably not worth the effort.
A
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
qemu segfault when starting virt-manager
Status in QEMU:
Fix Release
Changing status to "Fix Released" since this should have been included
since a couple of releases now.
** Changed in: qemu
Status: Fix Committed => Fix Released
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** Changed in: qemu
Status: Fix Committed => Fix Released
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https://bugs.launchpad.net/bugs/788701
Title:
qemu-user fails to run rpcgen (i386, x86_64)
Status in QEMU:
Fix Rele
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
qemu core dumps with -serial mon:vc
Status in QEMU:
Fix Released
Bu
If I've got the previous comments right, this was not a QEMU bug, but a
bug in "mount" and the guest kernel ... so closing this QEMU ticket here
now.
** Changed in: qemu
Status: Fix Committed => Fix Released
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On Mon, Jun 27, 2016 at 13:07:42 -0700, Richard Henderson wrote:
> On 06/27/2016 12:01 PM, Emilio G. Cota wrote:
> >This set of locks will allow us to correctly emulate cmpxchg16
> >in a parallel TCG. The key observation is that no architecture
> >supports 16-byte regular atomic load/stores; only "
Dear Paolo,
Paolo Bonzini writes:
>> After applying your series on top of f12103af and running "./configure"
>> in a clean working directory, I get the following errors for "make
>> check-source":
>>
>> $ make check-source
>> egrep: config-host.h: No such file or directory
>> egrep: qmp-command
Hello,
Thomas Huth, on Sun 26 Jun 2016 10:04:02 +0200, wrote:
> Provide basic support for stateless DHCPv6 (see RFC 3736) so
> that guests can also automatically boot via IPv6 with SLIRP
> (for IPv6 network booting, see RFC 5970 for details).
Cool :)
I'm here commenting in my reading order, not
On 06/27/2016 12:01 PM, Emilio G. Cota wrote:
This patch only adds the helpers. Functions to invoke the helpers
from translated code are generated in subsequent patches.
Signed-off-by: Emilio G. Cota
---
target-i386/helper.h | 34 ++
target-i386/mem_helper.c
Which version of QEMU are you using? How did you start QEMU (i.e. which
kind of graphics card did you specify)? And which version of CentOS are
you using for the guest?
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On 06/27/2016 12:01 PM, Emilio G. Cota wrote:
Signed-off-by: Emilio G. Cota
---
softmmu_template.h | 58 ++
tcg/tcg.h | 16 +++
2 files changed, 74 insertions(+)
diff --git a/softmmu_template.h b/softmmu_template.h
index
On 06/27/2016 12:01 PM, Emilio G. Cota wrote:
This set of locks will allow us to correctly emulate cmpxchg16
in a parallel TCG. The key observation is that no architecture
supports 16-byte regular atomic load/stores; only "locked" accesses
(e.g. via cmpxchg16b on x86) are allowed, and therefore w
** Attachment added: "cmdline"
https://bugs.launchpad.net/qemu/+bug/1596579/+attachment/4691252/+files/cmdline
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Title:
segfault upon reboot
From: Fam Zheng
We only care about the associated backend, so blk_drain is more
appropriate here.
Signed-off-by: Fam Zheng
Reviewed-by: Kevin Wolf
Reviewed-by: John Snow
Message-id: 20160612065603.21911-1-f...@redhat.com
Signed-off-by: John Snow
---
hw/ide/macio.c | 2 +-
1 file changed, 1
Thomas Huth, on Mon 27 Jun 2016 12:41:36 +0200, wrote:
> Commit fad7fb9ccd8013ea03 ("Add IPv6 support to the TFTP code")
> refactored some common code for preparing the mbuf into a new
> function called tftp_prep_mbuf_data(). One part of this common
> code is to do a "memset(m->m_data, 0, m->m_siz
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