On 07/09/2016 04:34 AM, Mark Cave-Ayland wrote:
On 04/07/16 17:46, Michael S. Tsirkin wrote:
From: Marcel Apfelbaum
Skip bus_master_enable region creation on PCI device init
in order to be sure the IOMMU device (if present) would
be created in advance. Add this memory region at machine_done t
On 2016-07-05 10:19, Peter Xu wrote:
> Remove VT-d calls in common q35 codes. Instead, we provide a general
> find_add_as() for x86-iommu type.
>
> Signed-off-by: Peter Xu
> ---
> hw/i386/intel_iommu.c | 15 ---
> include/hw/i386/intel_iommu.h | 5 -
> include/hw/i386/x8
On 07/09/2016 02:43 AM, Mark Cave-Ayland wrote:
> On 01/07/16 07:41, David Gibson wrote:
>
>> From: Benjamin Herrenschmidt
>>
>> The architecture specifies that any instruction that sets MSR:PR will also
>> set MSR:EE, IR and DR.
>>
>> Signed-off-by: Benjamin Herrenschmidt
>> Signed-off-by: Cédr
On Sat, 2016-07-09 at 10:16 +0200, Cédric Le Goater wrote:
> The login prompt is reached with a full Darwin disk image.
>
> So I must be missing a scenario :/
Yes same here, Darwin worked fine, but I did reproduce the problem with
OS 9. See the fix I sent.
Cheers,
Ben.
On 07/09/2016 10:25 AM, Benjamin Herrenschmidt wrote:
> On Sat, 2016-07-09 at 10:16 +0200, Cédric Le Goater wrote:
>> The login prompt is reached with a full Darwin disk image.
>>
>> So I must be missing a scenario :/
>
> Yes same here, Darwin worked fine, but I did reproduce the problem with
> O
On 09/07/16 04:08, Benjamin Herrenschmidt wrote:
> On Sat, 2016-07-09 at 13:00 +1000, Benjamin Herrenschmidt wrote:
>>> Additionally, hreg_compute_mem_idx() will treat PR=1 as DR=1/IR=1
>>> as well ! That means that if those old processors allow PR=1 and IR
>>> or DR=0 and MacOS uses it, we do hav
On 09/07/16 08:07, Marcel Apfelbaum wrote:
> On 07/09/2016 04:34 AM, Mark Cave-Ayland wrote:
>> On 04/07/16 17:46, Michael S. Tsirkin wrote:
>>
>>> From: Marcel Apfelbaum
>>>
>>> Skip bus_master_enable region creation on PCI device init
>>> in order to be sure the IOMMU device (if present) would
On 09/07/16 04:42, Benjamin Herrenschmidt wrote:
> On Sat, 2016-07-09 at 13:41 +1000, Benjamin Herrenschmidt wrote:
>> MacOS uses an architecturally illegal MSR combination that
>> seems nonetheless supported by 32-bit processors, which is
>> to have MSR[PR]=1 and one or more of MSR[DR/IR/EE]=0.
>
On 07/09/2016 02:43 AM, Mark Cave-Ayland wrote:
On 01/07/16 07:41, David Gibson wrote:
From: Benjamin Herrenschmidt
The architecture specifies that any instruction that sets MSR:PR
will also
set MSR:EE, IR and DR.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: C?dric Le Goater
Hi T.Huth,
is possible add the sdl patches on BigEndian on Qemu 2.5.1 ?
the lastest are not initializing the display i dont understand what appening
with last qemu on Big Endian.
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http
Note that x86_64 has only _rt signal handlers. This implementation
attempts to share code with the x86_32 implementation.
Reported-by: Timothy Pearson
Suggested-by: Peter Maydell
Signed-off-by: Allan Wirth
---
linux-user/signal.c | 344 ---
targ
On Mon, Jul 4, 2016 at 10:57 AM, mar.krzeminski
wrote:
>
>
> W dniu 04.07.2016 o 14:18, Cédric Le Goater pisze:
>>
>> Some SPI controllers, such as the Aspeed AST2400, have a mode in which
>> accesses to the flash content are no different than doing MMIOs. The
>> controller generates all the neces
Hi Alex,
The variable clearly isn't visible to the user, so the user can know
whether the kernel supports this feature, but not whether the feature
is currently active. Perhaps there's no way to avoid races completely,
but don't you expect that if we define that certain operations are
blocked a
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