On 10/13/2016 02:51 AM, David Gibson wrote:
> On Mon, Oct 03, 2016 at 09:24:43AM +0200, Cédric Le Goater wrote:
>> Now that we are using real HW ids for the cores in PowerNV chips, we
>> can route the XSCOM accesses to them. We just need to attach a
>> specific XSCOM memory region to each core in t
+-- On Wed, 12 Oct 2016, Peter Maydell wrote --+
| > -while (gtb->compare < update.new) {
| > +if (gtb->compare < update.new) {
| >
| > +inc = update.new - gtb->compare - 1;
|
| Can you explain why the '- 1' here ?
I think I did that because while was
On October 13, 2016 2:09 PM, Emil Condrea wrote:
>As you suggested, I've dropped the all patches for xen_frontend.
>
>Emil
>
>On Wed, Oct 12, 2016 at 2:00 PM, Paolo Bonzini wrote:
>>
>>
>> On 09/10/2016 21:50, Emil Condrea wrote:
>>> On Tue, Oct 4, 2016 at 11:06 AM, Paolo Bonzini
>wrote:
>>
"Dr. David Alan Gilbert" writes:
> * Markus Armbruster (arm...@redhat.com) wrote:
>> Marc-André Lureau writes:
>>
>> > This option does nothing since commit 06ac27f. Deprecate it.
>> >
>> > Signed-off-by: Marc-André Lureau
>> > ---
>> > vl.c | 11 +++
>> > includ
Eric Blake writes:
> On 10/12/2016 10:47 AM, Vladimir Sementsov-Ogievskiy wrote:
>> HI all!
>>
>> My questions is: what are general recommendations in Qemu for return
>> code, if we have Error **errp?
>> What should I prefer: errp, duplicated by int return code, or void
>> functions with errp?
>
On 10/13/2016 04:52 AM, David Gibson wrote:
> On Mon, Oct 03, 2016 at 09:24:44AM +0200, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt
>>
>> The LPC (Low Pin Count) interface on a POWER8 is made accessible to
>> the system through the ADU (XSCOM interface). This interface is part
>> of se
On 10/13/2016 02:41 AM, David Gibson wrote:
> On Mon, Oct 03, 2016 at 09:24:42AM +0200, Cédric Le Goater wrote:
>> On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves
>> as a backbone to connect different units of the system. The host
>> firmware connects to the PIB through a bridg
Prepare xen_be_del_xendev to be shared with frontends:
* xen_be_del_xendev -> xen_pv_del_xendev
Signed-off-by: Emil Condrea
Acked-by: Anthony PERARD
Reviewed-by: Quan Xu
---
hw/xen/xen_backend.c | 2 +-
hw/xen/xen_pvdev.c | 2 +-
include/hw/xen/xen_pvdev.h | 2 +-
3 files change
Prepare xen_be_printf to be used by both backend and frontends:
* xen_be_printf -> xen_pv_printf
Signed-off-by: Emil Condrea
Acked-by: Anthony PERARD
---
hw/block/xen_disk.c| 58 +++---
hw/char/xen_console.c | 10
hw/display/xenfb.c
Prepare xen_be_evtchn_event to be shared with frontends:
* xen_be_evtchn_event -> xen_pv_evtchn_event
Signed-off-by: Emil Condrea
Acked-by: Anthony PERARD
Reviewed-by: Quan Xu
---
hw/xen/xen_backend.c | 2 +-
hw/xen/xen_pvdev.c | 2 +-
include/hw/xen/xen_pvdev.h | 2 +-
3 files
As you suggested, I've dropped the all patches for xen_frontend.
Emil
On Wed, Oct 12, 2016 at 2:00 PM, Paolo Bonzini wrote:
>
>
> On 09/10/2016 21:50, Emil Condrea wrote:
>> On Tue, Oct 4, 2016 at 11:06 AM, Paolo Bonzini wrote:
>>>
>>>
>>> On 04/10/2016 08:43, Emil Condrea wrote:
xen_be_fr
Prepare xen_be_find_xendev to be shared with frontends:
* xen_be_find_xendev -> xen_pv_find_xendev
Signed-off-by: Emil Condrea
Acked-by: Anthony PERARD
Reviewed-by: Quan Xu
---
hw/display/xenfb.c | 4 ++--
hw/xen/xen_backend.c | 2 +-
hw/xen/xen_pvdev.c | 2 +-
include/h
Prepare xen_be_unbind_evtchn to be shared with frontends:
* xen_be_unbind_evtchn -> xen_pv_unbind_evtchn
Signed-off-by: Emil Condrea
Acked-by: Anthony PERARD
Reviewed-by: Quan Xu
---
hw/block/xen_disk.c| 2 +-
hw/char/xen_console.c | 2 +-
hw/display/xenfb.c | 2 +-
hw/ne
+ cc Paolo Bonzini
On Thu, Oct 13, 2016 at 9:01 AM, Emil Condrea wrote:
> This patch series was splitted from QEMU:Xen stubdom vTPM for HVM virtual
> machine
> http://markmail.org/message/fkix7g3a5zdj7lvr
>
> It contains a reorganization of xen backend and frontend functions together
> with code
Prepare xen_be_send_notify to be shared with frontends:
* xen_be_send_notify -> xen_pv_send_notify
Signed-off-by: Emil Condrea
Acked-by: Anthony PERARD
Reviewed-by: Quan Xu
---
hw/block/xen_disk.c| 4 ++--
hw/char/xen_console.c | 4 ++--
hw/display/xenfb.c | 8
h
The name of the functions moved:
* xen_be_evtchn_event
* xen_be_unbind_evtchn
* xen_be_send_notify
Signed-off-by: Emil Condrea
---
hw/xen/xen_backend.c | 35 ---
hw/xen/xen_pvdev.c | 35 +++
include/hw/xen/xen_b
The purpose of the new file is to store generic functions shared by frontend
and backends such as xenstore operations, xendevs.
Signed-off-by: Quan Xu
Signed-off-by: Emil Condrea
---
hw/xen/Makefile.objs | 2 +-
hw/xen/xen_backend.c | 126 +---
* move xendevs qtail to xen_pvdev.c
* change xen_be_get_xendev to use a new function: xen_pv_insert_xendev
Signed-off-by: Emil Condrea
---
hw/xen/xen_backend.c | 51 +--
hw/xen/xen_pvdev.c | 57
The name of the functions moved to xen_pvdev.c:
* xenstore_cleanup_dir
* xen_config_cleanup
* xenstore_mkdir
Signed-off-by: Emil Condrea
Acked-by: Anthony PERARD
---
hw/xen/xen_backend.c | 49 -
hw/xen/xen_pvdev.c | 51 +++
Fixes:
* WARNING: line over 80 characters
Signed-off-by: Emil Condrea
---
hw/block/xen_disk.c | 3 ++-
hw/char/xen_console.c| 6 --
hw/display/xenfb.c | 30 --
hw/net/xen_nic.c | 12
hw/xen/xen_backend.c
Fixes the following errors:
* ERROR: line over 90 characters
* ERROR: code indent should never use tabs
* ERROR: space prohibited after that open square bracket '['
* ERROR: do not initialise statics to 0 or NULL
* ERROR: "(foo*)" should be "(foo *)"
Signed-off-by: Emil Condrea
---
hw/char/
This patch series was splitted from QEMU:Xen stubdom vTPM for HVM virtual
machine
http://markmail.org/message/fkix7g3a5zdj7lvr
It contains a reorganization of xen backend and frontend functions together
with code style fixes.
Common functions shared by backends and frontends are moved to xen_pvde
* xenstore_update -> xen_pvdev.c
Signed-off-by: Emil Condrea
---
hw/xen/xen_backend.c | 30 +++---
hw/xen/xen_pvdev.c | 23 +++
include/hw/xen/xen_backend.h | 3 +++
include/hw/xen/xen_pvdev.h | 1 +
4 files changed, 30 insertion
From: Thomas Huth
The current code uses pa_features_206 for POWERPC_MMU_2_06, and
for everything else, it uses pa_features_207. This is bad in some
cases because there is also a "degraded" MMU version of ISA 2.06,
called POWERPC_MMU_2_06a, which should of course use the flags for
2.06 instead. An
From: Cornelia Huck
Update headers against 4.8-rc2.
Signed-off-by: Cornelia Huck
---
include/standard-headers/linux/input-event-codes.h | 32
include/standard-headers/linux/input.h | 1 +
include/standard-headers/linux/virtio_config.h | 10 ++-
include/standard-header
On Wed, Oct 12, 2016 at 10:53:12AM +0200, Cédric Le Goater wrote:
> On 10/11/2016 12:24 PM, David Gibson wrote:
> > On Mon, Oct 10, 2016 at 02:56:25PM +0200, Cédric Le Goater wrote:
> >>
> @@ -227,11 +227,44 @@ static void ppc_powernv_init(MachineState *machine)
> snprintf(chip_n
From: Thomas Huth
KVM-PR currently does not support transactional memory, and the
implementation in TCG is just a fake. We should not announce TM
support in the ibm,pa-features property when running on such a
system, so disable it by default and only enable it if the KVM
implementation supports i
在 2016-10-13 3:46, Max Reitz 写道:
On 12.10.2016 10:55, Hao QingFeng wrote:
Max,
Just a common question for this case, if sshx block driver wasn't built
into qemu-img, this case would fail as below:
Good point, and thanks for bringing it up, but it's not directly linked
to this series other th
On Mon, Oct 03, 2016 at 09:24:44AM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> The LPC (Low Pin Count) interface on a POWER8 is made accessible to
> the system through the ADU (XSCOM interface). This interface is part
> of set of units connected together via a local OPB (On-
The following changes since commit 1dc33ed90bf1fe1c2014dffa0d9e863c520d953a:
Update version for v2.7.0 release (2016-09-02 13:44:11 +0100)
are available in the git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-2.7-20161013
for you to fetch changes up to 2e68f28854f0120c9a938
On Mon, Oct 03, 2016 at 09:24:42AM +0200, Cédric Le Goater wrote:
> On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves
> as a backbone to connect different units of the system. The host
> firmware connects to the PIB through a bridge unit, the
> Alter-Display-Unit (ADU), which giv
On Thu, Oct 13, 2016 at 01:52:55PM +1100, David Gibson wrote:
> On Mon, Oct 03, 2016 at 09:24:44AM +0200, Cédric Le Goater wrote:
> > From: Benjamin Herrenschmidt
> >
> > The LPC (Low Pin Count) interface on a POWER8 is made accessible to
> > the system through the ADU (XSCOM interface). This int
On Mon, Oct 03, 2016 at 09:24:45AM +0200, Cédric Le Goater wrote:
> As Qemu only supports a single instance of the ISA bus, we use the LPC
> controller of chip 0 to create one and plug in a couple of useful
> devices, like an UART and RTC. An IPMI BT device, which is also an ISA
> device, can be de
From: Thomas Huth
The function spapr_populate_cpu_dt() has become quite big
already, and since we likely have to extend the pa-features
property for every new processor generation, it is nicer
if we put the related code into a separate function.
Signed-off-by: Thomas Huth
Reviewed-by: Cédric Le
On Wed, Oct 12, 2016 at 10:38:53AM +0530, Nikunj A Dadhania wrote:
> Add required helpers (GEN_XX2FORM_EO) for supporting this instruction.
>
> xxbrh: VSX Vector Byte-Reverse Halfword
> xxbrw: VSX Vector Byte-Reverse Word
> xxbrd: VSX Vector Byte-Reverse Doubleword
> xxbrq: VSX Vector Byte-Reverse
On Wed, Oct 12, 2016 at 10:38:52AM +0530, Nikunj A Dadhania wrote:
> Vector Integer Negate Instructions:
>
> vnegw: Vector Negate Word
> vnegd: Vector Negate Doubleword
>
> Signed-off-by: Nikunj A Dadhania
> ---
> target-ppc/helper.h | 2 ++
> target-ppc/int_helper.c
On Mon, Oct 03, 2016 at 09:24:43AM +0200, Cédric Le Goater wrote:
> Now that we are using real HW ids for the cores in PowerNV chips, we
> can route the XSCOM accesses to them. We just need to attach a
> specific XSCOM memory region to each core in the appropriate window
> for the core number.
>
>
On Wed, Oct 12, 2016 at 10:38:51AM +0530, Nikunj A Dadhania wrote:
> Vector Extend Sign Instructions:
>
> vextsb2w: Vector Extend Sign Byte To Word
> vextsh2w: Vector Extend Sign Halfword To Word
> vextsb2d: Vector Extend Sign Byte To Doubleword
> vextsh2d: Vector Extend Sign Halfword To Doublewor
On Wed, Oct 12, 2016 at 4:04 PM, Stefan Hajnoczi wrote:
> Perhaps this approach can be prototyped with mprotect and a SIGSEGV
> handler if anyone wants to get async savevm going. I don't know if
> there are any disadvantages to mprotecting guest RAM that the kvm kernel
> module is using. Hopeful
On Tue, Oct 11, 2016 at 5:20 PM, Anthony PERARD
wrote:
> On Tue, Oct 04, 2016 at 09:43:31AM +0300, Emil Condrea wrote:
>> Fixes:
>> * WARNING: line over 80 characters
>>
>> Signed-off-by: Emil Condrea
>> ---
>> hw/block/xen_disk.c | 3 ++-
>> hw/char/xen_console.c| 6 --
>
Actually I've split fixing coding style in 2 patches: one for errors and
one for warnings. In this patch some resolve the error
"code indent should never use tabs" but if on the same line there is a
warning about line exceeding 80 characters, it will be fixed in
"Fix coding style warnings" patch.
Yes, I think the limit to apply to xattr size in 9pfs is the same as the
Linux xattr size limit, I will try to find this limit.
Thanks.
On 2016-10-13 4:49 GMT+08:00 Eric Blake wrote:
> On 10/12/2016 08:23 AM, Greg Kurz wrote:
> >
> > But in fact, I'm afraid we have a more serious problem here..
> From: Kirti Wankhede [mailto:kwankh...@nvidia.com]
> Sent: Thursday, October 13, 2016 3:03 AM
>
>
> On 10/12/2016 9:29 PM, Alex Williamson wrote:
> > On Wed, 12 Oct 2016 20:43:48 +0530
> > Kirti Wankhede wrote:
> >
> >> On 10/12/2016 7:22 AM, Tian, Kevin wrote:
> From: Kirti Wankhede [mai
From: Li Qiang
Currently, 9pfs sets the fs.xattr.copied_len field in V9fsFidState
to -1 to indicate a xattr walk fid. As the fs.xattr.copied_len is also
used to account for copied bytes, this may cause confusion. This patch
add a bool variable to represent the xattr walk fid.
Signed-off-by: Li Q
From: Li Qiang
In 9pfs xattr read/write function, it mix to use unsigned/signed
,32/64 bits integers. This will causes oob read/write issues. This patch
fix this.
Signed-off-by: Li Qiang
---
hw/9pfs/9p.c | 34 +-
hw/9pfs/9p.h | 4 ++--
2 files changed, 15 inser
log_max have no chance to be PCIE_AER_LOG_MAX_UNSET, unless user specify it.
Bonus:
1. remove unnecessary local variable.
2. fix a typo.
Signed-off-by: Cao jin
---
hw/pci/pcie_aer.c | 10 +-
include/hw/pci/pcie_aer.h | 2 +-
2 files changed, 2 insertions(+), 10 deletions(-)
di
From: Heiher
pandn FD, FS, FT
Operation: FD = ((NOT FS) AND FT)
Signed-off-by: Heiher
Signed-off-by: Fuxin Zhang
---
target-mips/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 55c2ca0..ed67180 100644
-
On 17/12/15 15:38, Aravinda Prasad wrote:
>
>
> On Thursday 17 December 2015 09:32 AM, David Gibson wrote:
>> On Wed, Dec 16, 2015 at 11:38:47AM +0530, Aravinda Prasad wrote:
>>> Introduce a new KVM capability to control how KVM
>>> behaves on machine check exception.
>>>
>>> Without this capabil
On October 12, 2016 9:46 PM, Anthony PERARD < anthony.per...@citrix.com > wrote:
>On Tue, Oct 04, 2016 at 09:43:43AM +0300, Emil Condrea wrote:
>> Prepare xen_be_del_xendev to be shared with frontends:
>> * xen_be_del_xendev -> xen_pv_del_xendev
>>
>> Signed-off-by: Emil Condrea
>
>Acked-by: Anth
On October 12, 2016 9:42 PM, Anthony PERARD < anthony.per...@citrix.com > wrote:
>On Tue, Oct 04, 2016 at 09:43:42AM +0300, Emil Condrea wrote:
>> Prepare xen_be_find_xendev to be shared with frontends:
>> * xen_be_find_xendev -> xen_pv_find_xendev
>>
>> Signed-off-by: Emil Condrea
>
>Acked-by: A
On October 12, 2016 9:41 PM, Anthony PERARD < anthony.per...@citrix.com > wrote:
>On Tue, Oct 04, 2016 at 09:43:41AM +0300, Emil Condrea wrote:
>> Prepare xen_be_evtchn_event to be shared with frontends:
>> * xen_be_evtchn_event -> xen_pv_evtchn_event
>>
>> Signed-off-by: Emil Condrea
>
>Acked-by
On October 12, 2016 9:41 PM, Anthony PERARD < anthony.per...@citrix.com > wrote:
>On Tue, Oct 04, 2016 at 09:43:40AM +0300, Emil Condrea wrote:
>> Prepare xen_be_send_notify to be shared with frontends:
>> * xen_be_send_notify -> xen_pv_send_notify
>>
>> Signed-off-by: Emil Condrea
>
>Acked-by: A
On October 12, 2016 9:37 PM, Anthony PERARD < anthony.per...@citrix.com > wrote:
>On Tue, Oct 04, 2016 at 09:43:39AM +0300, Emil Condrea wrote:
>> Prepare xen_be_unbind_evtchn to be shared with frontends:
>> * xen_be_unbind_evtchn -> xen_pv_unbind_evtchn
>>
>> Signed-off-by: Emil Condrea
>
>Acked
On 2016/10/12 22:21, Dr. David Alan Gilbert wrote:
* Stefan Hajnoczi (stefa...@gmail.com) wrote:
John and I recently discussed asynchronous savevm and I wanted to post
the ideas so they aren't forgotten. (We're not actively working on this
feature.)
Asynchronous savevm has the same effect as t
As context to everyone else as to why I'm going down the rabbit hole of
trying to remove external references to AioContext at all, see
https://lists.gnu.org/archive/html/qemu-devel/2016-10/msg00795.html
On 10/07/2016 03:49 AM, Paolo Bonzini wrote:
On 06/10/2016 22:22, John Snow wrote:
Calls
On real hardware, and under pHyp, the PCI host bridges on Power machines
typically advertise two outbound MMIO windows from the guest's physical
memory space to PCI memory space:
- A 32-bit window which maps onto 2GiB..4GiB in the PCI address space
- A 64-bit window which maps onto a large regi
Currently, the MMIO space for accessing PCI on pseries guests begins at
1 TiB in guest address space. Each PCI host bridge (PHB) has a 64 GiB
chunk of address space in which it places its outbound PIO and 32-bit and
64-bit MMIO windows.
This scheme as several problems:
- It limits guest RAM to
The libqos code for accessing PCI on the spapr machine type uses IOBASE()
and MMIOBASE() macros to determine the address in the CPU memory map of
the windows to PCI address space.
This is a detail of the implementation of PCI in the machine type, it's not
specified by the PAPR standard. Real gues
The 'spapr-pci-host-bridge' represents the virtual PCI host bridge (PHB)
for a PAPR guest. Unlike on x86, it's routine on Power (both bare metal
and PAPR guests) to have numerous independent PHBs, each controlling a
separate PCI domain.
There are two ways of configuring the spapr-pci-host-bridge
Currently the functions in pci-spapr.c (like pci-pc.c on which it's based)
don't distinguish between 32-bit and 64-bit PCI MMIO. At the moment, the
qemu side implementation is a bit weird and has a single MMIO window
straddling 32-bit and 64-bit regions, but we're likely to change that in
future.
In pci-spapr.c (as in pci-pc.c from which it was derived), the
pci_hole_start/pci_hole_size and pci_iohole_start/pci_iohole_size pairs[1]
essentially define the region of PCI (not CPU) addresses in which MMIO
or PIO BARs respectively will be allocated.
The size value is relative to the start value
Currently the default PCI host bridge for the 'pseries' machine type is
constructed with its IO windows in the 1TiB..(1TiB + 64GiB) range in
guest memory space. This means that if > 1TiB of guest RAM is specified,
the RAM will collide with the PCI IO windows, causing serious problems.
Problems wo
The current way we organize the IO windows into PCI space for the
pseries machine type has several problems.
- It makes it difficult to create very large MMIO spaces which is
necessary for certain PCI devices with very large BARs. This
problem has been known for a while.
- More recen
On Wed, Oct 12, 2016 at 02:06:10PM +0200, Laurent Vivier wrote:
>
>
> On 12/10/2016 12:55, David Gibson wrote:
> > On Wed, Oct 12, 2016 at 12:07:50PM +0200, Laurent Vivier wrote:
> >>
> >>
> >> On 12/10/2016 06:44, David Gibson wrote:
> >>> Currently the default PCI host bridge for the 'pseries'
On Wed, Oct 12, 2016 at 11:26:05AM +0200, Laurent Vivier wrote:
>
>
> On 12/10/2016 06:44, David Gibson wrote:
> > The 'spapr-pci-host-bridge' represents the virtual PCI host bridge (PHB)
> > for a PAPR guest. Unlike on x86, it's routine on Power (both bare metal
> > and PAPR guests) to have num
On Tue, Oct 11, 2016 at 02:01:19PM -0700,
no-re...@ec2-52-6-146-230.compute-1.amazonaws.com wrote:
[...]
> GTESTER tests/check-qom-proplist
> Found prop 'bv'
> **
> ERROR:/tmp/qemu-test/src/tests/check-qom-proplist.c:521:test_dummy_class_iterator:
> code should not be reached
> GTester: last ra
In some cases, ibm,client-architecture-support calls can fail. This
could happen in the current code for situations where the modified
device tree segment exceeds the buffer size provided by the guest
via the call parameters. In these cases, QEMU will reset, allowing
an opportunity to regenerate th
This adds machine options of the form:
-machine pseries,legacy-hotplug-events=true
-machine pseries,legacy-hotplug-events=false
to denote whether or not we wish to force the use of "legacy" style
hotplug events, which are surfaced through EPOW interrupts instead of
a dedicated interrupt sourc
From: Bharata B Rao
Add support for DRC count indexed hotplug ID type which is primarily
needed for memory hot unplug. This type allows for specifying the
number of DRs that should be plugged/unplugged starting from a given
DRC index.
Signed-off-by: Bharata B Rao
* updated rtas_event_log_v6_hp
Hotplug events were previously delivered using an EPOW interrupt
and were queued by linux guests into a circular buffer. For traditional
EPOW events like shutdown/resets, this isn't an issue, but for hotplug
events there are cases where this buffer can be exhausted, resulting
in the loss of hotplug
This updates the existing documentation to reflect recent updates to
the hotplug event structure, which are in draft form but slated
for inclusion in PAPR/LoPAPR.
Signed-off-by: Michael Roth
---
docs/specs/ppc-spapr-hotplug.txt | 55 +---
1 file changed, 46 in
Rather than machine instances having backward-compatible option
defaults that need to be repeatedly re-enabled for every new machine
type we introduce, we set the defaults appropriate for newer machine
types, then add code to explicitly disable instance options as needed
to maintain compatibility w
ibm,architecture-vec-5 is supposed to encode all option vector 5 bits
negotiated between platform/guest. Currently we hardcode this property
in the boot-time device tree to advertise a single negotiated
capability, "Form 1" NUMA Affinity, regardless of whether or not CAS
has been invoked or that ca
PAPR guests advertise their capabilities to the platform by passing
an ibm,architecture-vec structure via an
ibm,client-architecture-support hcall as described by LoPAPR v11,
B.6.2.3. during early boot.
Using this information, the platform enables the capabilities it
supports, then encodes a subse
Currently we access individual bytes of an option vector via
ldub_phys() to test for the presence of a particular capability
within that byte. Currently this is only done for the "dynamic
reconfiguration memory" capability bit. If that bit is present,
we pass a boolean value to spapr_h_cas_compose_
Commit 0a417869:
spapr: Move memory hotplug to RTAS_LOG_V6_HP_ID_DRC_COUNT type
dropped per-DRC/per-LMB hotplugs event in favor of a bulk add via a
single LMB count value. This was to avoid overrunning the guest EPOW
event queue with hotplug events. This works fine, but relies on the
guest ex
From: Bharata B Rao
Add support to hot remove pc-dimm memory devices.
Signed-off-by: Bharata B Rao
* add hooks to CAS/cmdline enablement of hotplug ACR support
Signed-off-by: Michael Roth
---
hw/ppc/spapr.c | 106 -
hw/ppc/spapr_drc.c |
This series is based on David's ppc-for-2.8 branch, and is also available from:
https://github.com/mdroth/qemu/commits/spapr-hotplug-event-update
Patches 1-4 address various deficiencies in how we currently handle option
vectors via ibm,client-architecture-support. This is done here in preparat
On Mon, Oct 10, 2016 at 15:59:02 +0200, Paolo Bonzini wrote:
> See each patch. My attempt at fixing whatever I did when I obviously
> didn't know enough^W about the C11 memory model, and at setting a
> better example for future generations...
Just for context. Building on this patchset, is it now
The lm32 target already has a disassembler which logs the assembly
instructions with "-d in_asm". Therefore, turn of the LOG_DIS() macro to
prevent logging the assembly instructions twice. Also turn the macro in a
one which is always compiled to catch any errors while the macro is turned
off.
Sign
On 10/12/2016 03:49 PM, Max Reitz wrote:
> Signed-off-by: Max Reitz
> ---
> tests/qemu-iotests/162 | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/tests/qemu-iotests/162 b/tests/qemu-iotests/162
> index f8eecb3..cad2bd7 100755
> --- a/tests/qemu-iotests/162
> +++ b/tests/qemu-iotests
Drop the rX, rY and rZ stuff and use dc->r{0,1,2} directly. This should
also fix the false positive in coverity CID 1005720.
Signed-off-by: Michael Walle
---
target-lm32/translate.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/target-lm32/translate.c b/target-lm32/t
On 10/12/2016 03:49 PM, Max Reitz wrote:
> Some block drivers may not be loaded yet, but qemu supports them
> nonetheless. bdrv_iterate_format() should report them, too.
>
> Signed-off-by: Max Reitz
> ---
> block.c | 18 ++
> 1 file changed, 18 insertions(+)
>
Reviewed-by: Eric
Don't truncate the multiplication and do a 64 bit one instead because
because the result is stored in a 64 bit variable.
Spotted by coverity, CID 1167561.
Signed-off-by: Michael Walle
---
hw/display/milkymist-tmu2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/display/
Be consistent with the reference manual.
Signed-off-by: Michael Walle
---
target-lm32/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index dc64cc6..fa8416a 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/tr
Hi,
Your series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Message-id: 20161012204907.25941-1-mre...@redhat.com
Subject: [Qemu-devel] [PATCH 0/3] iotests: Skip 162 if there is no SSH su
It's a bare metal program so I don't really have anywhere to print to,
other than my custom function to output to the uart. I did double check all
the address to make sure they agreed with the documentation and the Qemu
source code. I tried changing around the destinations of the output just to
ver
On Wed, Oct 12, 2016 at 10:58:43 +0200, Stefan Hajnoczi wrote:
> Hi Pranith,
> I was curious about the status of your MTTCG GSoC work:
>
> I saw your fence series which implements the noop memory barrier/fence
> instructions on various architectures, but I wasn't sure if that also
> covers the cas
Dear Sir/Ma'am
I want to ‘annotate’ the translation buffers - (adding a mechanism in the
translation buffers where we can store how many times they were executed,
and, for each one, add some ‘amount’ could be power, could be anything). I
need held to understand the translation buffer code in qemu,
On Thu, 13 Oct 2016 00:32:48 +0530
Kirti Wankhede wrote:
> On 10/12/2016 9:29 PM, Alex Williamson wrote:
> > On Wed, 12 Oct 2016 20:43:48 +0530
> > Kirti Wankhede wrote:
> >
> >> On 10/12/2016 7:22 AM, Tian, Kevin wrote:
> From: Kirti Wankhede [mailto:kwankh...@nvidia.com]
> Sent:
On 10/12/2016 03:49 PM, Max Reitz wrote:
> bdrv_iterate_format() did not actually sort the formats by name but by
> "pointer interpreted as string". That is probably not what we intended
> to do, so fix it (by changing qsort_strcmp() so it matches the example
> from qsort()'s manual page).
>
> Sig
Peter,
Greetings from DigitalOcean. We're experiencing the same symptoms
without this patch.
We have, collectively, many gigabytes of un-planned-for RSS being used
per-hypervisor
that we would like to get rid of =).
Without explicitly trying this patch (will do that ASAP), we immediately
not
On 10/12/2016 10:47 AM, Vladimir Sementsov-Ogievskiy wrote:
> HI all!
>
> My questions is: what are general recommendations in Qemu for return
> code, if we have Error **errp?
> What should I prefer: errp, duplicated by int return code, or void
> functions with errp?
Markus has already had severa
On 10/12/2016 08:23 AM, Greg Kurz wrote:
>
> But in fact, I'm afraid we have a more serious problem here... size
> comes from the guest and could cause g_malloc() to abort if QEMU has
> reached some RLIMIT... we need to call g_try_malloc0() and return
> ENOMEM if the allocation fails.
Even if it
bdrv_iterate_format() did not actually sort the formats by name but by
"pointer interpreted as string". That is probably not what we intended
to do, so fix it (by changing qsort_strcmp() so it matches the example
from qsort()'s manual page).
Signed-off-by: Max Reitz
---
block.c | 2 +-
1 file ch
Signed-off-by: Max Reitz
---
tests/qemu-iotests/162 | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/qemu-iotests/162 b/tests/qemu-iotests/162
index f8eecb3..cad2bd7 100755
--- a/tests/qemu-iotests/162
+++ b/tests/qemu-iotests/162
@@ -35,6 +35,9 @@ status=1 # failure is the defau
As reported by Hao QingFeng, iotest 162 is currently executed even if
qemu does not have any SSH support (which makes it fail, naturally).
Fixing that is not so trivial, because qemu-img currently does not
report modules, and SSH can be compiled as a module, so that needs to be
fixed first. While
Some block drivers may not be loaded yet, but qemu supports them
nonetheless. bdrv_iterate_format() should report them, too.
Signed-off-by: Max Reitz
---
block.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/block.c b/block.c
index e46e4b2..88a1ea5 100644
--- a/block.c
Hi
On Wed, Oct 12, 2016 at 11:15 PM Dr. David Alan Gilbert
wrote:
> Hi,
> I had a look at a couple of readline like libraries;
> editline and linenoise. A difficulty with using them is that
> they both want fd's or FILE*'s; editline takes either but
> from a brief look I think it's expecting
3 cases in a switch in disas_exc() require reference to the
ARM ARM spec in order to determine what case they're handling.
Signed-off-by: Thomas Hanson
---
target-arm/translate-a64.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm
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