[Qemu-devel] [PULL 3/4] hw/ppc/spapr: Fix the selection of the processor features

From: Thomas Huth The current code uses pa_features_206 for POWERPC_MMU_2_06, and for everything else, it uses pa_features_207. This is bad in some cases because there is also a "degraded" MMU version of ISA 2.06, called POWERPC_MMU_2_06a, which should of course use the flags

[Qemu-devel] [PULL 1/4] linux-headers: update

From: Cornelia Huck Update headers against 4.8-rc2. Signed-off-by: Cornelia Huck --- include/standard-headers/linux/input-event-codes.h | 32 include/standard-headers/linux/input.h | 1 +

Re: [Qemu-devel] [PATCH v4 03/20] ppc/pnv: add a core mask to PnvChip

On Wed, Oct 12, 2016 at 10:53:12AM +0200, Cédric Le Goater wrote: > On 10/11/2016 12:24 PM, David Gibson wrote: > > On Mon, Oct 10, 2016 at 02:56:25PM +0200, Cédric Le Goater wrote: > >> > @@ -227,11 +227,44 @@ static void ppc_powernv_init(MachineState *machine) >

[Qemu-devel] [PULL 4/4] ppc: Check the availability of transactional memory

From: Thomas Huth KVM-PR currently does not support transactional memory, and the implementation in TCG is just a fake. We should not announce TM support in the ibm,pa-features property when running on such a system, so disable it by default and only enable it if the KVM

Re: [Qemu-devel] [Qemu-block] [PATCH v4 0/3] iotests: Fix test 162

在 2016-10-13 3:46, Max Reitz 写道: On 12.10.2016 10:55, Hao QingFeng wrote: Max, Just a common question for this case, if sshx block driver wasn't built into qemu-img, this case would fail as below: Good point, and thanks for bringing it up, but it's not directly linked to this series other

Re: [Qemu-devel] [PATCH v4 08/20] ppc/pnv: add a LPC controller

On Mon, Oct 03, 2016 at 09:24:44AM +0200, Cédric Le Goater wrote: > From: Benjamin Herrenschmidt > > The LPC (Low Pin Count) interface on a POWER8 is made accessible to > the system through the ADU (XSCOM interface). This interface is part > of set of units connected

[Qemu-devel] [PULL 0/4] ppc patches for qemu-2.7 stable branch

The following changes since commit 1dc33ed90bf1fe1c2014dffa0d9e863c520d953a: Update version for v2.7.0 release (2016-09-02 13:44:11 +0100) are available in the git repository at: git://github.com/dgibson/qemu.git tags/ppc-for-2.7-20161013 for you to fetch changes up to

Re: [Qemu-devel] [PATCH v4 06/20] ppc/pnv: add XSCOM infrastructure

On Mon, Oct 03, 2016 at 09:24:42AM +0200, Cédric Le Goater wrote: > On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves > as a backbone to connect different units of the system. The host > firmware connects to the PIB through a bridge unit, the > Alter-Display-Unit (ADU), which

Re: [Qemu-devel] [PATCH v4 08/20] ppc/pnv: add a LPC controller

On Thu, Oct 13, 2016 at 01:52:55PM +1100, David Gibson wrote: > On Mon, Oct 03, 2016 at 09:24:44AM +0200, Cédric Le Goater wrote: > > From: Benjamin Herrenschmidt > > > > The LPC (Low Pin Count) interface on a POWER8 is made accessible to > > the system through the ADU

Re: [Qemu-devel] [PATCH v4 09/20] ppc/pnv: add a ISA bus

On Mon, Oct 03, 2016 at 09:24:45AM +0200, Cédric Le Goater wrote: > As Qemu only supports a single instance of the ISA bus, we use the LPC > controller of chip 0 to create one and plug in a couple of useful > devices, like an UART and RTC. An IPMI BT device, which is also an ISA > device, can be

[Qemu-devel] [PULL 2/4] hw/ppc/spapr: Move code related to "ibm, pa-features" to a separate function

From: Thomas Huth The function spapr_populate_cpu_dt() has become quite big already, and since we likely have to extend the pa-features property for every new processor generation, it is nicer if we put the related code into a separate function. Signed-off-by: Thomas Huth

Re: [Qemu-devel] [PATCH v1 3/3] target-ppc: implement xxbr[qdwh] instruction

On Wed, Oct 12, 2016 at 10:38:53AM +0530, Nikunj A Dadhania wrote: > Add required helpers (GEN_XX2FORM_EO) for supporting this instruction. > > xxbrh: VSX Vector Byte-Reverse Halfword > xxbrw: VSX Vector Byte-Reverse Word > xxbrd: VSX Vector Byte-Reverse Doubleword > xxbrq: VSX Vector

Re: [Qemu-devel] [PATCH v1 2/3] target-ppc: implement vnegw/d instructions

On Wed, Oct 12, 2016 at 10:38:52AM +0530, Nikunj A Dadhania wrote: > Vector Integer Negate Instructions: > > vnegw: Vector Negate Word > vnegd: Vector Negate Doubleword > > Signed-off-by: Nikunj A Dadhania > --- > target-ppc/helper.h | 2 ++ >

Re: [Qemu-devel] [PATCH v4 07/20] ppc/pnv: add XSCOM handlers to PnvCore

On Mon, Oct 03, 2016 at 09:24:43AM +0200, Cédric Le Goater wrote: > Now that we are using real HW ids for the cores in PowerNV chips, we > can route the XSCOM accesses to them. We just need to attach a > specific XSCOM memory region to each core in the appropriate window > for the core number. >

Re: [Qemu-devel] [PATCH v1 1/3] target-ppc: implement vexts[bh]2w and vexts[bhw]2d

On Wed, Oct 12, 2016 at 10:38:51AM +0530, Nikunj A Dadhania wrote: > Vector Extend Sign Instructions: > > vextsb2w: Vector Extend Sign Byte To Word > vextsh2w: Vector Extend Sign Halfword To Word > vextsb2d: Vector Extend Sign Byte To Doubleword > vextsh2d: Vector Extend Sign Halfword To

Re: [Qemu-devel] Async savevm using userfaultfd(2)

On Wed, Oct 12, 2016 at 4:04 PM, Stefan Hajnoczi wrote: > Perhaps this approach can be prototyped with mprotect and a SIGSEGV > handler if anyone wants to get async savevm going. I don't know if > there are any disadvantages to mprotecting guest RAM that the kvm kernel >

Re: [Qemu-devel] [PATCH 02/15] xen: Fix coding style warnings

On Tue, Oct 11, 2016 at 5:20 PM, Anthony PERARD wrote: > On Tue, Oct 04, 2016 at 09:43:31AM +0300, Emil Condrea wrote: >> Fixes: >> * WARNING: line over 80 characters >> >> Signed-off-by: Emil Condrea >> --- >> hw/block/xen_disk.c | 3

Re: [Qemu-devel] [PATCH 01/15] xen: Fix coding style errors

Actually I've split fixing coding style in 2 patches: one for errors and one for warnings. In this patch some resolve the error "code indent should never use tabs" but if on the same line there is a warning about line exceeding 80 characters, it will be fixed in "Fix coding style warnings" patch.

Re: [Qemu-devel] [PATCH 1/2] 9pfs: fix information leak in xattr read

Yes, I think the limit to apply to xattr size in 9pfs is the same as the Linux xattr size limit, I will try to find this limit. Thanks. On 2016-10-13 4:49 GMT+08:00 Eric Blake wrote: > On 10/12/2016 08:23 AM, Greg Kurz wrote: > > > > But in fact, I'm afraid we have a more

Re: [Qemu-devel] [PATCH v8 4/6] docs: Add Documentation for Mediated devices

> From: Kirti Wankhede [mailto:kwankh...@nvidia.com] > Sent: Thursday, October 13, 2016 3:03 AM > > > On 10/12/2016 9:29 PM, Alex Williamson wrote: > > On Wed, 12 Oct 2016 20:43:48 +0530 > > Kirti Wankhede wrote: > > > >> On 10/12/2016 7:22 AM, Tian, Kevin wrote: >

[Qemu-devel] [PATCH] 9pfs: add xattrwalk_fid field in V9fsFidState struct

From: Li Qiang Currently, 9pfs sets the fs.xattr.copied_len field in V9fsFidState to -1 to indicate a xattr walk fid. As the fs.xattr.copied_len is also used to account for copied bytes, this may cause confusion. This patch add a bool variable to represent the xattr walk fid.

[Qemu-devel] [PATCH v2] 9pfs: fix integer overflow issue in xattr read/write

From: Li Qiang In 9pfs xattr read/write function, it mix to use unsigned/signed ,32/64 bits integers. This will causes oob read/write issues. This patch fix this. Signed-off-by: Li Qiang --- hw/9pfs/9p.c | 34 +-

[Qemu-devel] [PATCH] pci_aer_init: cleanup

log_max have no chance to be PCIE_AER_LOG_MAX_UNSET, unless user specify it. Bonus: 1. remove unnecessary local variable. 2. fix a typo. Signed-off-by: Cao jin --- hw/pci/pcie_aer.c | 10 +- include/hw/pci/pcie_aer.h | 2 +- 2 files changed, 2

[Qemu-devel] [PATCH] target-mips: Fix Loongson pandn instruction.

From: Heiher pandn FD, FS, FT Operation: FD = ((NOT FS) AND FT) Signed-off-by: Heiher Signed-off-by: Fuxin Zhang --- target-mips/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target-mips/translate.c

Re: [Qemu-devel] [PATCH v2 4/4] spapr: Introduce FWNMI KVM capability

On 17/12/15 15:38, Aravinda Prasad wrote: > > > On Thursday 17 December 2015 09:32 AM, David Gibson wrote: >> On Wed, Dec 16, 2015 at 11:38:47AM +0530, Aravinda Prasad wrote: >>> Introduce a new KVM capability to control how KVM >>> behaves on machine check exception. >>> >>> Without this

Re: [Qemu-devel] [PATCH 14/15] xen: Rename xen_be_del_xendev

On October 12, 2016 9:46 PM, Anthony PERARD < anthony.per...@citrix.com > wrote: >On Tue, Oct 04, 2016 at 09:43:43AM +0300, Emil Condrea wrote: >> Prepare xen_be_del_xendev to be shared with frontends: >> * xen_be_del_xendev -> xen_pv_del_xendev >> >> Signed-off-by: Emil Condrea

Re: [Qemu-devel] [PATCH 13/15] xen: Rename xen_be_find_xendev

On October 12, 2016 9:42 PM, Anthony PERARD < anthony.per...@citrix.com > wrote: >On Tue, Oct 04, 2016 at 09:43:42AM +0300, Emil Condrea wrote: >> Prepare xen_be_find_xendev to be shared with frontends: >> * xen_be_find_xendev -> xen_pv_find_xendev >> >> Signed-off-by: Emil Condrea

Re: [Qemu-devel] [PATCH 12/15] xen: Rename xen_be_evtchn_event

On October 12, 2016 9:41 PM, Anthony PERARD < anthony.per...@citrix.com > wrote: >On Tue, Oct 04, 2016 at 09:43:41AM +0300, Emil Condrea wrote: >> Prepare xen_be_evtchn_event to be shared with frontends: >> * xen_be_evtchn_event -> xen_pv_evtchn_event >> >> Signed-off-by: Emil Condrea

Re: [Qemu-devel] [PATCH 11/15] xen: Rename xen_be_send_notify

On October 12, 2016 9:41 PM, Anthony PERARD < anthony.per...@citrix.com > wrote: >On Tue, Oct 04, 2016 at 09:43:40AM +0300, Emil Condrea wrote: >> Prepare xen_be_send_notify to be shared with frontends: >> * xen_be_send_notify -> xen_pv_send_notify >> >> Signed-off-by: Emil Condrea

Re: [Qemu-devel] [PATCH 10/15] xen: Rename xen_be_unbind_evtchn

On October 12, 2016 9:37 PM, Anthony PERARD < anthony.per...@citrix.com > wrote: >On Tue, Oct 04, 2016 at 09:43:39AM +0300, Emil Condrea wrote: >> Prepare xen_be_unbind_evtchn to be shared with frontends: >> * xen_be_unbind_evtchn -> xen_pv_unbind_evtchn >> >> Signed-off-by: Emil Condrea

Re: [Qemu-devel] Async savevm using userfaultfd(2)

On 2016/10/12 22:21, Dr. David Alan Gilbert wrote: * Stefan Hajnoczi (stefa...@gmail.com) wrote: John and I recently discussed asynchronous savevm and I wanted to post the ideas so they aren't forgotten. (We're not actively working on this feature.) Asynchronous savevm has the same effect as

Re: [Qemu-devel] [PATCH v2 04/11] blockjobs: Always use block_job_get_aio_context

As context to everyone else as to why I'm going down the rabbit hole of trying to remove external references to AioContext at all, see https://lists.gnu.org/archive/html/qemu-devel/2016-10/msg00795.html On 10/07/2016 03:49 AM, Paolo Bonzini wrote: On 06/10/2016 22:22, John Snow wrote:

[Qemu-devel] [PATCHv3 6/7] spapr_pci: Add a 64-bit MMIO window

On real hardware, and under pHyp, the PCI host bridges on Power machines typically advertise two outbound MMIO windows from the guest's physical memory space to PCI memory space: - A 32-bit window which maps onto 2GiB..4GiB in the PCI address space - A 64-bit window which maps onto a large

[Qemu-devel] [PATCHv3 7/7] spapr: Improved placement of PCI host bridges in guest memory map

Currently, the MMIO space for accessing PCI on pseries guests begins at 1 TiB in guest address space. Each PCI host bridge (PHB) has a 64 GiB chunk of address space in which it places its outbound PIO and 32-bit and 64-bit MMIO windows. This scheme as several problems: - It limits guest RAM to

[Qemu-devel] [PATCHv3 1/7] libqos: Isolate knowledge of spapr memory map to qpci_init_spapr()

The libqos code for accessing PCI on the spapr machine type uses IOBASE() and MMIOBASE() macros to determine the address in the CPU memory map of the windows to PCI address space. This is a detail of the implementation of PCI in the machine type, it's not specified by the PAPR standard. Real

[Qemu-devel] [PATCHv3 4/7] spapr_pci: Delegate placement of PCI host bridges to machine type

The 'spapr-pci-host-bridge' represents the virtual PCI host bridge (PHB) for a PAPR guest. Unlike on x86, it's routine on Power (both bare metal and PAPR guests) to have numerous independent PHBs, each controlling a separate PCI domain. There are two ways of configuring the spapr-pci-host-bridge

[Qemu-devel] [PATCHv3 3/7] libqos: Limit spapr-pci to 32-bit MMIO for now

Currently the functions in pci-spapr.c (like pci-pc.c on which it's based) don't distinguish between 32-bit and 64-bit PCI MMIO. At the moment, the qemu side implementation is a bit weird and has a single MMIO window straddling 32-bit and 64-bit regions, but we're likely to change that in future.

[Qemu-devel] [PATCHv3 2/7] libqos: Correct error in PCI hole sizing for spapr

In pci-spapr.c (as in pci-pc.c from which it was derived), the pci_hole_start/pci_hole_size and pci_iohole_start/pci_iohole_size pairs[1] essentially define the region of PCI (not CPU) addresses in which MMIO or PIO BARs respectively will be allocated. The size value is relative to the start

[Qemu-devel] [PATCHv3 5/7] spapr: Adjust placement of PCI host bridge to allow > 1TiB RAM

Currently the default PCI host bridge for the 'pseries' machine type is constructed with its IO windows in the 1TiB..(1TiB + 64GiB) range in guest memory space. This means that if > 1TiB of guest RAM is specified, the RAM will collide with the PCI IO windows, causing serious problems. Problems

[Qemu-devel] [PATCHv3 0/7] Improve PCI IO window orgnaization for pseries

The current way we organize the IO windows into PCI space for the pseries machine type has several problems. - It makes it difficult to create very large MMIO spaces which is necessary for certain PCI devices with very large BARs. This problem has been known for a while. - More

Re: [Qemu-devel] [PATCHv2 5/7] spapr: Adjust placement of PCI host bridge to allow > 1TiB RAM

On Wed, Oct 12, 2016 at 02:06:10PM +0200, Laurent Vivier wrote: > > > On 12/10/2016 12:55, David Gibson wrote: > > On Wed, Oct 12, 2016 at 12:07:50PM +0200, Laurent Vivier wrote: > >> > >> > >> On 12/10/2016 06:44, David Gibson wrote: > >>> Currently the default PCI host bridge for the 'pseries'

Re: [Qemu-devel] [PATCHv2 4/7] spapr_pci: Delegate placement of PCI host bridges to machine type

On Wed, Oct 12, 2016 at 11:26:05AM +0200, Laurent Vivier wrote: > > > On 12/10/2016 06:44, David Gibson wrote: > > The 'spapr-pci-host-bridge' represents the virtual PCI host bridge (PHB) > > for a PAPR guest. Unlike on x86, it's routine on Power (both bare metal > > and PAPR guests) to have

Re: [Qemu-devel] [PATCH 0/6] qdev class properties + abstract class support on device-list-properties

On Tue, Oct 11, 2016 at 02:01:19PM -0700, no-re...@ec2-52-6-146-230.compute-1.amazonaws.com wrote: [...] > GTESTER tests/check-qom-proplist > Found prop 'bv' > ** > ERROR:/tmp/qemu-test/src/tests/check-qom-proplist.c:521:test_dummy_class_iterator: > code should not be reached > GTester: last

[Qemu-devel] [PATCH 03/11] spapr: add option vector handling in CAS-generated resets

In some cases, ibm,client-architecture-support calls can fail. This could happen in the current code for situations where the modified device tree segment exceeds the buffer size provided by the guest via the call parameters. In these cases, QEMU will reset, allowing an opportunity to regenerate

[Qemu-devel] [PATCH 07/11] spapr: add hotplug interrupt machine options

This adds machine options of the form: -machine pseries,legacy-hotplug-events=true -machine pseries,legacy-hotplug-events=false to denote whether or not we wish to force the use of "legacy" style hotplug events, which are surfaced through EPOW interrupts instead of a dedicated interrupt

[Qemu-devel] [PATCH 09/11] spapr: Add DRC count indexed hotplug identifier type

From: Bharata B Rao Add support for DRC count indexed hotplug ID type which is primarily needed for memory hot unplug. This type allows for specifying the number of DRs that should be plugged/unplugged starting from a given DRC index. Signed-off-by: Bharata B Rao

[Qemu-devel] [PATCH 08/11] spapr_events: add support for dedicated hotplug event source

Hotplug events were previously delivered using an EPOW interrupt and were queued by linux guests into a circular buffer. For traditional EPOW events like shutdown/resets, this isn't an issue, but for hotplug events there are cases where this buffer can be exhausted, resulting in the loss of

[Qemu-devel] [PATCH 06/11] spapr: update spapr hotplug documentation

This updates the existing documentation to reflect recent updates to the hotplug event structure, which are in draft form but slated for inclusion in PAPR/LoPAPR. Signed-off-by: Michael Roth --- docs/specs/ppc-spapr-hotplug.txt | 55

[Qemu-devel] [PATCH 05/11] spapr: fix inheritance chain for default machine options

Rather than machine instances having backward-compatible option defaults that need to be repeatedly re-enabled for every new machine type we introduce, we set the defaults appropriate for newer machine types, then add code to explicitly disable instance options as needed to maintain compatibility

[Qemu-devel] [PATCH 04/11] spapr: improve ibm, architecture-vec-5 property handling

ibm,architecture-vec-5 is supposed to encode all option vector 5 bits negotiated between platform/guest. Currently we hardcode this property in the boot-time device tree to advertise a single negotiated capability, "Form 1" NUMA Affinity, regardless of whether or not CAS has been invoked or that

[Qemu-devel] [PATCH 01/11] spapr_ovec: initial implementation of option vector helpers

PAPR guests advertise their capabilities to the platform by passing an ibm,architecture-vec structure via an ibm,client-architecture-support hcall as described by LoPAPR v11, B.6.2.3. during early boot. Using this information, the platform enables the capabilities it supports, then encodes a

[Qemu-devel] [PATCH 02/11] spapr_hcall: use spapr_ovec_* interfaces for CAS options

Currently we access individual bytes of an option vector via ldub_phys() to test for the presence of a particular capability within that byte. Currently this is only done for the "dynamic reconfiguration memory" capability bit. If that bit is present, we pass a boolean value to

[Qemu-devel] [PATCH 10/11] spapr: use count+index for memory hotplug

Commit 0a417869: spapr: Move memory hotplug to RTAS_LOG_V6_HP_ID_DRC_COUNT type dropped per-DRC/per-LMB hotplugs event in favor of a bulk add via a single LMB count value. This was to avoid overrunning the guest EPOW event queue with hotplug events. This works fine, but relies on the guest

[Qemu-devel] [PATCH 11/11] spapr: Memory hot-unplug support

From: Bharata B Rao Add support to hot remove pc-dimm memory devices. Signed-off-by: Bharata B Rao * add hooks to CAS/cmdline enablement of hotplug ACR support Signed-off-by: Michael Roth --- hw/ppc/spapr.c

[Qemu-devel] [RFC PATCH 00/11] spapr: option vector re-work and memory unplug support

This series is based on David's ppc-for-2.8 branch, and is also available from: https://github.com/mdroth/qemu/commits/spapr-hotplug-event-update Patches 1-4 address various deficiencies in how we currently handle option vectors via ibm,client-architecture-support. This is done here in

Re: [Qemu-devel] [PATCH 0/5] More thread sanitizer fixes and atomic.h improvements

On Mon, Oct 10, 2016 at 15:59:02 +0200, Paolo Bonzini wrote: > See each patch. My attempt at fixing whatever I did when I obviously > didn't know enough^W about the C11 memory model, and at setting a > better example for future generations... Just for context. Building on this patchset, is it

Re: [Qemu-devel] [PATCH 3/3] iotests: Skip test 162 if there is no SSH support

On 10/12/2016 03:49 PM, Max Reitz wrote: > Signed-off-by: Max Reitz > --- > tests/qemu-iotests/162 | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/tests/qemu-iotests/162 b/tests/qemu-iotests/162 > index f8eecb3..cad2bd7 100755 > --- a/tests/qemu-iotests/162 > +++

[Qemu-devel] [PATCH 2/4] target-lm32: disable asm logging via LOG_DIS()

The lm32 target already has a disassembler which logs the assembly instructions with "-d in_asm". Therefore, turn of the LOG_DIS() macro to prevent logging the assembly instructions twice. Also turn the macro in a one which is always compiled to catch any errors while the macro is turned off.

[Qemu-devel] [PATCH 4/4] target-lm32: rewrite gen_compare()

Drop the rX, rY and rZ stuff and use dc->r{0,1,2} directly. This should also fix the false positive in coverity CID 1005720. Signed-off-by: Michael Walle --- target-lm32/translate.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git

Re: [Qemu-devel] [PATCH 2/3] block: Emit modules in bdrv_iterate_format()

On 10/12/2016 03:49 PM, Max Reitz wrote: > Some block drivers may not be loaded yet, but qemu supports them > nonetheless. bdrv_iterate_format() should report them, too. > > Signed-off-by: Max Reitz > --- > block.c | 18 ++ > 1 file changed, 18 insertions(+) >

[Qemu-devel] [PATCH 3/4] lm32: milkymist-tmu2: fix integer overflow

Don't truncate the multiplication and do a 64 bit one instead because because the result is stored in a 64 bit variable. Spotted by coverity, CID 1167561. Signed-off-by: Michael Walle --- hw/display/milkymist-tmu2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[Qemu-devel] [PATCH 1/4] target-lm32: swap operand of wcsr in LOG_DIS()

Be consistent with the reference manual. Signed-off-by: Michael Walle --- target-lm32/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-lm32/translate.c b/target-lm32/translate.c index dc64cc6..fa8416a 100644 --- a/target-lm32/translate.c

Re: [Qemu-devel] [PATCH 0/3] iotests: Skip 162 if there is no SSH support

Hi, Your series failed automatic build test. Please find the testing commands and their output below. If you have docker installed, you can probably reproduce it locally. Message-id: 20161012204907.25941-1-mre...@redhat.com Subject: [Qemu-devel] [PATCH 0/3] iotests: Skip 162 if there is no SSH

Re: [Qemu-devel] [Bug 1630723] [NEW] UART writes to netduino2/stm32f205-soc disappear

It's a bare metal program so I don't really have anywhere to print to, other than my custom function to output to the uart. I did double check all the address to make sure they agreed with the documentation and the Qemu source code. I tried changing around the destinations of the output just to

Re: [Qemu-devel] MTTCG memory ordering

On Wed, Oct 12, 2016 at 10:58:43 +0200, Stefan Hajnoczi wrote: > Hi Pranith, > I was curious about the status of your MTTCG GSoC work: > > I saw your fence series which implements the noop memory barrier/fence > instructions on various architectures, but I wasn't sure if that also > covers the

[Qemu-devel] (no subject)

Dear Sir/Ma'am I want to ‘annotate’ the translation buffers - (adding a mechanism in the translation buffers where we can store how many times they were executed, and, for each one, add some ‘amount’ could be power, could be anything). I need held to understand the translation buffer code in

Re: [Qemu-devel] [PATCH v8 4/6] docs: Add Documentation for Mediated devices

On Thu, 13 Oct 2016 00:32:48 +0530 Kirti Wankhede wrote: > On 10/12/2016 9:29 PM, Alex Williamson wrote: > > On Wed, 12 Oct 2016 20:43:48 +0530 > > Kirti Wankhede wrote: > > > >> On 10/12/2016 7:22 AM, Tian, Kevin wrote: > From: Kirti

Re: [Qemu-devel] [PATCH 1/3] block: Fix bdrv_iterate_format() sorting

On 10/12/2016 03:49 PM, Max Reitz wrote: > bdrv_iterate_format() did not actually sort the formats by name but by > "pointer interpreted as string". That is probably not what we intended > to do, so fix it (by changing qsort_strcmp() so it matches the example > from qsort()'s manual page). > >

Re: [Qemu-devel] [PATCH 00/15] optimize Qemu RSS usage

Peter, Greetings from DigitalOcean. We're experiencing the same symptoms without this patch. We have, collectively, many gigabytes of un-planned-for RSS being used per-hypervisor that we would like to get rid of =). Without explicitly trying this patch (will do that ASAP), we immediately

Re: [Qemu-devel] error reporting in functions

On 10/12/2016 10:47 AM, Vladimir Sementsov-Ogievskiy wrote: > HI all! > > My questions is: what are general recommendations in Qemu for return > code, if we have Error **errp? > What should I prefer: errp, duplicated by int return code, or void > functions with errp? Markus has already had

Re: [Qemu-devel] [PATCH 1/2] 9pfs: fix information leak in xattr read

On 10/12/2016 08:23 AM, Greg Kurz wrote: > > But in fact, I'm afraid we have a more serious problem here... size > comes from the guest and could cause g_malloc() to abort if QEMU has > reached some RLIMIT... we need to call g_try_malloc0() and return > ENOMEM if the allocation fails. Even if it

[Qemu-devel] [PATCH 1/3] block: Fix bdrv_iterate_format() sorting

bdrv_iterate_format() did not actually sort the formats by name but by "pointer interpreted as string". That is probably not what we intended to do, so fix it (by changing qsort_strcmp() so it matches the example from qsort()'s manual page). Signed-off-by: Max Reitz ---

[Qemu-devel] [PATCH 3/3] iotests: Skip test 162 if there is no SSH support

Signed-off-by: Max Reitz --- tests/qemu-iotests/162 | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/qemu-iotests/162 b/tests/qemu-iotests/162 index f8eecb3..cad2bd7 100755 --- a/tests/qemu-iotests/162 +++ b/tests/qemu-iotests/162 @@ -35,6 +35,9 @@ status=1 #

[Qemu-devel] [PATCH 0/3] iotests: Skip 162 if there is no SSH support

As reported by Hao QingFeng, iotest 162 is currently executed even if qemu does not have any SSH support (which makes it fail, naturally). Fixing that is not so trivial, because qemu-img currently does not report modules, and SSH can be compiled as a module, so that needs to be fixed first. While

[Qemu-devel] [PATCH 2/3] block: Emit modules in bdrv_iterate_format()

Some block drivers may not be loaded yet, but qemu supports them nonetheless. bdrv_iterate_format() should report them, too. Signed-off-by: Max Reitz --- block.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/block.c b/block.c index e46e4b2..88a1ea5

Re: [Qemu-devel] chardev's and fd's in monitors

Hi On Wed, Oct 12, 2016 at 11:15 PM Dr. David Alan Gilbert wrote: > Hi, > I had a look at a couple of readline like libraries; > editline and linenoise. A difficulty with using them is that > they both want fd's or FILE*'s; editline takes either but > from a brief look I

[Qemu-devel] [PATCH v3 4/4] target-arm: Comments added to identify cases in a switch

3 cases in a switch in disas_exc() require reference to the ARM ARM spec in order to determine what case they're handling. Signed-off-by: Thomas Hanson --- target-arm/translate-a64.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

Re: [Qemu-devel] [kvm-unit-tests PATCHv6 2/3] arm: pmu: Check cycle count increases

On 10/12/2016 01:10 PM, Christopher Covington wrote: > Hi Wei, > > On 10/12/2016 11:49 AM, Wei Huang wrote: >> On 10/11/2016 01:40 PM, Christopher Covington wrote: >>> Ensure that reads of the PMCCNTR_EL0 are monotonically increasing, >>> even for the smallest delta of two subsequent reads. >>>

[Qemu-devel] [PATCH v3 2/4] target-arm: Code changes to implement overwrite of tag field on PC load

For BR, BLR and RET instructions, if tagged addresses are enabled, the tag field in the address must be cleared out prior to loading the address into the PC. Depending on the current EL, it will be set to either all 0's or all 1's. Signed-off-by: Thomas Hanson ---

Re: [Qemu-devel] [PATCH 2/3] target-arm: Code changes to implement overwrite of tag field on PC load

On 10/11/2016 10:12 AM, Peter Maydell wrote: > On 11 October 2016 at 16:51, Thomas Hanson wrote: >> On 5 October 2016 at 16:01, Peter Maydell wrote: >>> It matches the style of the rest of the code which generally >>> prefers to convert

[Qemu-devel] [PATCH v3 3/4] target-arm: Comments to mark location of pending work for 56 bit addresses

Certain instructions which can not directly load a tagged address value may trigger a corner case when the address size is 56 bits. This is because incrementing or offsetting from the current PC can cause an arithetic roll-over into the tag bits. Per the ARM ARM spec, these cases should also be

[Qemu-devel] [PATCH v3 0/4] target-arm: Handle tagged addresses when loading PC

If tagged addresses are enabled, then addresses being loaded into the PC must be cleaned up by overwriting the tag bits with either all 0's or all 1's as specified in the ARM ARM spec. The decision process is dependent on whether the code will be running in EL0/1 or in EL2/3 and is controlled

[Qemu-devel] [PATCH v3 1/4] target-arm: Infrastucture changes to enable handling of tagged address loading into PC

When capturing the current CPU state for the TB, extract the TBI0 and TBI1 values from the correct TCR for the current EL and then add them to the TB flags field. Then, at the start of code generation for the block, copy the TBI fields into the DisasContext structure. Signed-off-by: Thomas

Re: [Qemu-devel] [Qemu-block] [PATCH v4 0/3] iotests: Fix test 162

On 12.10.2016 10:55, Hao QingFeng wrote: > Max, > > Just a common question for this case, if sshx block driver wasn't built > into qemu-img, this case would fail as below: Good point, and thanks for bringing it up, but it's not directly linked to this series other than by its subject, of course,

Re: [Qemu-devel] [PATCH v8 6/6] Add common functions for SET_IRQS and GET_REGION_INFO ioctls

On 10/12/2016 4:48 AM, Alex Williamson wrote: > On Tue, 11 Oct 2016 01:58:37 +0530 > Kirti Wankhede wrote: > >> Add common functions for SET_IRQS and to add capability buffer for >> GET_REGION_INFO ioctls > > Clearly should be two (or more) separate patches since

[Qemu-devel] chardev's and fd's in monitors

Hi, I had a look at a couple of readline like libraries; editline and linenoise. A difficulty with using them is that they both want fd's or FILE*'s; editline takes either but from a brief look I think it's expecting to extract the fd. That makes them tricky to integrate into qemu, where the

Re: [Qemu-devel] [PATCH v8 4/6] docs: Add Documentation for Mediated devices

On 10/12/2016 9:29 PM, Alex Williamson wrote: > On Wed, 12 Oct 2016 20:43:48 +0530 > Kirti Wankhede wrote: > >> On 10/12/2016 7:22 AM, Tian, Kevin wrote: From: Kirti Wankhede [mailto:kwankh...@nvidia.com] Sent: Wednesday, October 12, 2016 4:45 AM >> +*

[Qemu-devel] [PATCH] script/clean-includes: added duplicate #include check

Added script to check duplicate #include entries. This check will scan and print the files in which duplicate #include entries are present. Script might output false postive entries as well. Such entries should not be removed. So if it finds any duplicate entries script will terminate with an

Re: [Qemu-devel] [PATCH v1 2/2] gdbstub: Fix vCont behaviour

On Wed, Oct 12, 2016 at 03:55:18PM +0200, Claudio Imbrenda wrote: > On 12/10/16 15:15, David Hildenbrand wrote: > >>> +for (cx = 0; ccpus && ccpus[cx]; cx++) { > >>> +cpu_single_step(cpu, 0); > > > > This looks suspicious > > why? we set all cpus to single step, since

Re: [Qemu-devel] [PATCH 05/22] qcow2-bitmap: structs and consts

On 11.10.2016 13:50, Vladimir Sementsov-Ogievskiy wrote: > On 01.10.2016 17:34, Max Reitz wrote: >> On 30.09.2016 12:53, Vladimir Sementsov-Ogievskiy wrote: >>> Create block/qcow2-bitmap.c >>> Add data structures and constraints accordingly to docs/specs/qcow2.txt >>> >>> Signed-off-by: Vladimir

Re: [Qemu-devel] [PATCH 09/22] block: introduce persistent dirty bitmaps

On 12.10.2016 14:30, Vladimir Sementsov-Ogievskiy wrote: > On 12.10.2016 14:38, Vladimir Sementsov-Ogievskiy wrote: >> On 07.10.2016 22:28, Max Reitz wrote: >>> On 30.09.2016 12:53, Vladimir Sementsov-Ogievskiy wrote: New field BdrvDirtyBitmap.persistent means, that bitmap should be saved

Re: [Qemu-devel] [PATCH 09/22] block: introduce persistent dirty bitmaps

On 11.10.2016 15:11, Vladimir Sementsov-Ogievskiy wrote: > On 07.10.2016 20:54, Max Reitz wrote: >> On 30.09.2016 12:53, Vladimir Sementsov-Ogievskiy wrote: >>> New field BdrvDirtyBitmap.persistent means, that bitmap should be saved >>> on bdrv_close, using format driver. Format driver should

Re: [Qemu-devel] [PATCH 06/22] qcow2: add dirty bitmaps extension

On 11.10.2016 14:09, Vladimir Sementsov-Ogievskiy wrote: > On 01.10.2016 17:46, Max Reitz wrote: >> On 30.09.2016 12:53, Vladimir Sementsov-Ogievskiy wrote: >>> Add dirty bitmap extension as specified in docs/specs/qcow2.txt. >>> For now, just mirror extension header into Qcow2 state and check >>>

Re: [Qemu-devel] [PATCH] target-lm32: fix LOG_DIS operand order

On 12 October 2016 at 18:15, Michael Walle wrote: > The order of most opcodes with immediates was wrong (according to the > reference manual) in the (debug) logging. Additionally, one operand for the > andhi instruction was completly wrong. Fix these. > > Signed-off-by: Michael

Re: [Qemu-devel] [Qemu-block] [PATCH v14 11/21] qapi: add integer range support for QObjectInputVisitor

Kevin Wolf writes: > Am 12.10.2016 um 17:50 hat Markus Armbruster geschrieben: >> "Daniel P. Berrange" writes: >> >> > The traditional CLI arg syntax allows two ways to specify >> > integer lists, either one value per key, or a range of >> > values per

Re: [Qemu-devel] [PATCH] vfio: Fix vfio_rtl8168_quirk_data_read address offset

Am 10.10.2016 um 17:18 schrieb Alex Williamson: On Sun, 9 Oct 2016 19:56:03 +0200 Thorsten Kohfeldt wrote: From: Thorsten Kohfeldt Date: Sat, 24 Sep 2016 20:43:20 +0200 Subject: [PATCH] vfio: Fix vfio_rtl8168_quirk_data_read address

Re: [Qemu-devel] [kvm-unit-tests PATCHv6 2/3] arm: pmu: Check cycle count increases

Hi Wei, On 10/12/2016 11:49 AM, Wei Huang wrote: > On 10/11/2016 01:40 PM, Christopher Covington wrote: >> Ensure that reads of the PMCCNTR_EL0 are monotonically increasing, >> even for the smallest delta of two subsequent reads. >> >> Signed-off-by: Christopher Covington >>

[Qemu-devel] [PATCH v2 1/4] target-arm: Implement dummy MDCCINT_EL1

MDCCINT_EL1 is part of the DCC debugger communication channel between the CPU and an attached external debugger. QEMU doesn't implement this, but since Linux may try to access this register we need to provide at least a dummy implementation. Signed-off-by: Peter Maydell

[Qemu-devel] [PATCH v2 3/4] hw/intc/arm_gicv3: Fix ICC register tracepoints

Fix some problems with the tracepoints for ICC register reads and writes: * tracepoints for ICC_BPR, ICC_APR, ICC_IGRPEN, ICC_EIOR were not printing the that indicated whether the access was to the group 0 or 1 register * the ICC_IGREPEN1_EL3 read function was not actually calling the

[Qemu-devel] [PATCH v2 4/4] hw/char/pl011: Add trace events

Add some trace events for the pl011 UART model. Signed-off-by: Peter Maydell --- hw/char/pl011.c | 71 hw/char/trace-events | 9 +++ 2 files changed, 59 insertions(+), 21 deletions(-) diff --git

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