The condition '!A || (A && B)' is equivalent to '!A || B'
Buglink: https://bugs.launchpad.net/qemu/+bug/1464611
Signed-off-by: Thomas Huth
---
hw/tpm/tpm_passthrough.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/tpm/tpm_passthrough.c b/hw/tpm/tpm_passthrough.c
i
HI all!
My questions is: what are general recommendations in Qemu for return
code, if we have Error **errp?
What should I prefer: errp, duplicated by int return code, or void
functions with errp?
void + errp seems good, just to not duplicate things. But it has a
disadvantage of necessity of
On 10/11/2016 01:40 PM, Christopher Covington wrote:
> Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
> even for the smallest delta of two subsequent reads.
>
> Signed-off-by: Christopher Covington
> Reviewed-by: Andrew Jones
> ---
> arm/pmu.c | 60
"Daniel P. Berrange" writes:
> The traditional CLI arg syntax allows two ways to specify
> integer lists, either one value per key, or a range of
> values per key. eg the following are identical:
>
> -arg foo=5,foo=6,foo=7
> -arg foo=5-7
>
> This extends the QObjectInputVisitor so that it is
Am 11.10.2016 um 09:37 hat Ashijeet Acharya geschrieben:
> Add InetSocketAddress compatibility to SSH driver.
>
> Add a new option "server" to the SSH block driver which then accepts
> a InetSocketAddress.
>
> "host" and "port" are supported as legacy options and are mapped to
> their InetSocketA
On Wed, 12 Oct 2016 20:43:48 +0530
Kirti Wankhede wrote:
> On 10/12/2016 7:22 AM, Tian, Kevin wrote:
> >> From: Kirti Wankhede [mailto:kwankh...@nvidia.com]
> >> Sent: Wednesday, October 12, 2016 4:45 AM
> +* mdev_supported_types:
> +List of current supported mediated device types
Am 11.10.2016 um 09:37 hat Ashijeet Acharya geschrieben:
> This series adds blockdev-add support for SSH block driver.
>
> Patch 1 prepares the code for the addition of a new option prefix,
> which is "server.". This is accomplished by adding a
> ssh_has_filename_options_conflict() function which
Am 12.10.2016 um 17:50 hat Markus Armbruster geschrieben:
> "Daniel P. Berrange" writes:
>
> > The traditional CLI arg syntax allows two ways to specify
> > integer lists, either one value per key, or a range of
> > values per key. eg the following are identical:
> >
> > -arg foo=5,foo=6,foo=7
On 10/12/2016 07:26 AM, Vladimir Sementsov-Ogievskiy wrote:
it is almost a duplication of test_transaction_failure, I think it would
be better to make separate do_test_transaction_failure with parameter
and two wrappers
Yes, sorry -- I missed that for this iteration, but I'll act on it for
On 12 October 2016 at 16:33, Thomas Huth wrote:
> The condition '!A || (A && B)' is equivalent to '!A || B'
>
> Buglink: https://bugs.launchpad.net/qemu/+bug/1464611
> Signed-off-by: Thomas Huth
Reviewed-by: Peter Maydell
thanks
-- PMM
On 10/12/2016 06:22 AM, Kevin Wolf wrote:
Am 11.10.2016 um 17:47 hat John Snow geschrieben:
On 10/10/2016 03:23 PM, Mark Cave-Ayland wrote:
On 10/10/16 17:34, Eric Blake wrote:
On 10/09/2016 11:43 AM, Mark Cave-Ayland wrote:
The hard-coded default alignment is BDRV_SECTOR_SIZE, however thi
Richard Henderson writes:
> Add all of cmpxchg, op_fetch, fetch_op, and xchg.
> Handle both endian-ness, and sizes up to 8.
> Handle expanding non-atomically, when emulating in serial.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
> ---
> Makefile.objs | 2 +-
> Ma
Richard Henderson writes:
> Allow qemu to build on 32-bit hosts without 64-bit atomic ops.
>
> Even if we only allow 32-bit hosts to multi-thread emulate 32-bit
> guests, we still need some way to handle the 32-bit guest using a
> 64-bit atomic operation. Do so by dropping back to single-step.
On Wed, Oct 12, 2016 at 9:31 PM, Kevin Wolf wrote:
> Am 11.10.2016 um 09:37 hat Ashijeet Acharya geschrieben:
>> This series adds blockdev-add support for SSH block driver.
>>
>> Patch 1 prepares the code for the addition of a new option prefix,
>> which is "server.". This is accomplished by addin
Both branches of the ternary operator have the same expressions. Drop the
operator.
This fixes: https://bugs.launchpad.net/qemu/+bug/1414293
Signed-off-by: Michael Walle
---
target-lm32/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-lm32/translate.c b/tar
** Also affects: archlinux
Importance: Undecided
Status: New
** No longer affects: archlinux
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1541643
Title:
IA32_FEATURE_CONTROL MSR unset f
On 12.10.2016 18:23, Michael Walle wrote:
> Both branches of the ternary operator have the same expressions. Drop the
> operator.
>
> This fixes: https://bugs.launchpad.net/qemu/+bug/1414293
>
> Signed-off-by: Michael Walle
> ---
> target-lm32/translate.c | 2 +-
> 1 file changed, 1 insertion(+
On 12 October 2016 at 17:23, Michael Walle wrote:
> Both branches of the ternary operator have the same expressions. Drop the
> operator.
>
> This fixes: https://bugs.launchpad.net/qemu/+bug/1414293
>
> Signed-off-by: Michael Walle
> ---
> target-lm32/translate.c | 2 +-
> 1 file changed, 1 inse
Am 12.10.2016 um 18:20 hat Ashijeet Acharya geschrieben:
> On Wed, Oct 12, 2016 at 9:31 PM, Kevin Wolf wrote:
> > Am 11.10.2016 um 09:37 hat Ashijeet Acharya geschrieben:
> >> This series adds blockdev-add support for SSH block driver.
> >>
> >> Patch 1 prepares the code for the addition of a new
Am 2016-10-12 18:35, schrieb Peter Maydell:
but I noticed while doing the review that our LOG_DIS
is wrong for the compare-immediates:
LOG_DIS("cmpei r%d, r%d, %d\n", dc->r0, dc->r1,
sign_extend(dc->imm16, 16));
but the processor reference manual says cmpei's mnemonic
sh
On Wed, Oct 12, 2016 at 9:21 PM, Kevin Wolf wrote:
> Am 11.10.2016 um 09:37 hat Ashijeet Acharya geschrieben:
>> Add InetSocketAddress compatibility to SSH driver.
>>
>> Add a new option "server" to the SSH block driver which then accepts
>> a InetSocketAddress.
>>
>> "host" and "port" are support
On 12/10/2016 15:55, Claudio Imbrenda wrote:
>>> +for (cx = 0; ccpus && ccpus[cx]; cx++) {
>>> +cpu_single_step(cpu, 0);
>> >
>> > This looks suspicious
> why? we set all cpus to single step, since that is the default, and then
> we clear the single-step pro
On Wed, Oct 12, 2016 at 10:10 PM, Kevin Wolf wrote:
> Am 12.10.2016 um 18:20 hat Ashijeet Acharya geschrieben:
>> On Wed, Oct 12, 2016 at 9:31 PM, Kevin Wolf wrote:
>> > Am 11.10.2016 um 09:37 hat Ashijeet Acharya geschrieben:
>> >> This series adds blockdev-add support for SSH block driver.
>> >
Am 2016-10-12 18:35, schrieb Peter Maydell:
On 12 October 2016 at 17:23, Michael Walle wrote:
Both branches of the ternary operator have the same expressions. Drop
the
operator.
This fixes: https://bugs.launchpad.net/qemu/+bug/1414293
Signed-off-by: Michael Walle
---
target-lm32/translate.
On 12 October 2016 at 17:42, Michael Walle wrote:
> Am 2016-10-12 18:35, schrieb Peter Maydell:
>>
>> but I noticed while doing the review that our LOG_DIS
>> is wrong for the compare-immediates:
>>
>> LOG_DIS("cmpei r%d, r%d, %d\n", dc->r0, dc->r1,
>> sign_extend(dc->imm16
> On 21 Sep 2016, at 19:15, Eric Blake wrote:
>
> On 09/21/2016 10:27 AM, Felipe Franciosi wrote:
>> On GCC versions 3.4 and newer, simply using (void) in front of a
>> function that has been declared with WUR will no longer suppress a
>> compilation warning. This commit brings the ignore_value(
The order of most opcodes with immediates was wrong (according to the
reference manual) in the (debug) logging. Additionally, one operand for the
andhi instruction was completly wrong. Fix these.
Signed-off-by: Michael Walle
---
target-lm32/translate.c | 34 +-
1
On 12 October 2016 at 18:11, Michael Walle wrote:
> Am 2016-10-12 18:35, schrieb Peter Maydell:
>> but I noticed while doing the review that our LOG_DIS
>> is wrong for the compare-immediates:
>>
>> LOG_DIS("cmpei r%d, r%d, %d\n", dc->r0, dc->r1,
>> sign_extend(dc->imm16, 1
On 10/12/2016 05:07 AM, Paolo Bonzini wrote:
>
>
> On 12/10/2016 13:59, Halil Pasic wrote:
>> IMHO this would:
>> * allow us to keep the good old MVStateInfo objects unmodified and
>> the semantic of VMStateInfo unchanged
>> * make clear that VMStateLinked does not care about the calculated s
"Daniel P. Berrange" writes:
> If given an option string such as
>
> size=1024,nodes=10,nodes=4-5,nodes=1-2,policy=bind
>
> the qemu_opts_to_qdict() method will currently overwrite
> the values for repeated option keys, so only the last
> value is in the returned dict:
>
> size=QString("102
Add some useful trace events for the ARM generic timers (notably
the various register writes and the resulting IRQ line state).
Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
---
Makefile.objs | 1 +
target-arm/helper.c | 20
target-arm/trace-eve
This set of straightforward patches is a preliminary
for adding virtualization support to the GICv3 emulation:
* add a (nop implementation of) MDCCINT_EL1, since KVM
will read/write it on worldswitch
* fix some bugs in the GICv3 trace events
* add trace events for the generic timers
(which
Add some trace events for the pl011 UART model.
Signed-off-by: Peter Maydell
---
hw/char/pl011.c | 71
hw/char/trace-events | 9 +++
2 files changed, 59 insertions(+), 21 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
i
Fix some problems with the tracepoints for ICC register reads
and writes:
* tracepoints for ICC_BPR, ICC_APR, ICC_IGRPEN,
ICC_EIOR were not printing the that indicated whether
the access was to the group 0 or 1 register
* the ICC_IGREPEN1_EL3 read function was not actually calling
the a
MDCCINT_EL1 is part of the DCC debugger communication
channel between the CPU and an attached external debugger.
QEMU doesn't implement this, but since Linux may try
to access this register we need to provide at least
a dummy implementation.
Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Igle
Hi Wei,
On 10/12/2016 11:49 AM, Wei Huang wrote:
> On 10/11/2016 01:40 PM, Christopher Covington wrote:
>> Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
>> even for the smallest delta of two subsequent reads.
>>
>> Signed-off-by: Christopher Covington
>> Reviewed-by: Andrew J
Am 10.10.2016 um 17:18 schrieb Alex Williamson:
On Sun, 9 Oct 2016 19:56:03 +0200
Thorsten Kohfeldt wrote:
From: Thorsten Kohfeldt
Date: Sat, 24 Sep 2016 20:43:20 +0200
Subject: [PATCH] vfio: Fix vfio_rtl8168_quirk_data_read address offset
Introductory comment for rtl8168 VFIO MSI-X quirk s
Kevin Wolf writes:
> Am 12.10.2016 um 17:50 hat Markus Armbruster geschrieben:
>> "Daniel P. Berrange" writes:
>>
>> > The traditional CLI arg syntax allows two ways to specify
>> > integer lists, either one value per key, or a range of
>> > values per key. eg the following are identical:
>> >
On 12 October 2016 at 18:15, Michael Walle wrote:
> The order of most opcodes with immediates was wrong (according to the
> reference manual) in the (debug) logging. Additionally, one operand for the
> andhi instruction was completly wrong. Fix these.
>
> Signed-off-by: Michael Walle
Reviewed-by
On 11.10.2016 14:09, Vladimir Sementsov-Ogievskiy wrote:
> On 01.10.2016 17:46, Max Reitz wrote:
>> On 30.09.2016 12:53, Vladimir Sementsov-Ogievskiy wrote:
>>> Add dirty bitmap extension as specified in docs/specs/qcow2.txt.
>>> For now, just mirror extension header into Qcow2 state and check
>>>
On 11.10.2016 15:11, Vladimir Sementsov-Ogievskiy wrote:
> On 07.10.2016 20:54, Max Reitz wrote:
>> On 30.09.2016 12:53, Vladimir Sementsov-Ogievskiy wrote:
>>> New field BdrvDirtyBitmap.persistent means, that bitmap should be saved
>>> on bdrv_close, using format driver. Format driver should maint
On 12.10.2016 14:30, Vladimir Sementsov-Ogievskiy wrote:
> On 12.10.2016 14:38, Vladimir Sementsov-Ogievskiy wrote:
>> On 07.10.2016 22:28, Max Reitz wrote:
>>> On 30.09.2016 12:53, Vladimir Sementsov-Ogievskiy wrote:
New field BdrvDirtyBitmap.persistent means, that bitmap should be saved
On 11.10.2016 13:50, Vladimir Sementsov-Ogievskiy wrote:
> On 01.10.2016 17:34, Max Reitz wrote:
>> On 30.09.2016 12:53, Vladimir Sementsov-Ogievskiy wrote:
>>> Create block/qcow2-bitmap.c
>>> Add data structures and constraints accordingly to docs/specs/qcow2.txt
>>>
>>> Signed-off-by: Vladimir Se
On Wed, Oct 12, 2016 at 03:55:18PM +0200, Claudio Imbrenda wrote:
> On 12/10/16 15:15, David Hildenbrand wrote:
> >>> +for (cx = 0; ccpus && ccpus[cx]; cx++) {
> >>> +cpu_single_step(cpu, 0);
> >
> > This looks suspicious
>
> why? we set all cpus to single step, since
Added script to check duplicate #include entries. This check will scan and
print the files in which duplicate #include entries are present.
Script might output false postive entries as well. Such entries should
not be removed. So if it finds any duplicate entries script will terminate
with an exit
On 10/12/2016 9:29 PM, Alex Williamson wrote:
> On Wed, 12 Oct 2016 20:43:48 +0530
> Kirti Wankhede wrote:
>
>> On 10/12/2016 7:22 AM, Tian, Kevin wrote:
From: Kirti Wankhede [mailto:kwankh...@nvidia.com]
Sent: Wednesday, October 12, 2016 4:45 AM
>> +* mdev_supported_types:
Hi,
I had a look at a couple of readline like libraries;
editline and linenoise. A difficulty with using them is that
they both want fd's or FILE*'s; editline takes either but
from a brief look I think it's expecting to extract the fd.
That makes them tricky to integrate into qemu, where
the cha
On 10/12/2016 4:48 AM, Alex Williamson wrote:
> On Tue, 11 Oct 2016 01:58:37 +0530
> Kirti Wankhede wrote:
>
>> Add common functions for SET_IRQS and to add capability buffer for
>> GET_REGION_INFO ioctls
>
> Clearly should be two (or more) separate patches since SET_IRQS and
> REGION_INFO are
On 12.10.2016 10:55, Hao QingFeng wrote:
> Max,
>
> Just a common question for this case, if sshx block driver wasn't built
> into qemu-img, this case would fail as below:
Good point, and thanks for bringing it up, but it's not directly linked
to this series other than by its subject, of course,
If tagged addresses are enabled, then addresses being loaded into the
PC must be cleaned up by overwriting the tag bits with either all 0's
or all 1's as specified in the ARM ARM spec. The decision process is
dependent on whether the code will be running in EL0/1 or in EL2/3 and
is controlled
When capturing the current CPU state for the TB, extract the TBI0 and TBI1
values from the correct TCR for the current EL and then add them to the TB
flags field.
Then, at the start of code generation for the block, copy the TBI fields
into the DisasContext structure.
Signed-off-by: Thomas Hanson
Certain instructions which can not directly load a tagged address value
may trigger a corner case when the address size is 56 bits. This is
because incrementing or offsetting from the current PC can cause an
arithetic roll-over into the tag bits. Per the ARM ARM spec, these cases
should also be a
On 10/11/2016 10:12 AM, Peter Maydell wrote:
> On 11 October 2016 at 16:51, Thomas Hanson wrote:
>> On 5 October 2016 at 16:01, Peter Maydell wrote:
>>> It matches the style of the rest of the code which generally
>>> prefers to convert register numbers into TCGv earlier rather
>>> than later (at
For BR, BLR and RET instructions, if tagged addresses are enabled, the
tag field in the address must be cleared out prior to loading the
address into the PC. Depending on the current EL, it will be set to
either all 0's or all 1's.
Signed-off-by: Thomas Hanson
---
target-arm/translate-a64.c | 9
On 10/12/2016 01:10 PM, Christopher Covington wrote:
> Hi Wei,
>
> On 10/12/2016 11:49 AM, Wei Huang wrote:
>> On 10/11/2016 01:40 PM, Christopher Covington wrote:
>>> Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
>>> even for the smallest delta of two subsequent reads.
>>>
3 cases in a switch in disas_exc() require reference to the
ARM ARM spec in order to determine what case they're handling.
Signed-off-by: Thomas Hanson
---
target-arm/translate-a64.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm
Hi
On Wed, Oct 12, 2016 at 11:15 PM Dr. David Alan Gilbert
wrote:
> Hi,
> I had a look at a couple of readline like libraries;
> editline and linenoise. A difficulty with using them is that
> they both want fd's or FILE*'s; editline takes either but
> from a brief look I think it's expecting
Some block drivers may not be loaded yet, but qemu supports them
nonetheless. bdrv_iterate_format() should report them, too.
Signed-off-by: Max Reitz
---
block.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/block.c b/block.c
index e46e4b2..88a1ea5 100644
--- a/block.c
As reported by Hao QingFeng, iotest 162 is currently executed even if
qemu does not have any SSH support (which makes it fail, naturally).
Fixing that is not so trivial, because qemu-img currently does not
report modules, and SSH can be compiled as a module, so that needs to be
fixed first. While
Signed-off-by: Max Reitz
---
tests/qemu-iotests/162 | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/qemu-iotests/162 b/tests/qemu-iotests/162
index f8eecb3..cad2bd7 100755
--- a/tests/qemu-iotests/162
+++ b/tests/qemu-iotests/162
@@ -35,6 +35,9 @@ status=1 # failure is the defau
bdrv_iterate_format() did not actually sort the formats by name but by
"pointer interpreted as string". That is probably not what we intended
to do, so fix it (by changing qsort_strcmp() so it matches the example
from qsort()'s manual page).
Signed-off-by: Max Reitz
---
block.c | 2 +-
1 file ch
On 10/12/2016 08:23 AM, Greg Kurz wrote:
>
> But in fact, I'm afraid we have a more serious problem here... size
> comes from the guest and could cause g_malloc() to abort if QEMU has
> reached some RLIMIT... we need to call g_try_malloc0() and return
> ENOMEM if the allocation fails.
Even if it
On 10/12/2016 10:47 AM, Vladimir Sementsov-Ogievskiy wrote:
> HI all!
>
> My questions is: what are general recommendations in Qemu for return
> code, if we have Error **errp?
> What should I prefer: errp, duplicated by int return code, or void
> functions with errp?
Markus has already had severa
Peter,
Greetings from DigitalOcean. We're experiencing the same symptoms
without this patch.
We have, collectively, many gigabytes of un-planned-for RSS being used
per-hypervisor
that we would like to get rid of =).
Without explicitly trying this patch (will do that ASAP), we immediately
not
On 10/12/2016 03:49 PM, Max Reitz wrote:
> bdrv_iterate_format() did not actually sort the formats by name but by
> "pointer interpreted as string". That is probably not what we intended
> to do, so fix it (by changing qsort_strcmp() so it matches the example
> from qsort()'s manual page).
>
> Sig
On Thu, 13 Oct 2016 00:32:48 +0530
Kirti Wankhede wrote:
> On 10/12/2016 9:29 PM, Alex Williamson wrote:
> > On Wed, 12 Oct 2016 20:43:48 +0530
> > Kirti Wankhede wrote:
> >
> >> On 10/12/2016 7:22 AM, Tian, Kevin wrote:
> From: Kirti Wankhede [mailto:kwankh...@nvidia.com]
> Sent:
Dear Sir/Ma'am
I want to ‘annotate’ the translation buffers - (adding a mechanism in the
translation buffers where we can store how many times they were executed,
and, for each one, add some ‘amount’ could be power, could be anything). I
need held to understand the translation buffer code in qemu,
On Wed, Oct 12, 2016 at 10:58:43 +0200, Stefan Hajnoczi wrote:
> Hi Pranith,
> I was curious about the status of your MTTCG GSoC work:
>
> I saw your fence series which implements the noop memory barrier/fence
> instructions on various architectures, but I wasn't sure if that also
> covers the cas
It's a bare metal program so I don't really have anywhere to print to,
other than my custom function to output to the uart. I did double check all
the address to make sure they agreed with the documentation and the Qemu
source code. I tried changing around the destinations of the output just to
ver
Hi,
Your series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Message-id: 20161012204907.25941-1-mre...@redhat.com
Subject: [Qemu-devel] [PATCH 0/3] iotests: Skip 162 if there is no SSH su
Be consistent with the reference manual.
Signed-off-by: Michael Walle
---
target-lm32/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index dc64cc6..fa8416a 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/tr
Don't truncate the multiplication and do a 64 bit one instead because
because the result is stored in a 64 bit variable.
Spotted by coverity, CID 1167561.
Signed-off-by: Michael Walle
---
hw/display/milkymist-tmu2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/display/
On 10/12/2016 03:49 PM, Max Reitz wrote:
> Some block drivers may not be loaded yet, but qemu supports them
> nonetheless. bdrv_iterate_format() should report them, too.
>
> Signed-off-by: Max Reitz
> ---
> block.c | 18 ++
> 1 file changed, 18 insertions(+)
>
Reviewed-by: Eric
Drop the rX, rY and rZ stuff and use dc->r{0,1,2} directly. This should
also fix the false positive in coverity CID 1005720.
Signed-off-by: Michael Walle
---
target-lm32/translate.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/target-lm32/translate.c b/target-lm32/t
The lm32 target already has a disassembler which logs the assembly
instructions with "-d in_asm". Therefore, turn of the LOG_DIS() macro to
prevent logging the assembly instructions twice. Also turn the macro in a
one which is always compiled to catch any errors while the macro is turned
off.
Sign
On 10/12/2016 03:49 PM, Max Reitz wrote:
> Signed-off-by: Max Reitz
> ---
> tests/qemu-iotests/162 | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/tests/qemu-iotests/162 b/tests/qemu-iotests/162
> index f8eecb3..cad2bd7 100755
> --- a/tests/qemu-iotests/162
> +++ b/tests/qemu-iotests
On Mon, Oct 10, 2016 at 15:59:02 +0200, Paolo Bonzini wrote:
> See each patch. My attempt at fixing whatever I did when I obviously
> didn't know enough^W about the C11 memory model, and at setting a
> better example for future generations...
Just for context. Building on this patchset, is it now
This series is based on David's ppc-for-2.8 branch, and is also available from:
https://github.com/mdroth/qemu/commits/spapr-hotplug-event-update
Patches 1-4 address various deficiencies in how we currently handle option
vectors via ibm,client-architecture-support. This is done here in preparat
From: Bharata B Rao
Add support to hot remove pc-dimm memory devices.
Signed-off-by: Bharata B Rao
* add hooks to CAS/cmdline enablement of hotplug ACR support
Signed-off-by: Michael Roth
---
hw/ppc/spapr.c | 106 -
hw/ppc/spapr_drc.c |
Commit 0a417869:
spapr: Move memory hotplug to RTAS_LOG_V6_HP_ID_DRC_COUNT type
dropped per-DRC/per-LMB hotplugs event in favor of a bulk add via a
single LMB count value. This was to avoid overrunning the guest EPOW
event queue with hotplug events. This works fine, but relies on the
guest ex
Currently we access individual bytes of an option vector via
ldub_phys() to test for the presence of a particular capability
within that byte. Currently this is only done for the "dynamic
reconfiguration memory" capability bit. If that bit is present,
we pass a boolean value to spapr_h_cas_compose_
PAPR guests advertise their capabilities to the platform by passing
an ibm,architecture-vec structure via an
ibm,client-architecture-support hcall as described by LoPAPR v11,
B.6.2.3. during early boot.
Using this information, the platform enables the capabilities it
supports, then encodes a subse
ibm,architecture-vec-5 is supposed to encode all option vector 5 bits
negotiated between platform/guest. Currently we hardcode this property
in the boot-time device tree to advertise a single negotiated
capability, "Form 1" NUMA Affinity, regardless of whether or not CAS
has been invoked or that ca
Rather than machine instances having backward-compatible option
defaults that need to be repeatedly re-enabled for every new machine
type we introduce, we set the defaults appropriate for newer machine
types, then add code to explicitly disable instance options as needed
to maintain compatibility w
This updates the existing documentation to reflect recent updates to
the hotplug event structure, which are in draft form but slated
for inclusion in PAPR/LoPAPR.
Signed-off-by: Michael Roth
---
docs/specs/ppc-spapr-hotplug.txt | 55 +---
1 file changed, 46 in
Hotplug events were previously delivered using an EPOW interrupt
and were queued by linux guests into a circular buffer. For traditional
EPOW events like shutdown/resets, this isn't an issue, but for hotplug
events there are cases where this buffer can be exhausted, resulting
in the loss of hotplug
From: Bharata B Rao
Add support for DRC count indexed hotplug ID type which is primarily
needed for memory hot unplug. This type allows for specifying the
number of DRs that should be plugged/unplugged starting from a given
DRC index.
Signed-off-by: Bharata B Rao
* updated rtas_event_log_v6_hp
This adds machine options of the form:
-machine pseries,legacy-hotplug-events=true
-machine pseries,legacy-hotplug-events=false
to denote whether or not we wish to force the use of "legacy" style
hotplug events, which are surfaced through EPOW interrupts instead of
a dedicated interrupt sourc
In some cases, ibm,client-architecture-support calls can fail. This
could happen in the current code for situations where the modified
device tree segment exceeds the buffer size provided by the guest
via the call parameters. In these cases, QEMU will reset, allowing
an opportunity to regenerate th
On Tue, Oct 11, 2016 at 02:01:19PM -0700,
no-re...@ec2-52-6-146-230.compute-1.amazonaws.com wrote:
[...]
> GTESTER tests/check-qom-proplist
> Found prop 'bv'
> **
> ERROR:/tmp/qemu-test/src/tests/check-qom-proplist.c:521:test_dummy_class_iterator:
> code should not be reached
> GTester: last ra
On Wed, Oct 12, 2016 at 11:26:05AM +0200, Laurent Vivier wrote:
>
>
> On 12/10/2016 06:44, David Gibson wrote:
> > The 'spapr-pci-host-bridge' represents the virtual PCI host bridge (PHB)
> > for a PAPR guest. Unlike on x86, it's routine on Power (both bare metal
> > and PAPR guests) to have num
On Wed, Oct 12, 2016 at 02:06:10PM +0200, Laurent Vivier wrote:
>
>
> On 12/10/2016 12:55, David Gibson wrote:
> > On Wed, Oct 12, 2016 at 12:07:50PM +0200, Laurent Vivier wrote:
> >>
> >>
> >> On 12/10/2016 06:44, David Gibson wrote:
> >>> Currently the default PCI host bridge for the 'pseries'
Currently the default PCI host bridge for the 'pseries' machine type is
constructed with its IO windows in the 1TiB..(1TiB + 64GiB) range in
guest memory space. This means that if > 1TiB of guest RAM is specified,
the RAM will collide with the PCI IO windows, causing serious problems.
Problems wo
The current way we organize the IO windows into PCI space for the
pseries machine type has several problems.
- It makes it difficult to create very large MMIO spaces which is
necessary for certain PCI devices with very large BARs. This
problem has been known for a while.
- More recen
In pci-spapr.c (as in pci-pc.c from which it was derived), the
pci_hole_start/pci_hole_size and pci_iohole_start/pci_iohole_size pairs[1]
essentially define the region of PCI (not CPU) addresses in which MMIO
or PIO BARs respectively will be allocated.
The size value is relative to the start value
Currently the functions in pci-spapr.c (like pci-pc.c on which it's based)
don't distinguish between 32-bit and 64-bit PCI MMIO. At the moment, the
qemu side implementation is a bit weird and has a single MMIO window
straddling 32-bit and 64-bit regions, but we're likely to change that in
future.
The 'spapr-pci-host-bridge' represents the virtual PCI host bridge (PHB)
for a PAPR guest. Unlike on x86, it's routine on Power (both bare metal
and PAPR guests) to have numerous independent PHBs, each controlling a
separate PCI domain.
There are two ways of configuring the spapr-pci-host-bridge
The libqos code for accessing PCI on the spapr machine type uses IOBASE()
and MMIOBASE() macros to determine the address in the CPU memory map of
the windows to PCI address space.
This is a detail of the implementation of PCI in the machine type, it's not
specified by the PAPR standard. Real gues
Currently, the MMIO space for accessing PCI on pseries guests begins at
1 TiB in guest address space. Each PCI host bridge (PHB) has a 64 GiB
chunk of address space in which it places its outbound PIO and 32-bit and
64-bit MMIO windows.
This scheme as several problems:
- It limits guest RAM to
On real hardware, and under pHyp, the PCI host bridges on Power machines
typically advertise two outbound MMIO windows from the guest's physical
memory space to PCI memory space:
- A 32-bit window which maps onto 2GiB..4GiB in the PCI address space
- A 64-bit window which maps onto a large regi
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