Reviewed-by: Dmitry Fleytman
> On 19 Oct 2016, at 09:47 AM, Cao jin wrote:
>
> Internal flag msix_used is unnecessary, it has the same effect as
> msix_enabled().
>
> The corresponding msi flag is already dropped in commit 1070048e.
>
> CC: Dmitry Fleytman
> CC: Jason Wang
> CC: Markus Arm
According to the disscussion:
http://lists.nongnu.org/archive/html/qemu-devel/2016-09/msg08215.html
Let leaf function returns reasonable -errno, let caller decide how to
handle the return value.
Suggested-by: Markus Armbruster
CC: Markus Armbruster
CC: Alex Williamson
CC: Michael S. Tsirkin
C
msix_init() reports errors with error_report(), which is wrong when
it's used in realize(). The same issue was fixed for msi_init() in
commit 1108b2f.
For some devices(like e1000e, vmxnet3) who won't fail because of
msix_init's failure, suppress the error report by passing NULL error object.
Bon
Resolve the TODO, msix=auto means msix on; if user specify msix=on,
then device creation fail on msix_init failure.
Also undo the overwrites of user configuration of msix.
CC: Michael S. Tsirkin
CC: Hannes Reinecke
CC: Paolo Bonzini
CC: Markus Armbruster
CC: Marcel Apfelbaum
Signed-off-by: Ca
CC: Markus Armbruster
CC: Marcel Apfelbaum
CC: Michael S. Tsirkin
Signed-off-by: Cao jin
---
hw/pci/msix.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/pci/msix.c b/hw/pci/msix.c
index 0ec1cb1..0cee631 100644
--- a/hw/pci/msix.c
+++ b/hw/pci/msix.c
@@ -447,8 +
Also move certain hunk above, to place msix init related code together.
CC: Hannes Reinecke
CC: Paolo Bonzini
CC: Markus Armbruster
CC: Marcel Apfelbaum
CC: Michael S. Tsirkin
Signed-off-by: Cao jin
---
hw/scsi/megasas.c | 19 ++-
1 file changed, 6 insertions(+), 13 deletion
Commit afea4e14 seems forgetting to undo the overwrites, which is
unsuitable.
CC: Hannes Reinecke
CC: Paolo Bonzini
CC: Markus Armbruster
CC: Marcel Apfelbaum
CC: Michael S. Tsirkin
Signed-off-by: Cao jin
---
hw/scsi/megasas.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
di
Resolve the TODO, msix=auto means msix on; if user specify msix=on,
then device creation fail on msix_init failure.
CC: Gerd Hoffmann
CC: Michael S. Tsirkin
CC: Markus Armbruster
CC: Marcel Apfelbaum
Reviewed-by: Gerd Hoffmann
Signed-off-by: Cao jin
---
hw/usb/hcd-xhci.c | 35 +
v4 changelog
1. add the missed comment of "errp" in the msix_init's function comment
2. fix typo: msic --> msix
3. fix a build failure due to "copy&paste" error, in patch
"megasas: change behaviour of msix switch"
4. separate the issus-fix part of vmxnet3's patch
5. a new patch added in the end
On migration target, msix_vector_use() will be called in vmxnet3_post_load()
in second time, without a matching second call to msi_vector_unuse(),
which results in vector reference leak.
CC: Dmitry Fleytman
CC: Jason Wang
CC: Markus Armbruster
Signed-off-by: Cao jin
---
hw/net/vmxnet3.c | 10
Param checking/correcting code of xchi->numintrs should be placed before
it is used.
Also move some resource-alloc code down, save the strenth to free them
on msi_init's failure.
CC: Gerd Hoffmann
CC: Markus Armbruster
CC: Marcel Apfelbaum
CC: Michael S. Tsirkin
Reviewed-by: Gerd Hoffmann
Si
On Tue, Oct 18, 2016 at 11:45 PM Gerd Hoffmann wrote:
> Three commits allocated pci ids in include/hw/pci/pci.h
> without also updating docs/specs/pci-ids.txt:
>
> bf439db pci: Allocate PCIe host bridge PCI ID
> 40d14be hw/pci: introduce PCI Expander Bridge (PXB)
> 02b0743 hw/pxb: introduce
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1476857207-10091-1-git-send-email-nik...@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH v2 0/2] POWER9 TCG enablements - part6
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=ba
Add required helpers (GEN_XX2FORM_EO) for supporting this instruction.
xxbrh: VSX Vector Byte-Reverse Halfword
xxbrw: VSX Vector Byte-Reverse Word
xxbrd: VSX Vector Byte-Reverse Doubleword
xxbrq: VSX Vector Byte-Reverse Quadword
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate.c
Vector Integer Negate Instructions:
vnegw: Vector Negate Word
vnegd: Vector Negate Doubleword
Signed-off-by: Nikunj A Dadhania
---
target-ppc/helper.h | 2 ++
target-ppc/int_helper.c | 12
target-ppc/translate/vmx-impl.inc.c | 2 ++
target-ppc/translat
This series contains 6 new instructions for POWER9 ISA3.0
Vector Integer Negate
Vector Byte-Reverse
Patches:
02:
vnegw: Vector Negate Word
vnegd: Vector Negate Doubleword
03:
xxbrh: VSX Vector Byte-Reverse Halfword
xxbrw: VSX Vector Byte-Reverse Word
xxbrd: VSX Vector By
Richard Henderson writes:
> On 10/12/2016 07:21 PM, David Gibson wrote:
>>> +static void gen_bswap32x4(TCGv_i64 outh, TCGv_i64 outl,
>>> + TCGv_i64 inh, TCGv_i64 inl)
>>> +{
>>> +TCGv_i64 hi = tcg_temp_new_i64();
>>> +TCGv_i64 lo = tcg_temp_new_i64();
>>> +
>>> +
David Gibson writes:
> [ Unknown signature status ]
> On Wed, Oct 12, 2016 at 10:38:52AM +0530, Nikunj A Dadhania wrote:
>> Vector Integer Negate Instructions:
>>
>> vnegw: Vector Negate Word
>> vnegd: Vector Negate Doubleword
>>
>> Signed-off-by: Nikunj A Dadhania
>> ---
>> target-ppc/helper
On Tue, Oct 18, 2016 at 06:28:26PM +0200, Laurent Vivier wrote:
>
>
> On 18/10/2016 17:14, Laurent Vivier wrote:
> >
> >
> > On 18/10/2016 12:52, David Gibson wrote:
> >> tco_test uses the libqos PCI code to access the device. This makes perfect
> >> sense for the PCI config space accesses. H
On Tue, Oct 18, 2016 at 10:46:39PM +0200, Thomas Huth wrote:
> The OpenBIOS NVRAM set-up is based on the layout defined in the CHRP
> (Common Hardware Reference Platform) specification. This is the same
> layout that is also used by the PAPR specification and thus by the SLOF
> firmware of the pser
On Tue, Oct 18, 2016 at 06:48:16PM +0200, Laurent Vivier wrote:
>
>
> On 18/10/2016 12:52, David Gibson wrote:
> > The usual use model for the libqos PCI functions is to map a specific PCI
> > BAR using qpci_iomap() then pass the returned token into IO accessor
> > functions. This, and the fact
On Tue, Oct 18, 2016 at 05:14:04PM +0200, Laurent Vivier wrote:
>
>
> On 18/10/2016 12:52, David Gibson wrote:
> > tco_test uses the libqos PCI code to access the device. This makes perfect
> > sense for the PCI config space accesses. However for IO, rather than the
> > usual PCI approach of ma
On Tue, Oct 18, 2016 at 03:28:17PM +0200, Laurent Vivier wrote:
>
>
> On 18/10/2016 12:52, David Gibson wrote:
> > The PCI IO space (aka PIO, aka legacy IO) and PCI memory space (aka MMIO)
> > are distinct address spaces by the PCI spec (although parts of one might be
> > aliased to parts of the
On Tue, Oct 18, 2016 at 05:00:08PM +0200, Laurent Vivier wrote:
>
>
> On 18/10/2016 12:52, David Gibson wrote:
> > The PCI backends in libqos each supply an iomap() and iounmap() function
> > which is used to set up a specified PCI BAR. But PCI BAR allocation takes
> > place entirely within PCI
On Tue, Oct 18, 2016 at 03:50:23PM -0500, Michael Roth wrote:
> With the addition of "numa_node" properties for PHBs we began
> advertising NUMA affinity in cases where nb_numa_nodes > 1.
>
> Since the default on the guest side is to make no assumptions about
> PHB NUMA affinity (defaulting to -1)
On Tue, Oct 18, 2016 at 06:14:09PM +0200, Laurent Vivier wrote:
>
>
> On 18/10/2016 12:52, David Gibson wrote:
> > ivshmem implements a block of shared memory in a PCI BAR. Currently our
> > test case accesses this using qtest_mem{read,write}. However, deducing
> > the correct addresses for the
On Tue, Oct 18, 2016 at 03:27:09PM +0200, Greg Kurz wrote:
> On Tue, 18 Oct 2016 21:52:06 +1100
> David Gibson wrote:
>
> > The 'addr' parameter to qvirtio_config_read*() doesn't have a consistent
> > meaning: when using the virtio-pci versions, it's a full PCI space address,
> > but for virtio-m
On Wed, Oct 19, 2016 at 10:15:16AM +1100, Alexey Kardashevskiy wrote:
> The following changes since commit bd56ff33ed174cbe825a3b9929399ca804ce0f27:
>
> pseries: Update SLOF firmware image to 20161019 (2016-10-19 10:05:26 +1100)
>
> are available in the git repository at:
>
> g...@github.com
On 19/10/16 03:34, Richard Henderson wrote:
> The two main goals in this patch set are:
>
> * Make use of the new MO_ALIGN_* flags, to allow less use of
>check_align, and support partially misaligned fp memory ops.
>
> * More cleanups for ASIs, in the end using the new atomic ops.
>
> The
An iopmem device is one which exposes volatile or non-volatile memory mapped
directly to a BAR region. One purpose is to provide buffers to do peer
to peer transfers on the bus. As such this device uses QEMU's drive
backing store to simulate non-volatile memory and provides through a
mapped BAR win
Public bug reported:
I'm building the master tree on a multicore ARMv8 machine running Ubuntu
16.04. The build worked just fine, using the simple directions in the
README file and "make -j 64" to do the build.
Next, I did "make test", and got this:
emv@armv8hello:~/src/qemu/qemu/build$ make test
> -Original Message-
> From: Stefan Hajnoczi [mailto:stefa...@redhat.com]
> Sent: Tuesday, October 18, 2016 6:09 PM
> Subject: Re: [virtio-dev] RE: [Qemu-devel] [PATCH v7 09/12] virtio-crypto: add
> data queue processing handler
>
> On Mon, Oct 17, 2016 at 06:29:42AM +, Gonglei (Arei)
On 10/19/2016 01:04 AM, Richard Henderson wrote:
> On 10/18/2016 02:50 PM, Marek Vasut wrote:
>> +/* Special R-Type instruction opcode */
>> +#define INSN_R_TYPE 0x3A
>> +
>> +/* I-Type instruction parsing */
>> +#define I_TYPE(instr, code) \
>> +struct {
On 10/19/2016 03:24 AM, Richard Henderson wrote:
> On 10/18/2016 03:05 PM, Marek Vasut wrote:
Thanks, I hope this is fixed now, although I mostly special-case the
R_ZERO handling throughout the code. Any writes to R_ZERO are now
ignored and any usage is converted to mov/movi instruct
From: Chris Wulff
Add support for emulating Altera NiosII R1 architecture into qemu.
This patch is based on previous work by Chris Wulff from 2012 and
updated to latest mainline QEMU.
Signed-off-by: Marek Vasut
Cc: Chris Wulff
Cc: Jeff Da Silva
Cc: Ley Foon Tan
Cc: Sandra Loosemore
Cc: Yves
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1476844470-29763-1-git-send-email-...@twiddle.net
Subject: [Qemu-devel] [PATCH v2 00/15] target-sparc improvements
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=
Now that we never call out to helpers when direct accesses can
handle an asi, remove the corresponding code in those helpers.
For ldda, this removes the entire helper.
Signed-off-by: Richard Henderson
---
target-sparc/helper.h | 1 -
target-sparc/ldst_helper.c | 811 --
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 31 +++
1 file changed, 7 insertions(+), 24 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 4c0346c..1ef2654 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/tr
The cpu is allowed to require stricter alignment on these 8- and 16-byte
operations, and the OS is required to fix up the accesses as necessary,
so the previous code was not wrong.
However, we can easily handle this misalignment for all direct 8-byte
operations and for direct 16-byte loads.
We mu
At the same time, fix a problem with stqf_asi, when
a write might access two pages.
Signed-off-by: Richard Henderson
---
target-sparc/helper.h | 2 --
target-sparc/ldst_helper.c | 72 --
target-sparc/translate.c | 79 +++
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 63
1 file changed, 63 insertions(+)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 0fb361a..3b3389c 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/t
Signed-off-by: Richard Henderson
---
target-sparc/helper.h | 4 ---
target-sparc/ldst_helper.c | 29 ---
target-sparc/translate.c | 70 +++---
3 files changed, 47 insertions(+), 56 deletions(-)
diff --git a/target-sparc/helper.h b/t
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index ee7bbc4..86432ac 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2046,6 +2046,1
On 10/18/2016 10:59 PM, Alex Williamson wrote:
> On Tue, 18 Oct 2016 20:38:21 +0800
> Jike Song wrote:
>> On 10/18/2016 12:02 AM, Alex Williamson wrote:
>>> On Fri, 14 Oct 2016 15:19:01 -0700
>>> Neo Jia wrote:
>>>
On Fri, Oct 14, 2016 at 10:51:24AM -0600, Alex Williamson wrote:
> O
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 52 +++-
1 file changed, 21 insertions(+), 31 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 8cd8bb6..8d879a9 100644
--- a/target-sparc/translate.c
+++
The functions that these generate are no longer used.
Signed-off-by: Richard Henderson
---
target-sparc/cpu.h | 8
1 file changed, 8 deletions(-)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index e94b8f1..5fb0ed1 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -638
It's handy to have a mmu idx for physical addresses, so
that mmu disabled and physical access asis can use the
same path as normal accesses.
Signed-off-by: Richard Henderson
---
target-sparc/cpu.h | 25 +---
target-sparc/ldst_helper.c | 27 ++
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 19 ---
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index a123c0b..4c0346c 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@
Several helpers call helper_raise_exception directly, which requires
in turn that their callers have performed save_state. The new function
allows a TCG return address to be passed in so that we can restore
PC + NPC + flags data from that.
This fixes a bug in the usage of helper_check_align, whos
This allows us to enforce 16 and 64-byte alignment
without any extra overhead.
Signed-off-by: Richard Henderson
Message-Id: <1466744068-6615-1-git-send-email-...@twiddle.net>
---
target-sparc/translate.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/t
The two main goals in this patch set are:
* Make use of the new MO_ALIGN_* flags, to allow less use of
check_align, and support partially misaligned fp memory ops.
* More cleanups for ASIs, in the end using the new atomic ops.
The final two patches require the "cmpxchg atomic" v6 patch set.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 49 +---
1 file changed, 21 insertions(+), 28 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index e7e07de..8cd8bb6 100644
--- a/target-sparc/translate.c
+++
As used by HelenOS, presumably for ultra 2 and 3,
prior to the sun4v platform and the current twinx names.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 8
1 file changed, 8 insertions(+)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 86432ac..
On 10/18/2016 03:05 PM, Marek Vasut wrote:
Thanks, I hope this is fixed now, although I mostly special-case the
R_ZERO handling throughout the code. Any writes to R_ZERO are now
ignored and any usage is converted to mov/movi instructions where
applicable.
We've done that in the past, but in the
On Tue, Oct 18, 2016 at 01:56:53PM +0200, Laurent Vivier wrote:
>
>
> On 18/10/2016 12:52, David Gibson wrote:
> > This series contains a number of cleanups to the libqos code for
> > accessing PCI devices, and to tests which use it.
> >
> > The general aim is to improve the consistency of seman
On Mon, 10/17 15:54, Paolo Bonzini wrote:
> This patch reorganizes aio_poll callers to establish new rules for
> dataplane locking. The idea is that I/O operations on a dataplane
> BDS (i.e. one where the AioContext is not the main one) do not call
> aio_poll anymore. Instead, they wait for the o
On Wed, 10/19 08:55, Fam Zheng wrote:
> Modulo the one harmful question, series:
s/harmful/unharmful/, apparently.
Fam
On Mon, 10/17 15:54, Paolo Bonzini wrote:
> This will be needed by bdrv_reopen_multiple, which calls
> bdrv_drain_all and thus will *release* the AioContext.
Looks okay, but I wonder how bdrv_drain_all releasing AioContext break anything?
Fam
>
> Signed-off-by: Paolo Bonzini
> ---
> v1
On Wed, Sep 28, 2016 at 11:07:13AM +0200, Gerd Hoffmann wrote:
> Hi,
>
> After a looong break finally the next round
> of the seabios serial console patches.
Hi Gerd,
Sorry for the delay in responding.
I ran some tests on your series and it looks like it causes issues
with some systems that a
On 18/10/16 22:00, Igor Mammedov wrote:
> On Tue, 11 Oct 2016 09:19:10 +1100
> Alexey Kardashevskiy wrote:
>
>> Ping, anyone?
> I have a similar patch
> http://patchwork.ozlabs.org/patch/681709/
> which bumps limit to 288 and does a little bit more
> so it wouldn't affect current users.
Why 288
Wow, a full 3 years later!
Well, better late than never...
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https://bugs.launchpad.net/bugs/1201446
Title:
Instructions not supported by targeted CPU do not throw SIGILL
Status in QE
On Tue, 18 Oct 2016 02:52:01 +0530
Kirti Wankhede wrote:
> Design for Mediated Device Driver:
> Main purpose of this driver is to provide a common interface for mediated
> device management that can be used by different drivers of different
> devices.
>
> This module provides a generic interface
The following changes since commit bd56ff33ed174cbe825a3b9929399ca804ce0f27:
pseries: Update SLOF firmware image to 20161019 (2016-10-19 10:05:26 +1100)
are available in the git repository at:
g...@github.com:aik/qemu.git
for you to fetch changes up to bd56ff33ed174cbe825a3b9929399ca804ce0
On 10/18/2016 02:50 PM, Marek Vasut wrote:
+/* Special R-Type instruction opcode */
+#define INSN_R_TYPE 0x3A
+
+/* I-Type instruction parsing */
+#define I_TYPE(instr, code) \
+struct { \
+uint8_t op; \
+union {
On 2016-10-17 07:35, Richard Henderson wrote:
> On 10/17/2016 03:55 AM, Christian Borntraeger wrote:
> > On 10/17/2016 10:26 AM, Thomas Huth wrote:
> > > On 14.10.2016 20:58, Michael Tokarev wrote:
> > > > Hi.
> > > >
> > > > This commit: c9bc3437a905b660561a26cd4ecc64579843267b
> > > > Author: Ri
On 10/18/2016 10:44 PM, Richard Henderson wrote:
> On 10/18/2016 11:32 AM, Marek Vasut wrote:
>> But the instruction encoding does, so I can use the field from the
>> instruction to directly index the register array.
>
> Well, no, you can't.
>
> In fact, it would be cleaner to have multiple array
Add nios2 disassembler support. This patch is composed from binutils files
from commit "Opcodes and assembler support for Nios II R2". The files from
binutils used in this patch are:
include/opcode/nios2.h
include/opcode/nios2r1.h
include/opcode/nios2r2.h
opcodes/nios2-opc.c
op
From: Chris Wulff
Add support for emulating Altera NiosII R1 architecture into qemu.
This patch is based on previous work by Chris Wulff from 2012 and
updated to latest mainline QEMU.
Signed-off-by: Marek Vasut
Cc: Chris Wulff
Cc: Jeff Da Silva
Cc: Ley Foon Tan
Cc: Sandra Loosemore
Cc: Yves
Add the Altera 10M50 Nios2 GHRD model. This allows emulating the
10M50 development kit with the Nios2 GHRD loaded in the FPGA. It
is possible to boot Linux kernel and run userspace, thus far only
from initrd as storage support is not yet implemented.
Signed-off-by: Marek Vasut
Cc: Chris Wulff
Cc
Add missing bits for qemu-user required for emulating Altera Nios2
userspace binaries.
Signed-off-by: Marek Vasut
Cc: Chris Wulff
Cc: Jeff Da Silva
Cc: Ley Foon Tan
Cc: Sandra Loosemore
Cc: Yves Vandervennet
---
V3: Checkpatch cleanup
---
include/elf.h | 2 +
linux-use
On 18/10/2016 16:56, Pranith Kumar wrote:
> gcc does not warn about the wrong type since it is a void pointer
> which can be cast to any type.
>
> Signed-off-by: Pranith Kumar
> ---
> translate-all.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/translate-all.c b/tr
From: Chris Wulff
Add the Altera timer model.
Signed-off-by: Marek Vasut
Cc: Chris Wulff
Cc: Jeff Da Silva
Cc: Ley Foon Tan
Cc: Sandra Loosemore
Cc: Yves Vandervennet
---
V3: Checkpatch cleanup
---
hw/timer/Makefile.objs | 1 +
hw/timer/altera_timer.c | 237
From: Chris Wulff
Add the Altera Nios2 internal interrupt controller model.
Signed-off-by: Marek Vasut
Cc: Chris Wulff
Cc: Jeff Da Silva
Cc: Ley Foon Tan
Cc: Sandra Loosemore
Cc: Yves Vandervennet
---
V3: Checkpatch cleanup
---
hw/intc/Makefile.objs | 1 +
hw/intc/nios2_iic.c | 103 ++
Add remaining bits of the Altera NiosII R1 support into qemu, which
is documentation, MAINTAINERS file entry, configure bits, arch_init
and configuration files for both linux-user (userland binaries) and
softmmu (hardware emulation).
Signed-off-by: Marek Vasut
Cc: Chris Wulff
Cc: Jeff Da Silva
- Original Message -
> From: "Pranith Kumar"
> To: "Paolo Bonzini" , "Sergey Fedorov"
> , "Cao jin"
> , "open list:All patches CC here"
>
> Sent: Tuesday, October 18, 2016 4:56:19 PM
> Subject: [PATCH 1/2] docs/rcu: Distinguish rcu_dereference and atomic_rcu_read
>
> Signed-off-by: P
- Original Message -
> From: "Cornelia Huck"
> To: "Paolo Bonzini"
> Cc: qemu-devel@nongnu.org, stefa...@redhat.com, borntrae...@de.ibm.com,
> f...@redhat.com, m...@redhat.com
> Sent: Tuesday, October 18, 2016 7:24:45 PM
> Subject: Re: [PATCH 00/12] virtio: cleanup ioeventfd start/stop
** Changed in: qemu
Status: New => Incomplete
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/786440
Title:
qcow2 double free
Status in QEMU:
Incomplete
Bug description:
version 0.14.1 w
fw_cfg_write() support has been removed since QEMU 2.4, so I think we
can treat this as fixed now:
http://git.qemu.org/?p=qemu.git;a=commitdiff;h=023e3148567ac898c725813
** Changed in: qemu
Status: New => Fix Released
--
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On 18 October 2016 at 21:49, Eduardo Habkost wrote:
> On Tue, Oct 18, 2016 at 09:30:01PM +0100, Peter Maydell wrote:
>> Lots of stuff in a device's C struct is strictly internal
>> and not to be messed with. I thought that QOM properties
>> were essentially how a device defined its public (and
>>
On Tue, Oct 18, 2016 at 09:30:01PM +0100, Peter Maydell wrote:
> On 18 October 2016 at 19:45, Eduardo Habkost wrote:
> > On Tue, Oct 18, 2016 at 07:12:51PM +0100, Peter Maydell wrote:
> >> We actually have a concrete instance in the tree at the moment:
> >> the raspberry pi 2. Specifically hw/arm/
On Tue, Oct 18, 2016 at 10:52:14PM +0200, Radim Krčmář wrote:
[...]
> The main problem is that QEMU changes virtual_tsc_khz when migrating
> without hardware scaling, so KVM is forced to get nanoseconds wrong ...
>
> If QEMU doesn't want to keep the TSC frequency constant, then it would
> be bette
The system and free space NVRAM partitions (for OpenBIOS) are created
in exactly the same way as the Mac-style CHRP NVRAM partitions, so we
can use the new common helper functions to do this job here, too.
Signed-off-by: Thomas Huth
---
hw/sparc/sun4m.c | 33 ++---
With the addition of "numa_node" properties for PHBs we began
advertising NUMA affinity in cases where nb_numa_nodes > 1.
Since the default on the guest side is to make no assumptions about
PHB NUMA affinity (defaulting to -1), there is still a valid use-case
for explicitly defining a PHB's NUMA a
In case we do not load the NVRAM contents from a file, use the new
CHRP NVRAM helper functions to pre-initialize the NVRAM partitions.
This way we can support the "-prom-env" parameter of QEMU on the
pseries machine, too.
Signed-off-by: Thomas Huth
---
hw/nvram/spapr_nvram.c | 6 ++
1 file c
2016-10-18 15:09-0200, Marcelo Tosatti:
> On Tue, Oct 18, 2016 at 03:41:03PM +0200, Paolo Bonzini wrote:
>> On 18/10/2016 01:58, Marcelo Tosatti wrote:
>> > > We should also blacklist the TSC deadline timer when invtsc is not
>> > > available.
>> >
>> > Actually, a nicer fix would be to check the d
The "system partition" and "free space" partition layouts are
defined by the CHRP and LoPAPR specification, and used by
OpenBIOS and SLOF. We can re-use this code for other machines
that use OpenBIOS and SLOF, too. So let's make this code independent
from the MAC NVRAM environment and put it into t
Everything that is related to CHRP NVRAM should rather reside in
chrp_nvram.c / chrp_nvram.h instead of openbios_firmware_abi.h.
Signed-off-by: Thomas Huth
---
hw/nvram/chrp_nvram.c| 31 +++-
hw/nvram/mac_nvram.c | 7 +++---
include/hw
The header now only contains inline functions related to the
Sun NVRAM, so the a name like sun_nvram.h seems to be more
appropriate now.
Signed-off-by: Thomas Huth
---
hw/sparc/sun4m.c | 2 +-
hw/sparc64/sun4u.c| 2
The OpenBIOS NVRAM set-up is based on the layout defined in the CHRP
(Common Hardware Reference Platform) specification. This is the same
layout that is also used by the PAPR specification and thus by the SLOF
firmware of the pseries machine. By refactoring the NVRAM code from
mac_nvram.c, we can u
On 10/18/2016 11:32 AM, Marek Vasut wrote:
But the instruction encoding does, so I can use the field from the
instruction to directly index the register array.
Well, no, you can't.
In fact, it would be cleaner to have multiple arrays -- one for general
registers and one for control registers
Three commits allocated pci ids in include/hw/pci/pci.h
without also updating docs/specs/pci-ids.txt:
bf439db pci: Allocate PCIe host bridge PCI ID
40d14be hw/pci: introduce PCI Expander Bridge (PXB)
02b0743 hw/pxb: introduce pxb-pcie expander for PCIe machines
This patch updates pci-ids.tx
On 18 October 2016 at 19:45, Eduardo Habkost wrote:
> On Tue, Oct 18, 2016 at 07:12:51PM +0100, Peter Maydell wrote:
>> We actually have a concrete instance in the tree at the moment:
>> the raspberry pi 2. Specifically hw/arm/bcm2836.c sets the
>> mp_affinity for each cpu to 0xF00 | n (where n is
On Tue, Oct 18, 2016 at 09:22:50PM +0200, Laurent Vivier wrote:
> Since commit 42ecaba ("target-i386: Call cpu_exec_init() on realize"),
> , commit 6dd0f83 ("target-ppc: Move cpu_exec_init() call to realize
> function"),
> and commit c6644fc ("s390x/cpu: Get rid of side effects when creating a
>
On 10/18/2016 02:45 PM, John Snow wrote:
>
>
> On 10/18/2016 06:22 AM, Kevin Wolf wrote:
>> This tests the different supported methods to create floppy drives and
>> how they interact.
>>
>> +function check_floppy_qtree()
>> +{
>> +echo
>> +echo Testing: "$@" | _filter_testdir
>> +
>> +
On 10/18/2016 06:22 AM, Kevin Wolf wrote:
This tests the different supported methods to create floppy drives and
how they interact.
Signed-off-by: Kevin Wolf
---
tests/qemu-iotests/172 | 242 +
tests/qemu-iotests/172.out | 1205
tests
Hello Jason,
+-- On Thu, 11 Aug 2016, Dmitry Fleytman wrote --+
| Reviewed-by: Dmitry Fleytman
|
| > @@ -531,6 +531,7 @@ static void vmxnet3_complete_packet(VMXNET3State *s,
int qidx, uint32_t tx_ridx)
| >
| > VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx,
&s->txq_descr[qidx].comp_ring);
| >
On 10/18/2016 05:31 PM, Richard Henderson wrote:
> On 10/17/2016 08:58 PM, Marek Vasut wrote:
>>> There's no particular reason why R_PC needs to be 64; if you change it
>>> to 32, you can simplify this.
>>
>> I believe this is in fact needed, see [1] page 18 (section 2, Register
>> file), quote:
>>
On Sat, Oct 15, 2016 at 04:26:13PM +0800, Xiubo Li wrote:
> Make it a bit clearer and more readable.
>
> Signed-off-by: Xiubo Li
> CC: John Snow
> ---
>
> V2:
> - Advice from John Snow. Thanks.
>
>
> block/rbd.c | 25 -
> 1 file changed, 12 insertions(+), 13 deletions
Put in cpu_exec_initfn() what initializes the CPU,
and leave in cpu_exec_init() what adds it to the environment.
As cpu_exec_initfn() is called by all XX_cpu_initfn(), call it
directly in cpu_common_initfn().
cpu_exec_init() is now a realize function, it will be renamed
to cpu_exec_realizefn() and
As cpu_exec_exit() mirrors the cpu_exec_realizefn(),
rename it as cpu_exec_unrealizefn().
Create and register a cpu_common_unrealizefn() function for
the CPU device class and call cpu_exec_unrealizefn() from
this function.
Remove cpu_exec_exit() from cpu_common_finalize()
(which mirrors init, not
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