[Qemu-devel] [PULL 0/4] cryptodev patches

The following changes since commit a470b33259bf82ef2336bfcd5d07640562d3f63b: Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2016-12-22 19:23:51 +) are available in the git repository at: https://github.com/gongleiarei/qemu.git

[Qemu-devel] [PULL 3/4] cryptodev: remove single-DES support in cryptodev

From: "Longpeng(Mike)" Single-DES is obsolete and it's broken/useless for decades, we should remove it in cryptodev, as suggested by Daniel. Guest who wants to use this obsolete cipher alg will use its built-in implementation instead. Signed-off-by: Longpeng(Mike)

[Qemu-devel] [PULL 4/4] cryptodev: add 3des-ede support

From: "Longpeng(Mike)" This patch add 3des-ede support for cryptodev. However this is effective only when backend using libgcrypt/nettle, because cipher-builtin doesn't support 3des-ede yet. Signed-off-by: Longpeng(Mike) Signed-off-by: Gonglei

[Qemu-devel] [PULL 2/4] cryptodev: add xts(aes) support

From: "Longpeng(Mike)" This patch add xts(aes) support. Signed-off-by: Longpeng(Mike) Reviewed-by: Gonglei Signed-off-by: Gonglei --- backends/cryptodev-builtin.c | 8 1 file changed, 8

[Qemu-devel] [PULL 1/4] cryptodev: fix the check of aes algorithm

From: "Longpeng(Mike)" As the key length of xts(aes) is different with other mode of aes, so we should check specially in cryptodev_builtin_get_aes_algo, if it is xts mode. Signed-off-by: Longpeng(Mike) Reviewed-by: Gonglei

[Qemu-devel] [Bug 1469924] Re: qemu-kvm crash when guest os is booting

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1469924 Title: qemu-kvm

[Qemu-devel] [PATCH 64/65] tcg/ppc: Handle ctpop opcode

Cc: qemu-...@nongnu.org Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 5 +++-- tcg/ppc/tcg-target.inc.c | 12 +++- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 57e66cf..abd8b3d

[Qemu-devel] [PATCH 58/65] target-sparc: Use ctpop helper

Cc: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/helper.c| 5 - target/sparc/helper.h| 1 - target/sparc/translate.c | 2 +- 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/target/sparc/helper.c

[Qemu-devel] [PATCH 55/65] target-alpha: Use ctpop helper

Signed-off-by: Richard Henderson --- target/alpha/helper.h | 2 -- target/alpha/int_helper.c | 5 - target/alpha/translate.c | 2 +- 3 files changed, 1 insertion(+), 8 deletions(-) diff --git a/target/alpha/helper.h b/target/alpha/helper.h index eed3906..d60f208

[Qemu-devel] [PATCH 48/65] tcg/i386: Handle ctz and clz opcodes

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 8 +-- tcg/i386/tcg-target.inc.c | 125 ++ 2 files changed, 120 insertions(+), 13 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index

[Qemu-devel] [PATCH 41/65] tcg/aarch64: Handle ctz and clz opcodes

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 8 tcg/aarch64/tcg-target.inc.c | 48 2 files changed, 52 insertions(+), 4 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h

[Qemu-devel] [PATCH 38/65] target-arm: Use clz opcode

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper-a64.c| 10 -- target/arm/helper-a64.h| 2 -- target/arm/helper.c| 5 - target/arm/helper.h| 1 - target/arm/translate-a64.c | 8

[Qemu-devel] [PATCH 36/65] target-unicore32: Use clz opcode

Signed-off-by: Richard Henderson --- target/unicore32/helper.c| 10 -- target/unicore32/helper.h| 3 --- target/unicore32/translate.c | 6 +++--- 3 files changed, 3 insertions(+), 16 deletions(-) diff --git a/target/unicore32/helper.c

[Qemu-devel] [PATCH 33/65] target-s390x: Use clz opcode

Signed-off-by: Richard Henderson --- target/s390x/helper.h | 1 - target/s390x/int_helper.c | 6 -- target/s390x/translate.c | 2 +- 3 files changed, 1 insertion(+), 8 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 207a6e7..9102071

[Qemu-devel] [PATCH 62/65] tests: New test-bitcnt

From: Alex Bennée Add some unit tests for bit count functions (currently only ctpop). As the routines are based on the Hackers Delight optimisations I based the test patterns on their tests. Signed-off-by: Alex Bennée Signed-off-by: Richard

[Qemu-devel] [PATCH 34/65] target-tilegx: Use clz and ctz opcodes

Signed-off-by: Richard Henderson --- target/tilegx/helper.c| 10 -- target/tilegx/helper.h| 2 -- target/tilegx/translate.c | 4 ++-- 3 files changed, 2 insertions(+), 14 deletions(-) diff --git a/target/tilegx/helper.c b/target/tilegx/helper.c index

[Qemu-devel] [PATCH 61/65] qemu/host-utils.h: Reduce the operation count in the fallback ctpop

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/qemu/host-utils.h | 25 +++-- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index

[Qemu-devel] [PATCH 28/65] target-cris: Use clz opcode

Cc: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/cris/helper.h| 1 - target/cris/op_helper.c | 5 - target/cris/translate.c | 2 +- 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/target/cris/helper.h

[Qemu-devel] [PATCH 26/65] disas/ppc: Handle popcnt and cnttz

Cc: qemu-...@nongnu.org Signed-off-by: Richard Henderson --- disas/ppc.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/disas/ppc.c b/disas/ppc.c index bd05623..ed7e0d0 100644 --- a/disas/ppc.c +++ b/disas/ppc.c @@ -1955,6 +1955,9 @@ extract_tbr (unsigned long

[Qemu-devel] [PATCH 57/65] target-s390x: Avoid a loop for popcnt

Signed-off-by: Richard Henderson --- target/s390x/int_helper.c | 15 ++- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/target/s390x/int_helper.c b/target/s390x/int_helper.c index 5bc470b..f26f36a 100644 --- a/target/s390x/int_helper.c +++

[Qemu-devel] [PATCH 59/65] target-tilegx: Use ctpop helper

Signed-off-by: Richard Henderson --- target/tilegx/helper.c| 5 - target/tilegx/helper.h| 1 - target/tilegx/translate.c | 2 +- 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/target/tilegx/helper.c b/target/tilegx/helper.c index b6f5e29..4964bb9

[Qemu-devel] [Bug 1469978] Re: compile qemu use with KVM machine not supported

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1469978 Title: compile

[Qemu-devel] [PATCH 22/65] tcg: Pass the opcode width to target_parse_constraint

This will let us choose how to interpret a given constraint depending on whether the opcode is 32- or 64-bit. Which will let us share more constraint combinations between opcodes. At the same time, change the interface to return the advanced pointer instead of passing it in/out by reference.

[Qemu-devel] [PATCH 51/65] target-arm: Use clrsb helper

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper-a64.c| 10 -- target/arm/helper-a64.h| 2 -- target/arm/translate-a64.c | 8 3 files changed, 4 insertions(+), 16 deletions(-) diff --git

[Qemu-devel] [PATCH 56/65] target-ppc: Use ctpop helper

Cc: qemu-...@nongnu.org Signed-off-by: Richard Henderson --- target/ppc/helper.h | 3 +-- target/ppc/int_helper.c | 18 +++--- target/ppc/translate.c | 6 +- 3 files changed, 9 insertions(+), 18 deletions(-) diff --git a/target/ppc/helper.h

[Qemu-devel] [PATCH 65/65] tcg/i386: Handle ctpop opcode

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 5 +++-- tcg/i386/tcg-target.inc.c | 12 +++- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b8f73f5..21d96ec 100644 ---

[Qemu-devel] [PATCH 21/65] tcg: Transition flat op_defs array to a target callback

This will allow the target to tailor the constraints to the auto-detected ISA extensions. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 14 ++-- tcg/arm/tcg-target.inc.c | 14 ++--

[Qemu-devel] [PATCH 52/65] target-tricore: Use clrsb helper

Tested-by: Bastian Koppelmann Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/tricore/helper.h| 1 - target/tricore/op_helper.c | 5 - target/tricore/translate.c | 2 +- 3

[Qemu-devel] [PATCH 50/65] tcg: Add helpers for clrsb

The number of actual invocations does not warrent an opcode, and the backends generating it. But at least we can eliminate redundant helpers. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg-runtime.c | 10 ++ tcg/tcg-op.c

[Qemu-devel] [PATCH 63/65] tcg: Use ctpop to generate ctz if needed

Particularly when andc is also available, this is two insns shorter than using clz to compute ctz. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 100 +++ 1 file changed, 60 insertions(+), 40 deletions(-) diff --git

[Qemu-devel] [PATCH 46/65] tcg/i386: Hoist common arguments in tcg_out_op

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 197 ++ 1 file changed, 95 insertions(+), 102 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index e497bef..83572ac 100644 ---

[Qemu-devel] [PATCH 20/65] tcg: Add markup for output requires new register

This is the same concept as, and same markup as, the early clobber markup in gcc. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg.c | 34 ++ tcg/tcg.h | 1 + 2 files changed, 23 insertions(+), 12

[Qemu-devel] [PATCH 53/65] target-xtensa: Use clrsb helper

Cc: Max Filippov Signed-off-by: Richard Henderson --- target/xtensa/translate.c | 11 +-- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 5c719a4..5a93705 100644 ---

[Qemu-devel] [PATCH 60/65] target-i386: Use ctpop helper

Signed-off-by: Richard Henderson --- target/i386/cc_helper.c | 3 +++ target/i386/cpu.h| 1 + target/i386/ops_sse.h| 26 -- target/i386/ops_sse_header.h | 1 - target/i386/translate.c | 13 +++-- 5 files changed,

[Qemu-devel] [PATCH 45/65] tcg/i386: Fuly convert tcg_target_op_def

Use a switch instead of searching a table. Share constraints between 32-bit and 64-bit, when at all possible. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 340 +++--- 1 file changed, 198 insertions(+), 142

[Qemu-devel] [PATCH 19/65] tcg/optimize: Fold movcond 0/1 into setcond

Signed-off-by: Richard Henderson --- tcg/optimize.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index f41ed2c..9e26bb7 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1105,6 +1105,21 @@ void tcg_optimize(TCGContext

[Qemu-devel] [PATCH 47/65] tcg/i386: Allow bmi2 shiftx to have non-matching operands

Previously we could not have different constraints for different ISA levels, which prevented us from eliding the matching constraint for shifts. We do now have to make sure that the operands match for constant shifts. We can also handle some small left shifts via lea. Signed-off-by: Richard

[Qemu-devel] [PATCH 54/65] tcg: Add opcode for ctpop

The number of actual invocations of ctpop itself does not warrent an opcode, but it is very helpful for POWER7 to use in generating an expansion for ctz. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg-runtime.c| 10

[Qemu-devel] [PATCH 18/65] target-s390x: Use the new deposit and extract ops

Use the new primitives for RISBG. Signed-off-by: Richard Henderson --- target/s390x/translate.c | 34 ++ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 02bc705..6cebb7e

[Qemu-devel] [PATCH 40/65] tcg/ppc: Handle ctz and clz opcodes

Cc: qemu-...@nongnu.org Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 10 +--- tcg/ppc/tcg-target.inc.c | 67 2 files changed, 73 insertions(+), 4 deletions(-) diff --git a/tcg/ppc/tcg-target.h

[Qemu-devel] [PATCH 44/65] tcg/s390: Handle clz opcode

Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.h | 2 +- tcg/s390/tcg-target.inc.c | 36 +++- 2 files changed, 36 insertions(+), 2 deletions(-) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 3ac2dc9..22500ba

[Qemu-devel] [PATCH 49/65] tcg/i386: Rely on undefined/undocumented behaviour of BSF/BSR

The ISA manual documents the output is undefined if the input was zero. However, we document in target-i386 that the behavior of real silicon is to preserve the contents of the output register. We also mention that there are real applications that depend on this. That this is baked into silicon

[Qemu-devel] [PATCH 14/65] target-arm: Use new deposit and extract ops

Use the new primitives for UBFX and SBFX. Cc: qemu-...@nongnu.org Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 81 +- target/arm/translate.c | 37 + 2 files changed, 37 insertions(+), 81

[Qemu-devel] [PATCH 39/65] target-i386: Use clz and ctz opcodes

Signed-off-by: Richard Henderson --- target/i386/helper.h | 2 -- target/i386/int_helper.c | 11 --- target/i386/translate.c | 31 ++- 3 files changed, 14 insertions(+), 30 deletions(-) diff --git a/target/i386/helper.h

[Qemu-devel] [PATCH 43/65] tcg/mips: Handle clz opcode

Cc: Yongbok Kim Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 4 ++-- tcg/mips/tcg-target.inc.c | 34 ++ 2 files changed, 36 insertions(+), 2 deletions(-) diff --git a/tcg/mips/tcg-target.h

[Qemu-devel] [PATCH 30/65] target-mips: Use clz opcode

Cc: Yongbok Kim Signed-off-by: Richard Henderson --- target/mips/helper.h| 7 --- target/mips/op_helper.c | 22 -- target/mips/translate.c | 23 --- 3 files changed, 16 insertions(+), 36 deletions(-)

[Qemu-devel] [PATCH 13/65] target-alpha: Use deposit and extract ops

Signed-off-by: Richard Henderson --- target/alpha/translate.c | 67 ++-- 1 file changed, 42 insertions(+), 25 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 114927b..5ac2277 100644 ---

[Qemu-devel] [PATCH 35/65] target-tricore: Use clz opcode

Tested-by: Bastian Koppelmann Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/tricore/helper.h| 2 -- target/tricore/op_helper.c | 10 -- target/tricore/translate.c | 5

[Qemu-devel] [PATCH 42/65] tcg/arm: Handle ctz and clz opcodes

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 4 ++-- tcg/arm/tcg-target.inc.c | 27 +++ 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/tcg/arm/tcg-target.h

[Qemu-devel] [PATCH 24/65] tcg: Add clz and ctz opcodes

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg-runtime.c| 20 +++ tcg/README | 8 +++ tcg/aarch64/tcg-target.h | 4 ++ tcg/arm/tcg-target.h | 2 + tcg/i386/tcg-target.h| 4 ++

[Qemu-devel] [PATCH 11/65] tcg/s390: Implement field extraction opcodes

Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.h | 4 ++-- tcg/s390/tcg-target.inc.c | 11 +++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index d650a72..e9ac12e 100644 ---

[Qemu-devel] [PATCH 37/65] target-xtensa: Use clz opcode

Cc: Max Filippov Signed-off-by: Richard Henderson --- target/xtensa/helper.h| 2 -- target/xtensa/op_helper.c | 13 - target/xtensa/translate.c | 13 +++-- 3 files changed, 11 insertions(+), 17 deletions(-) diff --git

[Qemu-devel] [PATCH 31/65] target-openrisc: Use clz and ctz opcodes

Signed-off-by: Richard Henderson --- target/openrisc/helper.h | 2 -- target/openrisc/int_helper.c | 19 --- target/openrisc/translate.c | 6 -- 3 files changed, 4 insertions(+), 23 deletions(-) diff --git a/target/openrisc/helper.h

[Qemu-devel] [PATCH 09/65] tcg/ppc: Implement field extraction opcodes

Reviewed-by: David Gibson Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 4 ++-- tcg/ppc/tcg-target.inc.c | 10 ++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h

[Qemu-devel] [PATCH 27/65] target-alpha: Use the ctz and clz opcodes

Signed-off-by: Richard Henderson --- target/alpha/helper.h | 2 -- target/alpha/int_helper.c | 10 -- target/alpha/translate.c | 4 ++-- 3 files changed, 2 insertions(+), 14 deletions(-) diff --git a/target/alpha/helper.h b/target/alpha/helper.h index

[Qemu-devel] [PATCH 29/65] target-microblaze: Use clz opcode

Cc: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/helper.h| 1 - target/microblaze/op_helper.c | 5 - target/microblaze/translate.c | 2 +- 3 files changed, 1 insertion(+), 7 deletions(-) diff --git

[Qemu-devel] [PATCH 32/65] target-ppc: Use clz and ctz opcodes

Cc: qemu-...@nongnu.org Signed-off-by: Richard Henderson --- target/ppc/helper.h | 4 target/ppc/int_helper.c | 20 target/ppc/translate.c | 20 3 files changed, 16 insertions(+), 28 deletions(-) diff --git

[Qemu-devel] [PATCH 08/65] tcg/mips: Implement field extraction opcodes

Cc: Yongbok Kim Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 2 +- tcg/mips/tcg-target.inc.c | 4 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 1bcea3b..f1c3137

[Qemu-devel] [PATCH 10/65] tcg/s390: Expose host facilities to tcg-target.h

This lets us expose facilities to TCG_TARGET_HAS_* defines directly, rather than hiding behind function calls. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.h | 126 -- tcg/s390/tcg-target.inc.c | 74

[Qemu-devel] [PATCH 17/65] target-ppc: Use the new deposit and extract ops

Use the new primitives for RDWINM and RLDICL. Reviewed-by: David Gibson Signed-off-by: Richard Henderson --- target/ppc/translate.c | 35 +++ 1 file changed, 19 insertions(+), 16 deletions(-) diff --git

[Qemu-devel] [PATCH 25/65] disas/i386.c: Handle tzcnt

Signed-off-by: Richard Henderson --- disas/i386.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/disas/i386.c b/disas/i386.c index 57145d0..07f871f 100644 --- a/disas/i386.c +++ b/disas/i386.c @@ -682,6 +682,7 @@ fetch_data(struct

[Qemu-devel] [PATCH 23/65] tcg: Allow an operand to be matching or a constant

This allows an output operand to match an input operand only when the input operand needs a register. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/README | 13 + tcg/tcg.c | 63

[Qemu-devel] [PATCH 07/65] tcg/i386: Implement field extraction opcodes

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 12 +--- tcg/i386/tcg-target.inc.c | 38 ++ 2 files changed, 47 insertions(+), 3 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index

[Qemu-devel] [PATCH 15/65] target-i386: Use new deposit and extract ops

A couple of places where it was easy to identify a right-shift followed by an extract or and-with-immediate, and the obvious sign-extract from a high byte register. Acked-by: Eduardo Habkost Signed-off-by: Richard Henderson --- target/i386/translate.c |

[Qemu-devel] [PATCH 06/65] tcg/arm: Implement field extraction opcodes

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 4 ++-- tcg/arm/tcg-target.inc.c | 24 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/tcg/arm/tcg-target.h

[Qemu-devel] [PATCH 16/65] target-mips: Use the new extract op

Use extract for EXT and DEXT. Reviewed-by: Yongbok Kim Signed-off-by: Richard Henderson --- target/mips/translate.c | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index

[Qemu-devel] [PATCH 05/65] tcg/arm: Move isa detection to tcg-target.h

This allows us to use this detection within the TCG_TARGET_HAS_* macros, instead of requiring a function call into tcg-target.inc.c. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 36

[Qemu-devel] [PATCH 12/65] tcg/s390: Support deposit into zero

Since we can no longer use matching constraints, this does mean we must handle that data movement by hand. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 30 ++ 1 file changed, 26 insertions(+), 4 deletions(-) diff --git

[Qemu-devel] [PATCH 04/65] tcg/aarch64: Implement field extraction opcodes

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 8 tcg/aarch64/tcg-target.inc.c | 14 ++ 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/tcg/aarch64/tcg-target.h

[Qemu-devel] [PATCH 03/65] tcg: Add deposit_z expander

While we don't require a new opcode, it is handy to have an expander that knows the first source is zero. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 143 +++ tcg/tcg-op.h | 6 +++ 2 files changed, 149

[Qemu-devel] [PATCH v5 00/65] tcg 2.9 patch queue

This is a combination of two patch sets that have had previous revisions, as well as some new patches. I wanted to post this all together since Alex was having trouble with prerequisites. The full tree is at git://github.com/rth7680/qemu.git tcg-2.9 Changes sinve v4: * Feedback from Alex

[Qemu-devel] [PATCH 02/65] tcg: Minor adjustments to deposit expanders

Assert that len is not 0. Since we have asserted that ofs + len <= N, a later check for len == N implies that ofs == 0. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 6 -- 1 file changed, 4 insertions(+), 2

[Qemu-devel] [PATCH 01/65] tcg: Add field extraction primitives

Adds tcg_gen_extract_* and tcg_gen_sextract_* for extraction of fixed position bitfields, much like we already have for deposit. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/README | 20 ++- tcg/aarch64/tcg-target.h

[Qemu-devel] [PATCH 0/2] tcg/s390 improvements

tags/pull-tcg-20161223 for you to fetch changes up to e45d4ef6e345831c8d67a5bffe0d057efc20f4ff: tcg/s390: Remove 'R' constraint (2016-12-23 19:38:27 -0800) queued s390 host fixes

[Qemu-devel] [PATCH 2/2] tcg/s390: Remove 'R' constraint

Since R0 is reserved, we don't need a special case constraint. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 25 ++--- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c

[Qemu-devel] [PATCH 1/2] tcg/s390: Fix setcond expansion

We can't use LOAD AND TEST for unsigned data and then expect to extract the result with ADD LOGICAL WITH CARRY. Fall through to using COMPARE LOGICAL IMMEDIATE instead. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 50

[Qemu-devel] [PATCH 0/2] tcg/s390 improvements

tags/pull-tcg-20161223 for you to fetch changes up to e45d4ef6e345831c8d67a5bffe0d057efc20f4ff: tcg/s390: Remove 'R' constraint (2016-12-23 19:38:27 -0800) queued s390 host fixes

[Qemu-devel] [PATCH] The QEMU crashes since invoking qemu_thread_set_name(), the backtrace is:

From: Caoxinhua (gdb) bt #0 0x7f9a68b095d7 in __GI_raise (sig=sig@entry=6) at ../nptl/sysdeps/unix/sysv/linux/raise.c:56 #1 0x7f9a68b0acc8 in __GI_abort () at abort.c:90 #2 0x7f9a69cda389 in PAT_abort () from /usr/lib64/libuvpuserhotfix.so #3 0x7f9a69cdda0d

[Qemu-devel] [PATCH 11/21] backup: move r/w error handling code to r/w functions

It simplifies code: we do not need error_is_read parameter and retrying in backup_loop. Also, retrying for read and write are separate, so we will not reread if write failed after successfull read. Signed-off-by: Vladimir Sementsov-Ogievskiy --- block/backup.c | 141

[Qemu-devel] [PATCH v2] ps2: Fix lost scancodes by recent changes

With "ps2: use QEMU qcodes instead of scancodes", key handling was changed to qcode base. But all scancodes are not converted to new one. This adds some missing qcodes/scancodes what I found in using. [set1 and set2 are still missing, but I'm not sure what is right values yet.] Signed-off-by:

Re: [Qemu-devel] [PATCH] ps2: Fix lost scancodes by recent changes

Eric Blake writes: > On 12/23/2016 07:00 AM, OGAWA Hirofumi wrote: >> >> With "ps2: use QEMU qcodes instead of scancodes", key handling was >> changed to qcode base. But all scancodes are not converted to new one. >> >> This adds some missing qcodes what I found in using. >>

Re: [Qemu-devel] [libvirt] Cannot add iothreads label in libvirt xml configuration file

On Thu, Dec 22, 2016 at 5:01 PM, John Ferlan wrote: > > > On 12/21/2016 12:11 PM, Weiwei Jia wrote: >> Hi, >> >> I cannot add iothreads >> (https://libvirt.org/formatdomain.html#elementsIOThreadsAllocation) in >> the libvirt xml configuration file. Once I add >> "4" and other

Re: [Qemu-devel] [PATCH] ps2: Fix lost scancodes by recent changes

Hi, Hervé Poussineau writes: >> [Q_KEY_CODE_RO] = 0x73, >> +[Q_KEY_CODE_HIRAGANA] = 0x70, >> +[Q_KEY_CODE_HENKAN] = 0x79, >> +[Q_KEY_CODE_YEN] = 0x7d, >> [Q_KEY_CODE_KP_COMMA] = 0x7e, >> >> [Q_KEY_CODE__MAX] = 0, > > Can you also add the keycodes

Re: [Qemu-devel] [PATCH] ps2: Fix lost scancodes by recent changes

On 12/23/2016 07:00 AM, OGAWA Hirofumi wrote: > > With "ps2: use QEMU qcodes instead of scancodes", key handling was > changed to qcode base. But all scancodes are not converted to new one. > > This adds some missing qcodes what I found in using. > > Signed-off-by: OGAWA Hirofumi

Re: [Qemu-devel] [PATCH] ps2: Fix lost scancodes by recent changes

Le 23/12/2016 à 14:00, OGAWA Hirofumi a écrit : With "ps2: use QEMU qcodes instead of scancodes", key handling was changed to qcode base. But all scancodes are not converted to new one. This adds some missing qcodes what I found in using. Signed-off-by: OGAWA Hirofumi

Re: [Qemu-devel] [PATCH v3 0/6] trace: [tcg] Optimize per-vCPU tracing states with separate TB caches

On 12/23/2016 10:51 AM, Lluís Vilanova wrote: >> On 12/22/2016 10:35 AM, Lluís Vilanova wrote: >>> To handle both issues, this series replicates the shared physical TB cache, >>> creating a separate physical TB cache for every combination of event states >>> (those with the 'vcpu' and 'tcg'

[Qemu-devel] [PATCH 13/21] coroutine: add qemu_coroutine_add_next

Simple add coroutine to self->co_queue_wakeup. Signed-off-by: Vladimir Sementsov-Ogievskiy --- include/qemu/coroutine.h | 2 ++ util/qemu-coroutine.c| 7 +++ 2 files changed, 9 insertions(+) diff --git a/include/qemu/coroutine.h b/include/qemu/coroutine.h

[Qemu-devel] [PATCH 00/21] new backup architecture

Hi all. This is a new architecture for backup. It solves some current problems: 1. intersecting requests: for now at request start we wait for all intersecting requests, which means that a. we may wait even for unrelated to our request clusters b. not full async: if we are going to copy

[Qemu-devel] [PATCH 08/21] backup: skip unallocated clusters for full mode

In case of full backup we can skip unallocated clusters if the target disk is already zero-initialized. Signed-off-by: Vladimir Sementsov-Ogievskiy --- block/backup.c | 8 ++-- tests/qemu-iotests/055 | 2 ++ 2 files changed, 8 insertions(+), 2 deletions(-)

Re: [Qemu-devel] [PULL 24/25] target-i386: Fix eflags.TF/#DB handling of syscall/sysret insns

Paolo Bonzini writes: > From: Doug Evans > > The syscall and sysret instructions behave a bit differently: > TF is checked after the instruction completes. > This allows the o/s to disable #DB at a syscall by adding TF to FMASK. > And then when the sysret is executed the

[Qemu-devel] [Bug 1652373] [NEW] User-mode QEMU is not deterministic

Public bug reported: QEMU in user-mode (linux-user or bsd-user) has no way to get the equivalent of the "-icount" argument found in softmmu mode. It is true that some system calls in user-mode can prevent deterministic execution, but it would be very simple to patch time-related syscalls to

[Qemu-devel] [PATCH 09/21] backup: separate copy function

Signed-off-by: Vladimir Sementsov-Ogievskiy --- block/backup.c | 103 ++--- 1 file changed, 61 insertions(+), 42 deletions(-) diff --git a/block/backup.c b/block/backup.c index 4ef8daf..2c8b7ba 100644 ---

Re: [Qemu-devel] [PATCH v3 0/6] trace: [tcg] Optimize per-vCPU tracing states with separate TB caches

Richard Henderson writes: > On 12/22/2016 10:35 AM, Lluís Vilanova wrote: >> To handle both issues, this series replicates the shared physical TB cache, >> creating a separate physical TB cache for every combination of event states >> (those with the 'vcpu' and 'tcg' properties). Then, all vCPUs

[Qemu-devel] [PATCH 1/3] io: add methods to set I/O handlers on AioContext

This is in preparation for making qio_channel_yield work on AioContexts other than the main one. Signed-off-by: Paolo Bonzini --- include/io/channel.h | 42 ++ io/channel-socket.c | 16 +++- io/channel-tls.c | 12

[Qemu-devel] [PATCH 2/3] io: make qio_channel_yield aware of AioContexts

Support separate coroutines for reading and writing, and restart the coroutine on the AioContext where it was suspended on. Signed-off-by: Paolo Bonzini --- include/io/channel.h | 7 +++--- io/channel-socket.c | 12 +- io/channel.c | 62

[Qemu-devel] [RFC PATCH 0/3] io/nbd: AioContext support

This is RFC because the APIs it uses (aio_co_schedule/aio_co_wake) do not exist yet in master, but it should be enough for a first review of the QIOChannel API concepts and to give an idea of their usage. It makes qio_channel_yield aware of AioContexts by adding a new API

[Qemu-devel] [PATCH 3/3] nbd: do not block on partial reply header reads

Read the replies from a coroutine. qio_channel_yield is used so that the right coroutine is restarted automatically, eliminating the need for send_coroutine in NBDClientSession. Signed-off-by: Paolo Bonzini --- block/nbd-client.c | 108

Re: [Qemu-devel] [PATCH 07/10] aio-posix: remove walking_handlers, protecting AioHandler list with list_lock

On 21/12/2016 15:03, Paolo Bonzini wrote: > Signed-off-by: Paolo Bonzini > --- > aio-posix.c | 64 > - > 1 file changed, 38 insertions(+), 26 deletions(-) > > diff --git a/aio-posix.c b/aio-posix.c > index

[Qemu-devel] [PATCH 14/21] block: add trace point on bdrv_close_all

Signed-off-by: Vladimir Sementsov-Ogievskiy --- block.c| 1 + block/trace-events | 1 + 2 files changed, 2 insertions(+) diff --git a/block.c b/block.c index 39ddea3..3aa433b 100644 --- a/block.c +++ b/block.c @@ -2372,6 +2372,7 @@ static void

Re: [Qemu-devel] [PATCH v3 0/6] trace: [tcg] Optimize per-vCPU tracing states with separate TB caches

On 12/22/2016 10:35 AM, Lluís Vilanova wrote: > To handle both issues, this series replicates the shared physical TB cache, > creating a separate physical TB cache for every combination of event states > (those with the 'vcpu' and 'tcg' properties). Then, all vCPUs tracing the same > events will

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