Re: [Qemu-devel] [virtio-dev] Re: [RESEND Patch v1 00/37] Implementation of vhost-pci for inter-vm commucation

On 01/05/2017 03:34 PM, Wei Wang wrote: Hi Marc-André On 12/20/2016 12:43 AM, Marc-André Lureau wrote: On Mon, Dec 19, 2016 at 7:00 AM Wei Wang > wrote: This patch series implements vhost-pci, which is a point-to-point based inter-vm

Re: [Qemu-devel] [RFC]virtio-blk: add disk-name device property

Thank you for pointing out this, i'll resend the patch if my suggestion is acceptted. 2016-12-30 15:34 GMT+08:00 Cao jin : > As I know, this is not a good way to submit a patch. You need to read > the guideline first: http://wiki.qemu.org/Contribute/SubmitAPatch > > --

Re: [Qemu-devel] [RFC]virtio-blk: add disk-name device property

Thank you. -device virtio-blk-pci,serial=vdabc will solve my problem to some extent. 2017-01-04 0:29 GMT+08:00 Stefan Hajnoczi : > On Fri, Dec 30, 2016 at 10:41:35AM +0800, Junkang Fu wrote: > > From 74e913fc41ea98d1dde692175f1e3fb6729342aa Mon Sep 17 00:00:00 2001 > > From:

Re: [Qemu-devel] [RFC]virtio-blk: add disk-name device property

You got it, that's exactly what I mean.Thank you for your advise. 2017-01-04 0:53 GMT+08:00 Eric Blake : > On 12/29/2016 08:41 PM, Junkang Fu wrote: > >>From 74e913fc41ea98d1dde692175f1e3fb6729342aa Mon Sep 17 00:00:00 2001 > > From: "junkang.fjk"

Re: [Qemu-devel] [RESEND Patch v1 00/37] Implementation of vhost-pci for inter-vm commucation

Hi Marc-André On 12/20/2016 12:43 AM, Marc-André Lureau wrote: On Mon, Dec 19, 2016 at 7:00 AM Wei Wang > wrote: This patch series implements vhost-pci, which is a point-to-point based inter-vm communication solution. The QEMU

[Qemu-devel] [PATCH RFC] mem-prealloc: Reduce large guest start-up and migration time.

Using "-mem-prealloc" option for a very large guest leads to huge guest start-up and migration time. This is because with "-mem-prealloc" option qemu tries to map every guest page (create address translations), and make sure the pages are available during runtime. virsh/libvirt by default, seems

Re: [Qemu-devel] [PATCH v3 0/4] migration: skip scanning and migrating ram pages released by virtio-balloon driver.

On 1/5/2017 7:03 AM, Li, Liang Z wrote: >> Am 23.12.2016 um 03:50 schrieb Li, Liang Z: While measuring live migration performance for qemu/kvm guest, it was observed that the qemu doesn’t maintain any intelligence for the guest ram pages released by the guest balloon driver and

[Qemu-devel] uncached memory access in qtest

Hi, I’m trying to write a unit test to access a fw_cfg device via ACPI memory. When I access the memory from qtest using the readx() functions, I get the right values. If I change the contents on the host side, though, then access from the guest, the contents are unchanged. If I register a

[Qemu-devel] [PATCH V6 1/2] Add a new qmp command to start/stop replication

We can call this qmp command to start/stop replication outside of qemu. Like Xen colo need this function. Signed-off-by: Zhang Chen Signed-off-by: Wen Congyang Reviewed-by: Eric Blake Reviewed-by: Stefano Stabellini

[Qemu-devel] [PATCH V6 0/2] Add new qmp commands to suppurt Xen COLO

Xen COLO depend on qemu COLO replication function. So, We need new qmp commands for Xen to use qemu replication. Corresponding libxl patches already in xen.git. Commit ID: ed37ef1f91c20f0ab162ce60f8c38400b917fa64 COLO: introduce new API to prepare/start/do/get_error/stop replication

[Qemu-devel] [PATCH V6 2/2] Add a new qmp command to do checkpoint, query xen replication status

We can call this qmp command to do checkpoint outside of qemu. Xen colo will need this function. Signed-off-by: Zhang Chen Signed-off-by: Wen Congyang --- docs/qmp-commands.txt | 24 migration/colo.c | 17

[Qemu-devel] [PATCH v6 RESEND 08/10] tcg-mips: Add tcg unwind info

Tested-by: Aurelien Jarno Tested-by: James Hogan Tested-by: YunQiang Su Signed-off-by: Richard Henderson Signed-off-by: Jin Guojie --- tcg/mips/tcg-target.inc.c | 44

[Qemu-devel] [PATCH v6 RESEND 06/10] tcg-mips: Adjust load/store functions for mips64

tcg_out_ldst: using a generic ALIAS_PADD to avoid ifdefs tcg_out_ld: generates LD or LW tcg_out_st: generates SD or SW Tested-by: Aurelien Jarno Tested-by: James Hogan Tested-by: YunQiang Su Signed-off-by: Richard Henderson

[Qemu-devel] [PATCH v6 RESEND 01/10] tcg-mips: Move bswap code to a subroutine

Without the mips32r2 instructions to perform swapping, bswap is quite large, dominating the size of each reverse-endian qemu_ld/qemu_st operation. Create a subroutine in the prologue block. The subroutine requires extra reserved registers (TCG_TMP[2, 3]). Using these within qemu_ld means that

[Qemu-devel] [PATCH v6 RESEND 04/10] tcg-mips: Add bswap32u and bswap64

Without the mips32r2 instructions to perform swapping, bswap is quite large, dominating the size of each reverse-endian qemu_ld/qemu_st operation. Create two subroutines in the prologue block. The subroutines require extra reserved registers (TCG_TMP[2, 3]). Using these within qemu_ld means

[Qemu-devel] [PATCH v6 RESEND 02/10] tcg-mips: Add mips64 opcodes

Since the mips manual tables are in octal, reorg all of the opcodes into that format for clarity. Note that the 64-bit opcodes are as yet unused. Tested-by: Aurelien Jarno Tested-by: James Hogan Tested-by: YunQiang Su

[Qemu-devel] [PATCH v6 RESEND 07/10] tcg-mips: Adjust prologue for mips64

Take stack frame parameters out from the function body. Tested-by: Aurelien Jarno Tested-by: James Hogan Tested-by: YunQiang Su Signed-off-by: Richard Henderson Signed-off-by: Jin Guojie

[Qemu-devel] [PATCH v6 RESEND 09/10] tcg-mips: Adjust calling conventions for mips64

Tested-by: Aurelien Jarno Tested-by: James Hogan Tested-by: YunQiang Su Signed-off-by: Richard Henderson Signed-off-by: Jin Guojie --- tcg/mips/tcg-target.h | 19 +++

[Qemu-devel] [PATCH v6 RESEND 03/10] tcg-mips: Support 64-bit opcodes

Bulk patch adding 64-bit opcodes into tcg_out_op. Note that mips64 is as yet neither complete nor enabled. Tested-by: Aurelien Jarno Tested-by: James Hogan Tested-by: YunQiang Su Signed-off-by: Richard Henderson

[Qemu-devel] [PATCH v6 RESEND 00/10] tcg mips64 and mips r6 improvements

Resend for review. All modifications have been made according to Henderson's review comments, and all tests passed. Changes in v6: * Update against master(v2.8.0-rc3) * Fix two bugs according to Richard Henderson's review comments (1) mask: extend TARGET_PAGE_MASK to the proper type

[Qemu-devel] [PATCH v6 RESEND 10/10] tcg-mips: Adjust qemu_ld/st for mips64

Tested-by: Aurelien Jarno Tested-by: James Hogan Tested-by: YunQiang Su Signed-off-by: Richard Henderson Signed-off-by: Jin Guojie --- tcg/mips/tcg-target.inc.c | 203

[Qemu-devel] [PATCH v6 RESEND 05/10] tcg-mips: Adjust move functions for mips64

tcg_out_mov: using OPC_OR as most mips assemblers do; tcg_out_movi: extended to 64-bit immediate. Tested-by: Aurelien Jarno Tested-by: James Hogan Tested-by: YunQiang Su Signed-off-by: Richard Henderson

Re: [Qemu-devel] [PATCH v5 0/7] Add support for the Epson RX8900 RTC to the aspeed board

Hi, Your series failed automatic build test. Please find the testing commands and their output below. If you have docker installed, you can probably reproduce it locally. Subject: [Qemu-devel] [PATCH v5 0/7] Add support for the Epson RX8900 RTC to the aspeed board Message-id:

Re: [Qemu-devel] [PATCH v5 0/7] Add support for the Epson RX8900 RTC to the aspeed board

Hi, Your series seems to have some coding style problems. See output below for more information: Type: series Subject: [Qemu-devel] [PATCH v5 0/7] Add support for the Epson RX8900 RTC to the aspeed board Message-id: 20170105043430.3176-1-alast...@au1.ibm.com === TEST SCRIPT BEGIN ===

Re: [Qemu-devel] [PATCH v3] intel_iommu: allow dynamic switch of IOMMU region

> From: Alex Williamson [mailto:alex.william...@redhat.com] > Sent: Wednesday, January 04, 2017 5:21 AM > > On Mon, 26 Dec 2016 10:45:55 +0800 > Jason Wang wrote: > > > On 2016年12月23日 11:26, Peter Xu wrote: > > > On Thu, Dec 22, 2016 at 07:34:10PM +0800, Jason Wang wrote: >

[Qemu-devel] [Bug 1654137] [NEW] Ctrl-A b not working in 2.8.0

Public bug reported: With a recent update from 2.7.0 to 2.8.0 I have discovered that I can no longer send a "break" to the VM. Ctrl-A b is simply ignored. Other Ctrl-A sequences seem to work correctly. This is on a NetBSD amd64 system, version 7.99.53, and qemu was installed on this system

[Qemu-devel] [PATCH v5 7/7] arm: Add an RX8900 RTC to the ASpeed board

From: Alastair D'Silva Connect an RX8900 RTC to i2c12 of the AST2500 SOC at address 0x32 Signed-off-by: Alastair D'Silva Signed-off-by: Chris Smart --- hw/arm/aspeed.c | 29 + 1 file changed, 29

[Qemu-devel] [PATCH v5 6/7] tests: Test all implemented RX8900 functionality

From: Alastair D'Silva Signed-off-by: Alastair D'Silva --- tests/Makefile.include | 2 + tests/rx8900-test.c| 880 + 2 files changed, 882 insertions(+) create mode 100644 tests/rx8900-test.c

[Qemu-devel] [PATCH v5 3/7] qtest: Support setting named GPIOs

From: Alastair D'Silva Some devices change their behaviour based on the state of their input GPIO lines. This patch allows testing of the variable behaviour by providing facilities for the test to set the state of these GPIO lines. Signed-off-by: Alastair D'Silva

[Qemu-devel] [PATCH v5 5/7] hw/timer: Add Epson RX8900 RTC support

From: Alastair D'Silva This patch adds support for the Epson RX8900 I2C RTC. The following chip features are implemented: - RTC (wallclock based, ptimer 10x oversampling to pick up wallclock transitions) - Time update interrupt (per second/minute, wallclock

[Qemu-devel] [PATCH v5 1/7] arm: Uniquely name imx25 I2C buses.

From: Alastair D'Silva The imx25 chip provides 3 i2c buses, but they have all been named "i2c", which makes it difficult to predict which bus a device will be connected to when specified on the command line. This patch addresses the issue by naming the buses uniquely:

[Qemu-devel] [PATCH v5 2/7] qtest: Support named interrupts

From: Alastair D'Silva The QTest framework cannot check the state of named interrupts. This patch adds support for them. Read actions are via callbacks, which allows for pulsed interrupts to be read (the polled method used for the unnamed interrupts cannot read pulsed

[Qemu-devel] [PATCH v5 0/7] Add support for the Epson RX8900 RTC to the aspeed board

From: Alastair D'Silva This patch series adds support for the Epson RX8900 RTC to the Aspeed board. The tests use the existing imx25 infrastructure, and some minor changes have been made to uniquely identify the I2C buses. Support for named interrupts has been implemented

[Qemu-devel] [PATCH v5 4/7] qtest: Fix whitespace

From: Alastair D'Silva Fix 2 cases of incorrect indentation Signed-off-by: Alastair D'Silva --- qtest.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qtest.c b/qtest.c index a947892..143077e 100644 --- a/qtest.c +++

Re: [Qemu-devel] [PATCH v3] intel_iommu: allow dynamic switch of IOMMU region

> From: Peter Xu [mailto:pet...@redhat.com] > Sent: Thursday, January 05, 2017 11:53 AM > > > > /* Handle Translation Enable/Disable */ > > > static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool en) > > > { > > > +if (s->dmar_enabled == en) { > > > +return; > > > +} > > > +

Re: [Qemu-devel] [PATCH v3] intel_iommu: allow dynamic switch of IOMMU region

Hi, Kevin, On Thu, Jan 05, 2017 at 03:30:28AM +, Tian, Kevin wrote: > > From: Peter Xu [mailto:pet...@redhat.com] > > Sent: Thursday, December 22, 2016 5:48 PM > > > > This is preparation work to finally enabled dynamic switching ON/OFF for > > VT-d protection. The old VT-d codes is using

Re: [Qemu-devel] [PATCH v3] intel_iommu: allow dynamic switch of IOMMU region

> From: Peter Xu [mailto:pet...@redhat.com] > Sent: Thursday, December 22, 2016 5:48 PM > > This is preparation work to finally enabled dynamic switching ON/OFF for > VT-d protection. The old VT-d codes is using static IOMMU region, and > that won't satisfy vfio-pci device listeners. Is "IOMMU

Re: [Qemu-devel] [kvm-unit-tests PATCH v2 2/2] run_tests: allow run tests in parallel

On Wed, Jan 04, 2017 at 04:09:39PM +0100, Radim Krčmář wrote: > 2017-01-03 18:10+0800, Peter Xu: > > run_task.sh is getting slow. This patch is trying to make it faster by > > running the tests concurrently. > > > > We provide a new parameter "-j" for the run_tests.sh, which can be used > > to

Re: [Qemu-devel] [kvm-unit-tests PATCH 2/2] run_tests: allow run tests in parallel

On Wed, Jan 04, 2017 at 03:55:42PM +0100, Radim Krčmář wrote: [...] > >> done > >> run_task "$cmd" "$testname" "$groups" "$smp" "$kernel" "$opts" "$arch" > >> "$check" "$accel" "$timeout" & > > > > I think this might work, however it has assumption that these $cmd > > tasks are the only

Re: [Qemu-devel] [PATCH 15/54] chardev: qom-ify

On 12/12/2016 04:42 PM, Marc-André Lureau wrote: > Turn Chardev into Object. > > qemu_chr_alloc() is replaced by the qemu_chardev_new() constructor. It > will call qemu_char_open() to open/intialize the chardev with the > ChardevCommon *backend settings. > > The CharDriver::create() callback is

Re: [Qemu-devel] [PATCH v10 16/26] intel_iommu: add support for split irqchip

On Wed, Jan 04, 2017 at 11:33:36AM +0100, Jan Kiszka wrote: > On 2017-01-03 07:15, Peter Xu wrote: > > On Sun, Jun 26, 2016 at 03:27:50PM +0200, Jan Kiszka wrote: > >> On 2016-06-26 03:48, Peter Xu wrote: > >>> On Sat, Jun 25, 2016 at 05:18:40PM +0200, Jan Kiszka wrote: > On 2016-06-25 15:18,

Re: [Qemu-devel] TSC frequency configuration & invtsc migration (was Re: [PATCH 4/4] kvm: Allow migration with invtsc)

On Wed, Jan 04, 2017 at 08:26:27PM -0200, Marcelo Tosatti wrote: > On Wed, Jan 04, 2017 at 05:59:17PM -0200, Eduardo Habkost wrote: > > On Wed, Jan 04, 2017 at 11:39:16AM -0200, Eduardo Habkost wrote: > > > On Wed, Jan 04, 2017 at 09:56:56AM -0200, Marcelo Tosatti wrote: > > > > On Tue, Dec 27,

Re: [Qemu-devel] [PATCH v3 0/4] migration: skip scanning and migrating ram pages released by virtio-balloon driver.

> Am 23.12.2016 um 03:50 schrieb Li, Liang Z: > >> While measuring live migration performance for qemu/kvm guest, it was > >> observed that the qemu doesn’t maintain any intelligence for the > >> guest ram pages released by the guest balloon driver and treat such > >> pages as any other normal

Re: [Qemu-devel] [PATCH 0/4] QOM'ify work for ppc

On Thu, Jan 05, 2017 at 08:53:07AM +0800, 赵小强 wrote: > Ok！ > > Just one more comment： > After check the code flow, It's clear that the initialized memory > region must be add to address space by calling > memory_region_add_subregion in platform code before it can be > accessed. Yes.. but I don't

Re: [Qemu-devel] [PATCH 4/6] prep: QOM'ify System I/O

On Wed, Jan 04, 2017 at 10:17:10PM +0100, Hervé Poussineau wrote: > Le 03/01/2017 à 05:45, David Gibson a écrit : > > On Thu, Dec 29, 2016 at 11:12:14PM +0100, Hervé Poussineau wrote: > > > Part of the functionality is copied from hw/ppc/prep.c. > > > Also add support for board

Re: [Qemu-devel] [PATCH 0/4] QOM'ify work for ppc

Ok！ Just one more comment： After check the code flow, It's clear that the initialized memory region must be add to address space by calling memory_region_add_subregion in platform code before it can be accessed. Best wishes ！ > 在 2017年1月5日，08:20，David Gibson 写道：

[Qemu-devel] [PATCH RESEND 6/6] crypto: add AEAD algorithms testcases

This patch add some AEAD algorithms testcases Signed-off-by: Longpeng(Mike) --- tests/Makefile.include | 2 + tests/test-crypto-aead.c | 357 +++ 2 files changed, 359 insertions(+) create mode 100644 tests/test-crypto-aead.c

[Qemu-devel] [PATCH RESEND 3/6] crypto: implement nettle-backed AEAD algorithms

This patch add nettle-backed AEAD algorithms Signed-off-by: Longpeng(Mike) --- crypto/aead-nettle.c | 174 --- 1 file changed, 167 insertions(+), 7 deletions(-) diff --git a/crypto/aead-nettle.c b/crypto/aead-nettle.c index

[Qemu-devel] [PATCH RESEND 5/6] crypto: implement other common funcs for AEAD algorithms

If currently gcrypt/nettle doesn't support AEAD alg, then we should implement some no-op funcs. Signed-off-by: Longpeng(Mike) --- crypto/aead.c | 44 ++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/crypto/aead.c

[Qemu-devel] [PATCH RESEND 1/6] configure: add CONFIG_GCRYPT/NETTLE_AEAD item

This item will be used for gcrypt/nettle backed AEAD algorithms. It's hardly to decide which version of gcrypt/nettle started supporting AEAD algorithms, but it's easily for us to making a test in configure to know whether current gcrypt/nettle support AEAD. Signed-off-by: Longpeng(Mike)

[Qemu-devel] [PATCH RESEND 4/6] crypto: implement gcrypt-backed AEAD algorithms

This patch add gcrypt-backed AEAD algorithms support Signed-off-by: Longpeng(Mike) --- crypto/aead-gcrypt.c | 173 +-- 1 file changed, 167 insertions(+), 6 deletions(-) diff --git a/crypto/aead-gcrypt.c

[Qemu-devel] [PATCH RESEND 2/6] crypto: add AEAD algorithms framework

This patch introduce AEAD algorithms framework. We currently plan to support six basic AEAD algorithms, ccm(aes128/192/256) and gcm(aes128/192/256), so we need to add ccm/gcm mode in qapi/crypto.json simultaneously. Signed-off-by: Longpeng(Mike) --- crypto/Makefile.objs |

[Qemu-devel] [PATCH RESEND 0/6] crypto:add AEAD algorithms support

Since QEMU has been supported cryptodev, so it is necessary to support more crypto algorithms(i.e. hmac,aead) in QEMU backend. We have already added HMAC support, and this patchset adds AEAD algos support. --- Hi Daniel, Would you please review this patchset? AEAD is also an important

Re: [Qemu-devel] [PATCH 0/4] QOM'ify work for ppc

On Wed, Jan 04, 2017 at 05:04:02PM +, Peter Maydell wrote: > On 4 January 2017 at 03:28, David Gibson wrote: > > On Tue, Jan 03, 2017 at 10:02:21PM +0800, 赵小强 wrote: > >> Hi，david： > >> > >>To my understanding，what must be put in the realize function is > >>

Re: [Qemu-devel] [PATCH v4 7/8] tests: Test all implemented RX8900 functionality

On Wed, 2017-01-04 at 16:44 +1030, Andrew Jeffery wrote: > Hi Alastair, > > Again, small comments below. > > On Thu, 2016-12-15 at 16:48 +1100, Alastair D'Silva wrote: > > > From: Alastair D'Silva > > > Signed-off-by: Alastair D'Silva > > > > ---

Re: [Qemu-devel] [PATCH v5] qqq: module for synchronizing with a simulation

Hi, Your series failed automatic build test. Please find the testing commands and their output below. If you have docker installed, you can probably reproduce it locally. Type: series Message-id: 1483568308-28868-1-git-send-email-nutar...@ornl.gov Subject: [Qemu-devel] [PATCH v5] qqq: module for

Re: [Qemu-devel] TSC frequency configuration & invtsc migration (was Re: [PATCH 4/4] kvm: Allow migration with invtsc)

On Wed, Jan 04, 2017 at 05:59:17PM -0200, Eduardo Habkost wrote: > On Wed, Jan 04, 2017 at 11:39:16AM -0200, Eduardo Habkost wrote: > > On Wed, Jan 04, 2017 at 09:56:56AM -0200, Marcelo Tosatti wrote: > > > On Tue, Dec 27, 2016 at 05:21:20PM -0200, Eduardo Habkost wrote: > > > > Instead of

Re: [Qemu-devel] [PATCH 14/54] gtk: overwrite the console.c char driver

On 12/12/2016 04:42 PM, Marc-André Lureau wrote: > Instead of registering a vc handler to allocate the Gtk VC Chardev, > overwrite the console.c char driver. > > A later patch, when switching to QOM, will register a default console vc > QOM class if none has been registered before. > >

Re: [Qemu-devel] [PATCH v5] qqq: module for synchronizing with a simulation

Hi, Your series seems to have some coding style problems. See output below for more information: Type: series Message-id: 1483568308-28868-1-git-send-email-nutar...@ornl.gov Subject: [Qemu-devel] [PATCH v5] qqq: module for synchronizing with a simulation === TEST SCRIPT BEGIN === #!/bin/bash

[Qemu-devel] [PATCH v5] qqq: module for synchronizing with a simulation

This patch adds an interface for pacing the execution of QEMU to match an external simulation clock. Its aim is to permit QEMU to be used as a module within a larger simulation system. Signed-off-by: James J. Nutaro --- Makefile.target | 3 + cpus.c

[Qemu-devel] [PATCH v4] [i.MX] fix CS handling during SPI access.

The i.MX SPI device was not de-asserting the CS line at the end of memory access. This triggered a SIGSEGV in Qemu when the sabrelite emulator was acessing a SPI flash memory. Whith this path the CS signal is correctly asserted and deasserted arround memory access. Assertion level is now based

Re: [Qemu-devel] [PATCH 13/54] char: use error_report()

On 12/12/2016 04:42 PM, Marc-André Lureau wrote: > Prefer error_report() over fprintf(stderr..) > > Signed-off-by: Marc-André Lureau > --- > qemu-char.c | 27 +++ > 1 file changed, 15 insertions(+), 12 deletions(-) > > @@ -4130,17 +4130,20

Re: [Qemu-devel] [PATCH 12/54] spice-char: improve error reporting

On 12/12/2016 04:42 PM, Marc-André Lureau wrote: > Set errp to report errors up. > > Use error_report() to give hints about parameters on the right monitor, > instead of a direct fprintf() call. > > Signed-off-by: Marc-André Lureau > --- > spice-qemu-char.c | 29

Re: [Qemu-devel] [PATCH 11/54] char: rename TCPChardev and NetChardev

On 12/12/2016 04:42 PM, Marc-André Lureau wrote: > Rename the types to follow the name of the chardev kind. > - socket: TCPChardev -> SocketChardev > - udp: NetChardev -> UdpChardev > > Signed-off-by: Marc-André Lureau > --- > qemu-char.c | 74 >

Re: [Qemu-devel] [PATCH v3] [i.MX] fix CS handling during SPI access.

Le 04/01/2017 à 21:56, mar.krzeminski a écrit : W dniu 03.01.2017 o 21:35, Jean-Christophe Dubois pisze: The i.MX SPI device was not de-asserting the CS line at the end of memory access. This triggered a SIGSEGV in Qemu when the sabrelite emulator was acessing a SPI flash memory. Whit

Re: [Qemu-devel] [PATCH 00/54] WIP: chardev: qom-ify

On 01/04/2017 03:20 PM, Marc-André Lureau wrote: > Hi > > On Mon, Jan 2, 2017 at 11:27 AM Paolo Bonzini wrote: > >> >> >> On 12/12/2016 23:42, Marc-André Lureau wrote: >>> >>> Note: this series has been tested with Linux and cross-building with >>> mingw. It mostly breaks

Re: [Qemu-devel] [PATCH] win32: fix main-loop busy loop on socket/fd event

Hi On Wed, Jan 4, 2017 at 10:23 PM Paolo Bonzini wrote: > > > Paolo suggested to me on irc to call event_notifier_test_and_clear() > > after select() >0 from aio-win32.c's aio_prepare. Unfortunately, not all > > fds associated with ctx->notifiers are in AIO fd handlers set.

Re: [Qemu-devel] [PATCH 10/54] char: rename CharDriverState Chardev

On 12/12/2016 04:42 PM, Marc-André Lureau wrote: > Uniformify chardev type name. "Uniformify" - cute :) I might have written: Pick a uniform chardev type name. instead of inventing a word, but you're call on whether to keep it. > > Signed-off-by: Marc-André Lureau

Re: [Qemu-devel] [PATCH 2/3] io: make qio_channel_yield aware of AioContexts

> > @@ -84,8 +83,8 @@ struct QIOChannel { > > unsigned int features; /* bitmask of QIOChannelFeatures */ > > char *name; > > AioContext *ctx; > > -QIOChannelRestart *read_coroutine; > > -QIOChannelRestart *write_coroutine; > > +Coroutine *read_coroutine; > > +

Re: [Qemu-devel] [PATCH] win32: fix main-loop busy loop on socket/fd event

> Paolo suggested to me on irc to call event_notifier_test_and_clear() > after select() >0 from aio-win32.c's aio_prepare. Unfortunately, not all > fds associated with ctx->notifiers are in AIO fd handlers set. > (qemu_set_nonblock() in util/oslib-win32.c calls qemu_fd_register()). That makes

Re: [Qemu-devel] [PATCH 00/54] WIP: chardev: qom-ify

Hi On Mon, Jan 2, 2017 at 11:27 AM Paolo Bonzini wrote: > > > On 12/12/2016 23:42, Marc-André Lureau wrote: > > > > Note: this series has been tested with Linux and cross-building with > > mingw. It mostly breaks on other platforms, > > What breaks exactly? > > Not much

Re: [Qemu-devel] [PATCH 4/6] prep: QOM'ify System I/O

Le 03/01/2017 à 05:45, David Gibson a écrit : On Thu, Dec 29, 2016 at 11:12:14PM +0100, Hervé Poussineau wrote: Part of the functionality is copied from hw/ppc/prep.c. Also add support for board identification/equipment registers. Signed-off-by: Hervé Poussineau ---

Re: [Qemu-devel] [PATCH 09/54] bt: use qemu_chr_alloc()

On 12/12/2016 04:42 PM, Marc-André Lureau wrote: > Use common allocator for CharDriverState. > > Rename the now untouched parent field. > > Signed-off-by: Marc-André Lureau > --- > hw/bt/hci-csr.c | 19 +-- > 1 file changed, 13 insertions(+), 6

Re: [Qemu-devel] [PATCH 08/54] char: allocate CharDriverState as a single object

On 01/04/2017 03:09 PM, Marc-André Lureau wrote: > Hi > > On Wed, Jan 4, 2017 at 9:26 PM Eric Blake wrote: > >> On 12/12/2016 04:42 PM, Marc-André Lureau wrote: >>> Use a single allocation for CharDriverState, this avoids extra >>> allocations & pointers, and is a step

Re: [Qemu-devel] [PATCH] fsl_etsec: Fix Tx BD ring wrapping handling

On Sun, Dec 25, 2016 at 8:12 PM, Jason Wang wrote: > > > On 2016年12月21日 05:11, Andrey Smirnov wrote: >> >> Current code that handles Tx buffer desciprtor ring scanning employs the >> following algorithm: >> >> 1. Restore current buffer descriptor pointer from TBPTRn

Re: [Qemu-devel] [PATCH v3] ps2: Fix lost scancodes by recent changes

Hervé Poussineau writes: > Le 04/01/2017 à 09:50, Gerd Hoffmann a écrit : >> On Mi, 2016-12-28 at 04:55 +0900, OGAWA Hirofumi wrote: >>> With "ps2: use QEMU qcodes instead of scancodes", key handling was >>> changed to qcode base. But all scancodes are not converted to new

Re: [Qemu-devel] [PATCH 08/54] char: allocate CharDriverState as a single object

Hi On Wed, Jan 4, 2017 at 9:26 PM Eric Blake wrote: > On 12/12/2016 04:42 PM, Marc-André Lureau wrote: > > Use a single allocation for CharDriverState, this avoids extra > > allocations & pointers, and is a step towards more object-oriented > > CharDriver. > > > > Gtk console

[Qemu-devel] [PATCH] win32: fix main-loop busy loop on socket/fd event

Commit 05e514b1d4d5bd4209e2c8bbc76ff05c85a235f3 introduced an AIO context optimization to avoid calling event_notifier_test_and_clear() on ctx->notifier. On Windows, the same notifier is being used to wakeup the wait on socket events (see commit d3385eb448e38f828c78f8f68ec5d79c66a58b5d). The

[Qemu-devel] [PATCH] Revert "win32: don't run subprocess tests on Mingw32 platform"

This reverts commit 7ad9339e372fcd12d584684d7f52ac259604a4f4. The error "Failed to execute helper program (No such file or directory)" is due to broken glib installation, missing windows gspawn helpers. Signed-off-by: Marc-André Lureau --- configure | 2 +- 1 file

Re: [Qemu-devel] [PATCH v3] [i.MX] fix CS handling during SPI access.

W dniu 03.01.2017 o 21:35, Jean-Christophe Dubois pisze: The i.MX SPI device was not de-asserting the CS line at the end of memory access. This triggered a SIGSEGV in Qemu when the sabrelite emulator was acessing a SPI flash memory. Whit this path the CS signal is correctly asserted and

Re: [Qemu-devel] Speed menu for GTK interfaace

Hi, > > We already have "pause" in gtk, adding a "throttle" item next to it > > looks reasonable to me. I don't think it is that useful to have 10% > > steps in there, you probably never throttle 10% in practice. It's > > probably more useful to have something like "throttle -> off / 50% / >

Re: [Qemu-devel] NBD handshake may block qemu main thread when socket delays or has packet loss

On 01/04/2017 02:45 AM, Fangyi (C) wrote: > As we all know, socket is in blocking mode when nbd is negotiating > with the other end. If the network is poor because of delay or packet > loss, socket read or write will return very slowly. The mainloop events > won't be handled in time util nbd

[Qemu-devel] [PATCH v2] ui/gtk: Fix mouse wheel on 3.4.0 or later

On 3.4.0 or later, send GDK_SCROLL_SMOOTH event, instead of GDK_SCROLL_UP/DOWN. This fixes it by converting any smooth scroll to up/down. (I.e. without smooth support) Signed-off-by: OGAWA Hirofumi --- ui/gtk.c | 13 + 1 file changed, 13

Re: [Qemu-devel] [PATCH V5 2/2] Add a new qmp command to do checkpoint, query xen replication status

On 12/27/2016 03:38 AM, Zhang Chen wrote: > We can call this qmp command to do checkpoint outside of qemu. > Like Xen colo need this function. That sentence is awkward; maybe: Xen colo will need this function. > > Signed-off-by: Zhang Chen > Signed-off-by: Wen

Re: [Qemu-devel] [PATCH] ui/gtk: Fix mouse wheel on 3.4.0 or later

Gerd Hoffmann writes: >> +#if GTK_CHECK_VERSION(3, 4, 0) >> +} else if (scroll->direction == GDK_SCROLL_SMOOTH) { >> +gdouble delta_x, delta_y; >> +if (!gdk_event_get_scroll_deltas((GdkEvent*)scroll, _x, >> _y)) >> +return TRUE; >> +if

Re: [Qemu-devel] [PATCH] linux-user: always start with parallel_cpus set to true

On 01/04/2017 12:22 PM, Laurent Vivier wrote: Yes, it's a good idea, but is it really expensive to always enable the parallel_cpus flag? It is somewhat expensive when the host does support the atomics being used; it is very expensive if the host does not. Of course the common case is x86_64

Re: [Qemu-devel] [PATCH 08/54] char: allocate CharDriverState as a single object

On 12/12/2016 04:42 PM, Marc-André Lureau wrote: > Use a single allocation for CharDriverState, this avoids extra > allocations & pointers, and is a step towards more object-oriented > CharDriver. > > Gtk console is a bit peculiar, gd_vc_chr_set_echo Truncated paragraph? > Signed-off-by:

Re: [Qemu-devel] [PATCH] linux-user: always start with parallel_cpus set to true

Le 04/01/2017 à 19:39, Alex Bennée a écrit : > > Laurent Vivier writes: > >> We always need real atomics, as we can have shared memory between >> processes. >> >> A good test case is the example from futex(2), futex_demo.c: >> >> the use case is >> >> mmap(...); >>

Re: [Qemu-devel] [PATCH] linux-user: always start with parallel_cpus set to true

Le 04/01/2017 à 20:35, Richard Henderson a écrit : > On 12/28/2016 09:37 AM, Laurent Vivier wrote: >> the use case is >> >> mmap(...); >> fork(); > > While true, we can notice that mmap contains MAP_SHARED, and trigger it > then. Similarly for shmat. Yes, it's a good idea, but is it

Re: [Qemu-devel] drive_mirror to nbd with tls ?

On 01/04/2017 01:34 PM, Alexandre DERUMIER wrote: > Hi, > > I'm currently trying to implemented drive_mirror to nbd with tls. > > It's working fine without tls, but with tls enabled on target, > > I don't known how to pass tls-creds to drive_mirror nbd uri ? Unfortunately, drive-mirror is

[Qemu-devel] [PATCH 3/4] hw/virtio: fix Link Control Register for PCI Express virtio devices

Make several Link Control Register flags writable to conform with the PCI Express spec. Signed-off-by: Marcel Apfelbaum --- hw/pci/pcie.c | 14 ++ hw/virtio/virtio-pci.c | 3 +++ include/hw/pci/pcie.h | 3 +++ 3 files changed, 20 insertions(+) diff

[Qemu-devel] [PATCH 2/4] hw/virtio: fix error enabling flags in Device Control register

When the virtio devices are PCI Express, make error-enabling flags writable to respect the PCIe spec. Signed-off-by: Marcel Apfelbaum --- hw/virtio/virtio-pci.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index

[Qemu-devel] TSC frequency configuration & invtsc migration (was Re: [PATCH 4/4] kvm: Allow migration with invtsc)

On Wed, Jan 04, 2017 at 11:39:16AM -0200, Eduardo Habkost wrote: > On Wed, Jan 04, 2017 at 09:56:56AM -0200, Marcelo Tosatti wrote: > > On Tue, Dec 27, 2016 at 05:21:20PM -0200, Eduardo Habkost wrote: > > > Instead of blocking migration on the source when invtsc is > > > enabled, rely on the

Re: [Qemu-devel] New Year's starting over ... bsd-user

On 4 January 2017 at 18:32, Alex Bennée wrote: > Apart from syscall mapping and backend calls to the BSD ABI what > differences are there between the two user-mode implementations? I'm a bit wary of sharing code between the two just because I think we'd end up breaking

[Qemu-devel] [PATCH 4/4] hw/virtio: fix Power Management Control Register for PCI Express virtio devices

Make Power Management State flag writable to conform with the PCI Express spec. Signed-off-by: Marcel Apfelbaum --- hw/virtio/virtio-pci.c | 5 + include/hw/pci/pcie.h | 2 ++ 2 files changed, 7 insertions(+) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c

[Qemu-devel] [PATCH 1/4] hw/pcie: fix Extended Configuration Space for devices with no Extended Capabilities

Absence of any Extended Capabilities is required to be indicated by an Extended Capability header with a Capability ID of h, a Capability Version of 0h, and a Next Capability Offset of 000h. Instead of inserting a 'NULL' capability is simpler to mark the start of the Extended Configuration

[Qemu-devel] [PATCH 0/4] hw/virtio: fix several PCI Express compliance issues

Fix a few issues found while running WHQL tests: - Assertion 1F27399E-30B9-44BC-8908-D6E6F3836212: FAILED. Enhanced Capability Header register of the PCI Express Enhanced Capabilities Absent Indicator table must be read-only . Solved in patch 1/4 - Assertion

Re: [Qemu-devel] [PATCH] linux-user: always start with parallel_cpus set to true

On 12/28/2016 09:37 AM, Laurent Vivier wrote: the use case is mmap(...); fork(); While true, we can notice that mmap contains MAP_SHARED, and trigger it then. Similarly for shmat. r~

[Qemu-devel] drive_mirror to nbd with tls ?

Hi, I'm currently trying to implemented drive_mirror to nbd with tls. It's working fine without tls, but with tls enabled on target, I don't known how to pass tls-creds to drive_mirror nbd uri ? I don't see any option in nbd uri schema. Currently, I have this error "TLS negotiation

Re: [Qemu-devel] New Year's starting over ... bsd-user

On 01/04/17 11:32, Alex Bennée wrote: > > Sean Bruno writes: > >> I'm pondering where to start with getting FreeBSD's bsd-user code into >> shape so it could actually be reviewed and accepted now that its sort of >> working again (signal handling fixed finally). > > Also

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