[Qemu-devel] [PATCH] m68k: Remove PCI and USB from config file

None of the ColdFire boards that we currently support has a PCI or USB bus (and AFAIK the upcoming q800 machine does not support PCI and USB either), so we do not need these settings the config file. Signed-off-by: Thomas Huth --- default-configs/m68k-softmmu.mak | 2 -- 1

Re: [Qemu-devel] [PATCH v3 2/2] intel_iommu: allow migration

On Fri, Jan 06, 2017 at 03:05:47PM +0800, Jason Wang wrote: > > > On 2017年01月06日 12:06, Peter Xu wrote: > >IOMMU needs to be migrated before all the PCI devices (in case there are > >devices that will request for address translation). So marking it with a > >priority higher than the default

Re: [Qemu-devel] [PATCH v3 2/2] intel_iommu: allow migration

On 2017年01月06日 12:06, Peter Xu wrote: IOMMU needs to be migrated before all the PCI devices (in case there are devices that will request for address translation). So marking it with a priority higher than the default (which PCI devices and other belong). Migration framework handled the rest.

[Qemu-devel] [PATCH v1 14/14] target-ppc: Add xsxsigqp instructions

xsxsigqp: VSX Scalar Extract Significand Quad Precision Signed-off-by: Nikunj A Dadhania --- target/ppc/translate/vsx-impl.inc.c | 29 + target/ppc/translate/vsx-ops.inc.c | 1 + 2 files changed, 30 insertions(+) diff --git

[Qemu-devel] [PATCH v1 13/14] target-ppc: Add xsxsigdp instruction

xsxsigdp: VSX Scalar Extract Significand Dual Precision Signed-off-by: Nikunj A Dadhania --- target/ppc/translate/vsx-impl.inc.c | 29 + target/ppc/translate/vsx-ops.inc.c | 1 + 2 files changed, 30 insertions(+) diff --git

Re: [Qemu-devel] [RFC] pxb: Restrict to x86

On 01/06/2017 08:13 AM, Marcel Apfelbaum wrote: On 01/06/2017 07:04 AM, David Gibson wrote: The PCI Expander Bridge (PXB) device is essentially a hack to allow different PCIe devices to be assigned to different NUMA nodes on x86. Each PXB is sort-of a separate PCI host bridge, except that its

[Qemu-devel] [PATCH v1 09/14] target-ppc: Add xscvdpqp instruction

From: Bharata B Rao xscvdpqp: VSX Scalar Convert Double-Precision format to Quad-Precision format Signed-off-by: Bharata B Rao Signed-off-by: Nikunj A Dadhania --- target/ppc/fpu_helper.c

[Qemu-devel] [PATCH v1 10/14] target-ppc: Add xscvqpdp instruction

From: Bharata B Rao xscvqpdp: VSX Scalar round & Convert Quad-Precision format to Double-Precision format Signed-off-by: Bharata B Rao Signed-off-by: Nikunj A Dadhania --- target/ppc/fpu_helper.c

[Qemu-devel] [PATCH v1 12/14] target-ppc: Add xsxexpqp instruction

xsxexpqp: VSX Scalar Extract Exponent Quad Precision Signed-off-by: Nikunj A Dadhania --- target/ppc/translate/vsx-impl.inc.c | 15 +++ target/ppc/translate/vsx-ops.inc.c | 1 + 2 files changed, 16 insertions(+) diff --git

[Qemu-devel] [PATCH v1 07/14] target-ppc: Add xscvdphp, xscvhpdp

From: Bharata B Rao xscvdphp: VSX Scalar round & Convert Double-Precision format to Half-Precision format xscvhpdp: VSX Scalar Convert Half-Precision format to Double-Precision format Signed-off-by: Bharata B Rao

[Qemu-devel] [PATCH v1 05/14] target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64

From: Bharata B Rao Since helper_compute_fprf() works on float64 argument, rename it to helper_compute_fprf_float64(). Also use a macro to generate helper_compute_fprf_float64() so that float128 version of the same helper can be introduced easily later.

[Qemu-devel] [PATCH v1 06/14] target-ppc: Add xsaddqp instructions

From: Bharata B Rao xsaddqp: VSX Scalar Add Quad-Precision Signed-off-by: Bharata B Rao Signed-off-by: Nikunj A Dadhania --- target/ppc/fpu_helper.c | 36

[Qemu-devel] [PATCH v1 11/14] target-ppc: Add xsxexpdp instruction

xsxexpdp: VSX Scalar Extract Exponent Dual Precision Signed-off-by: Nikunj A Dadhania --- target/ppc/translate/vsx-impl.inc.c | 13 + target/ppc/translate/vsx-ops.inc.c | 4 2 files changed, 17 insertions(+) diff --git

[Qemu-devel] [PATCH v1 03/14] target-ppc: Use float64 arg in helper_compute_fprf()

From: Bharata B Rao Use float64 argument instead of unit64_t in helper_compute_fprf() This allows code in helper_compute_fprf() to be reused later to work with float128 argument too. Signed-off-by: Bharata B Rao Signed-off-by: Nikunj A

[Qemu-devel] [PATCH v1 04/14] target-ppc: Replace isden by float64_is_zero_or_denormal

From: Bharata B Rao Replace isden() by float64_is_zero_or_denormal() so that code in helper_compute_fprf() can be reused to work with float128 argument. Signed-off-by: Bharata B Rao Signed-off-by: Nikunj A Dadhania

[Qemu-devel] [PATCH v1 08/14] target-ppc: Use correct precision for FPRF setting

From: Bharata B Rao Use correct FP precision when setting FPRF in FP conversion helpers instead of always assuming float64 precision. Signed-off-by: Bharata B Rao Signed-off-by: Nikunj A Dadhania ---

[Qemu-devel] [PATCH v1 00/14] POWER9 TCG enablements - part10

This series contains 11 new instructions for POWER9 ISA3.0 VSX Vector Insert/Extract Word VSX Scalar Extract Exponent/Significand VSX Scalar Convert VSX Scalar Add QP Various float related improvements Changelog: v0: Rebase and update reviewed-by Bharata B Rao (8):

[Qemu-devel] [PATCH v1 01/14] target-ppc: Add xxextractuw instruction

xxextractuw: VSX Vector Extract Unsigned Word Signed-off-by: Nikunj A Dadhania --- target/ppc/helper.h | 1 + target/ppc/int_helper.c | 26 ++ target/ppc/translate/vsx-impl.inc.c | 30 ++

[Qemu-devel] [PATCH v1 02/14] target-ppc: Add xxinsertw instruction

xxinsertw: VSX Vector Insert Word Signed-off-by: Nikunj A Dadhania --- target/ppc/helper.h | 1 + target/ppc/int_helper.c | 25 + target/ppc/translate/vsx-impl.inc.c | 5 +++-- target/ppc/translate/vsx-ops.inc.c |

Re: [Qemu-devel] [RFC] pxb: Restrict to x86

On 01/06/2017 07:04 AM, David Gibson wrote: The PCI Expander Bridge (PXB) device is essentially a hack to allow different PCIe devices to be assigned to different NUMA nodes on x86. Each PXB is sort-of a separate PCI host bridge, except that its config space is shared with the config space of

Re: [Qemu-devel] [PATCH 03/14] target-ppc: Use float64 arg in helper_compute_fprf()

David Gibson writes: > [ Unknown signature status ] > On Thu, Jan 05, 2017 at 04:56:08PM +0530, Nikunj A Dadhania wrote: >> From: Bharata B Rao >> >> Use float64 argument instead of unit64_t in helper_compute_fprf() >> This allows code

Re: [Qemu-devel] [PATCH 00/14] POWER9 TCG enablements - part10

David Gibson writes: > [ Unknown signature status ] > On Thu, Jan 05, 2017 at 04:56:05PM +0530, Nikunj A Dadhania wrote: >> This series contains 11 new instructions for POWER9 ISA3.0 >> VSX Vector Insert/Extract Word >> VSX Scalar Extract

[Qemu-devel] [RFC] pxb: Restrict to x86

The PCI Expander Bridge (PXB) device is essentially a hack to allow different PCIe devices to be assigned to different NUMA nodes on x86. Each PXB is sort-of a separate PCI host bridge, except that its config space is shared with the config space of the main PCI host bridge, rather than being

Re: [Qemu-devel] [PATCH v2 0/4] QOM'ify work for ppc

On Fri, Jan 06, 2017 at 08:26:24AM +0800, xiaoqiang zhao wrote: > This is some QOM'ify work relate with ppc. > See each commit message for details. > > changes in v2: > remove empty function 'spapr_vio_bridge_init' Applied to ppc-for-2.9, thanks. -- David Gibson| I'll

Re: [Qemu-devel] [PATCH 03/14] target-ppc: Use float64 arg in helper_compute_fprf()

On Fri, Jan 06, 2017 at 09:01:17AM +1100, David Gibson wrote: > On Thu, Jan 05, 2017 at 04:56:08PM +0530, Nikunj A Dadhania wrote: > > From: Bharata B Rao > > > > Use float64 argument instead of unit64_t in helper_compute_fprf() > > This allows code in

Re: [Qemu-devel] [PATCH v2 2/2] intel_iommu: allow migration

On 2017年01月06日 11:08, Peter Xu wrote: IOMMU needs to be migrated before all the PCI devices (in case there are devices that will request for address translation). So marking it with a priority higher than the default (which PCI devices and other belong). Migration framework handled the rest.

Re: [Qemu-devel] [Qemu-ppc] [PATCH 02/14] target-ppc: Add xxinsertw instruction

On 6 January 2017 at 03:27, David Gibson wrote: > On Thu, Jan 05, 2017 at 04:56:07PM +0530, Nikunj A Dadhania wrote: >> xxinsertw: VSX Vector Insert Word > > I think this still has problems with out of bounds values. > >> >> Signed-off-by: Nikunj A Dadhania

[Qemu-devel] [PATCH v3 1/2] migration: allow to prioritize save state entries

During migration, save state entries are saved/loaded without a specific order - we just traverse the savevm_state.handlers list and do it one by one. This might not be enough. There are requirements that we need to load specific device's vmstate first before others. For example, VT-d IOMMU

[Qemu-devel] [PATCH v3 2/2] intel_iommu: allow migration

IOMMU needs to be migrated before all the PCI devices (in case there are devices that will request for address translation). So marking it with a priority higher than the default (which PCI devices and other belong). Migration framework handled the rest. Signed-off-by: Peter Xu

[Qemu-devel] [PATCH v3 0/2] VT-d migration support

This series enables VT-d IOMMU migration. v3: - save/load for csr [Jason] v2: - remove SaveStateEntry.priority, let priority store only in one place, which is VMStateDescription. Meanwhile, provide another helper to fetch the priority. - add enum MigrationPriority to unify the ordering,

Re: [Qemu-devel] [PATCH v2 2/2] intel_iommu: allow migration

On Fri, Jan 06, 2017 at 11:42:30AM +0800, Jason Wang wrote: > > > On 2017年01月06日 11:08, Peter Xu wrote: > >IOMMU needs to be migrated before all the PCI devices (in case there are > >devices that will request for address translation). So marking it with a > >priority higher than the default

Re: [Qemu-devel] [Qemu-trivial] [PATCH for-2.9] docs: Fix description of the sentence

On 2017年01月06日 11:33, Zhang Chen wrote: Ping Applied to -net. Thanks

[Qemu-devel] [kvm-unit-tests PATCH v3 2/2] run_tests: allow run tests in parallel

run_task.sh is getting slow. This patch is trying to make it faster by running the tests concurrently. We provide a new parameter "-j" for the run_tests.sh, which can be used to specify how many run queues we want for the tests. Default queue length is 1, which is the old behavior. Quick test on

Re: [Qemu-devel] [Qemu-trivial] [PATCH for-2.9] docs: Fix description of the sentence

Ping On 12/26/2016 03:26 PM, Zhang Chen wrote: Hi~~ Jason. Can you pick up this patch? Thanks Zhang Chen On 12/08/2016 09:32 AM, Zhang Chen wrote: On 12/07/2016 09:30 PM, Stefan Hajnoczi wrote: On Wed, Dec 07, 2016 at 10:01:49AM +0100, Laurent Vivier wrote: Le 07/12/2016 à 09:58,

[Qemu-devel] [kvm-unit-tests PATCH v3 0/2] run_tests: support concurrent test execution

v3: - better handling for ctrl-c during run_tests.sh [Radim] v2: - patch 1: do per-test logging in all cases - patch 2: throw away task.bash, instead, take Radim's suggestion to use jobs run_tests.sh is getting slower. Maybe it's time to let it run faster. An obvious issue is that, we were

[Qemu-devel] [PULL 1/3] record/replay: add network support

From: Pavel Dovgalyuk This patch adds support of recording and replaying network packets in irount rr mode. Record and replay for network interactions is performed with the network filter. Each backend must have its own instance of the replay filter as follows:

[Qemu-devel] [kvm-unit-tests PATCH v3 1/2] run_tests: put logs into per-test file

We were using test.log before to keep all the test logs. This patch creates one log file per test case under logs/ directory with name "TESTNAME.log". A new file global.bash is added to store global informations. Signed-off-by: Peter Xu --- Makefile | 4 ++--

[Qemu-devel] [PULL 0/3] Net patches

The following changes since commit e92fbc753df4fab9ee524b5ea07a51bee8b6bae4: Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2017-01-05 12:44:23 +) are available in the git repository at: https://github.com/jasowang/qemu.git tags/net-pull-request

[Qemu-devel] [PULL 2/3] rtl8139: correctly handle PHY reset

From: Hervé Poussineau According to datasheet: "[Bit 15 of Basic Mode Control Register] sets the status and control registers of the PHY (register 0062-0074) in a default state. This bit is self-clearing. 1 = software reset; 0 = normal operation." This fixes the netcard

[Qemu-devel] [PULL 3/3] fsl_etsec: Fix Tx BD ring wrapping handling

From: Andrey Smirnov Current code that handles Tx buffer desciprtor ring scanning employs the following algorithm: 1. Restore current buffer descriptor pointer from TBPTRn 2. Process current descriptor 3. If current descriptor has BD_WRAP flag

Re: [Qemu-devel] [kvm-unit-tests PATCH v2 2/2] run_tests: allow run tests in parallel

On Thu, Jan 05, 2017 at 08:44:02PM +0100, Radim Krčmář wrote: [...] > > Anyway, IMHO squashing you suggestion of "trap exit SIGINT" at the > > entry of for_each_unittest() is an acceptable solution - it works in > > all cases. > > Seems like the best solution at this time ... > We actually want

[Qemu-devel] [PATCH v2 2/2] intel_iommu: allow migration

IOMMU needs to be migrated before all the PCI devices (in case there are devices that will request for address translation). So marking it with a priority higher than the default (which PCI devices and other belong). Migration framework handled the rest. Signed-off-by: Peter Xu

[Qemu-devel] [PATCH v2 0/2] VT-d migration support

This series enables VT-d IOMMU migration. v2: - remove SaveStateEntry.priority, let priority store only in one place, which is VMStateDescription. Meanwhile, provide another helper to fetch the priority. - add enum MigrationPriority to unify the ordering, rather than use magic numbers like

[Qemu-devel] [PATCH v2 1/2] migration: allow to prioritize save state entries

During migration, save state entries are saved/loaded without a specific order - we just traverse the savevm_state.handlers list and do it one by one. This might not be enough. There are requirements that we need to load specific device's vmstate first before others. For example, VT-d IOMMU

Re: [Qemu-devel] [PATCH v3] fsl_etsec: Fix Tx BD ring wrapping handling

On 2017年01月06日 04:26, Andrey Smirnov wrote: Current code that handles Tx buffer desciprtor ring scanning employs the following algorithm: 1. Restore current buffer descriptor pointer from TBPTRn 2. Process current descriptor 3. If current descriptor has BD_WRAP flag

Re: [Qemu-devel] [PATCH 1/2] migration: allow to prioritize save state entries

On Thu, Jan 05, 2017 at 12:49:59PM +, Dr. David Alan Gilbert wrote: > * Peter Xu (pet...@redhat.com) wrote: > > During migration, save state entries are saved/loaded without a specific > > order - we just traverse the savevm_state.handlers list and do it one by > > one. This might not be

[Qemu-devel] [PATCH v2] hw/display: QOM'ify g364fb.c

Drop the old Sysbus init and use instance_init and DeviceClass::realize instead Signed-off-by: xiaoqiang zhao --- hw/display/g364fb.c | 40 +--- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/hw/display/g364fb.c

Re: [Qemu-devel] [PATCH] hw/display: QOM'ify g364fb.c

在 2017年1月5日，23:10，Peter Maydell 写道： >> sysbus_init_irq(sbd, >irq); >>sysbus_init_mmio(sbd, >mem_ctrl); >>sysbus_init_mmio(sbd, >mem_vram); > > This means we call sysbus_init_mmio() on the MemoryRegion*s > before we have initialized them. That seems like a bad

[Qemu-devel] [PATCH v2 3/4] hw/ppc: QOM'ify ppce500_spin.c

Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao --- hw/ppc/ppce500_spin.c | 18 -- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index cf958a9e00..958536f6c6

[Qemu-devel] [PATCH v2 1/4] hw/gpio: QOM'ify mpc8xxx.c

* Drop the old SysBus init function and use instance_init * Change mpc8xxx_gpio_reset to a DeviceClass::reset function Signed-off-by: xiaoqiang zhao --- hw/gpio/mpc8xxx.c | 20 +++- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git

[Qemu-devel] [PATCH v2 0/4] QOM'ify work for ppc

This is some QOM'ify work relate with ppc. See each commit message for details. changes in v2: remove empty function 'spapr_vio_bridge_init' xiaoqiang zhao (4): hw/gpio: QOM'ify mpc8xxx.c hw/ppc: QOM'ify e500.c hw/ppc: QOM'ify ppce500_spin.c hw/ppc: QOM'ify spapr_vio.c

[Qemu-devel] [PATCH v2 4/4] hw/ppc: QOM'ify spapr_vio.c

Drop the old and empty SysBus init Signed-off-by: xiaoqiang zhao --- hw/ppc/spapr_vio.c | 10 -- 1 file changed, 10 deletions(-) diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c index cc1e09c568..8bfc5f971f 100644 --- a/hw/ppc/spapr_vio.c +++

[Qemu-devel] [PATCH v2 2/4] hw/ppc: QOM'ify e500.c

Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao --- hw/ppc/e500.c | 17 - 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index cf8b122afe..792bd79d39 100644 ---

Re: [Qemu-devel] [PATCH v2 4/4] prep: add IBM RS/6000 7020 (40p) machine emulation

On Thu, Jan 05, 2017 at 10:56:57PM +0100, Hervé Poussineau wrote: > Machine supports both Open Hack'Ware and OpenBIOS. > Open Hack'Ware is the default because OpenBIOS is currently unable to boot > PReP boot partitions or PReP kernels. > > Signed-off-by: Hervé Poussineau >

Re: [Qemu-devel] [PATCH 0/6] CAN bus support for QEMU (SJA1000 PCI so far)

Hi, Your series seems to have some coding style problems. See output below for more information: Message-id: cover.1483655893.git.p...@cmp.felk.cvut.cz Subject: [Qemu-devel] [PATCH 0/6] CAN bus support for QEMU (SJA1000 PCI so far) Type: series === TEST SCRIPT BEGIN === #!/bin/bash BASE=base

Re: [Qemu-devel] [PATCH v2 2/4] prep: add PReP System I/O

On Thu, Jan 05, 2017 at 10:56:55PM +0100, Hervé Poussineau wrote: > This device is a partial duplicate of System I/O device available in > hw/ppc/prep.c > This new one doesn't have all the Motorola-specific registers. > The old one should be deprecated and removed with the 'prep' machine. > >

Re: [Qemu-devel] [PATCH v2 3/4] prep: add IBM RS/6000 7020 (40p) memory controller

On Thu, Jan 05, 2017 at 10:56:56PM +0100, Hervé Poussineau wrote: > Signed-off-by: Hervé Poussineau Reviewed-by: David Gibson > --- > default-configs/ppc-softmmu.mak | 1 + > hw/ppc/Makefile.objs| 1 + > hw/ppc/rs6000_mc.c

[Qemu-devel] [PATCH 4/6] Fixed IRQ problem for CAN device can_pcm3680_pci.

From: Deniz Eren --- hw/can/can_pcm3680_pci.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/hw/can/can_pcm3680_pci.c b/hw/can/can_pcm3680_pci.c index 6e5c9f2..9d8d3f7 100644 --- a/hw/can/can_pcm3680_pci.c +++ b/hw/can/can_pcm3680_pci.c @@ -61,6 +61,7 @@

[Qemu-devel] [PATCH 6/6] CAN bus MIOe-3680 PCI (dual SJA1000 channel) emulation added.

From: Deniz Eren --- hw/can/Makefile.objs | 1 + hw/can/can_mioe3680_pci.c | 325 ++ 2 files changed, 326 insertions(+) create mode 100644 hw/can/can_mioe3680_pci.c diff --git a/hw/can/Makefile.objs

[Qemu-devel] [PATCH 3/6] CAN bus PCM-3680I PCI (dual SJA1000 channel) emulation added.

From: Deniz Eren --- hw/can/Makefile.objs | 1 + hw/can/can_pcm3680_pci.c | 315 +++ 2 files changed, 316 insertions(+) create mode 100644 hw/can/can_pcm3680_pci.c diff --git a/hw/can/Makefile.objs b/hw/can/Makefile.objs

[Qemu-devel] [PATCH 5/6] Minor clean-up of can_pcm3680_pci.

From: Deniz Eren --- hw/can/can_pcm3680_pci.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/can/can_pcm3680_pci.c b/hw/can/can_pcm3680_pci.c index 9d8d3f7..1134960 100644 --- a/hw/can/can_pcm3680_pci.c +++ b/hw/can/can_pcm3680_pci.c @@

[Qemu-devel] [PATCH 2/6] CAN bus Kvaser PCI CAN-S (single SJA1000 channel) emulation added.

From: Pavel Pisa Signed-off-by: Pavel Pisa --- hw/can/Makefile.objs| 1 + hw/can/can_kvaser_pci.c | 364 2 files changed, 365 insertions(+) create mode 100644 hw/can/can_kvaser_pci.c diff

[Qemu-devel] [PATCH 1/6] CAN bus simple SJA1000 PCI card emulation for QEMU

From: Pavel Pisa The work is based on Jin Yang GSoC 2013 work funded by Google and mentored in frame of RTEMS project GSoC slot donated to QEMU. Rewritten for QEMU-2.0+ versions and architecture cleanup by Pavel Pisa (Czech Technical University in Prague). The core

[Qemu-devel] [PATCH 0/6] CAN bus support for QEMU (SJA1000 PCI so far)

From: Pavel Pisa Hello Stefan and others, I have found some time over holidays. I have rebased patches and checked that the CAN bus emulation works with QEMU-2.8 release. The work has been started by Jin Yang in the frame of GSoC 2013 slot contributed by RTEMS project

[Qemu-devel] qemu-softmmu aborted with "Bad ram pointer"

Hello, debugging XIP kernel running directly from CFI FLASH I've got to a point where QEMU aborts with the message "Bad ram pointer 0xbb4". It turns out that that happens when QEMU tries to translate code from FLASH immediately after the kernel has written to the FLASH address range: writing to

Re: [Qemu-devel] [PATCH 8/8] io: introduce a DNS resolver API

On 01/05/2017 10:03 AM, Daniel P. Berrange wrote: > Currently DNS resolution is done automatically as part > of the creation of a QIOChannelSocket object instance. > This works ok for network clients where you just end > up a single network socket, but for servers, the results > of DNS resolution

[Qemu-devel] [scripts] default shell/perl locations

I don't suppose it would be possible to have configure check/change the interpreter path for scripts so that operating systems that don't have /usr/bin/perl for example, would work out of the box? sean signature.asc Description: OpenPGP digital signature

Re: [Qemu-devel] [PATCH v2 0/5] qtest: enable several tests for ppc64

On Thu, Jan 05, 2017 at 04:29:43PM +0100, Laurent Vivier wrote: > This series enables some tests existing for i386 and which > can also work on ppc64. > > VGA tests and netfilter tests are trivial, but ivshmem test > needs to enable the SPAPR PCI framework. We also fix a bug > in qpci_map() for

Re: [Qemu-devel] [PATCH 00/14] POWER9 TCG enablements - part10

On Thu, Jan 05, 2017 at 04:56:05PM +0530, Nikunj A Dadhania wrote: > This series contains 11 new instructions for POWER9 ISA3.0 > VSX Vector Insert/Extract Word > VSX Scalar Extract Exponent/Significand > VSX Scalar Convert > VSX Scalar Add QP > Various float related

Re: [Qemu-devel] [PATCH 04/14] target-ppc: Replace isden by float64_is_zero_or_denormal

On Thu, Jan 05, 2017 at 04:56:09PM +0530, Nikunj A Dadhania wrote: > From: Bharata B Rao > > Replace isden() by float64_is_zero_or_denormal() so that code in > helper_compute_fprf() can be reused to work with float128 argument. > > Signed-off-by: Bharata B Rao

Re: [Qemu-devel] [PATCH 02/14] target-ppc: Add xxinsertw instruction

On Thu, Jan 05, 2017 at 04:56:07PM +0530, Nikunj A Dadhania wrote: > xxinsertw: VSX Vector Insert Word I think this still has problems with out of bounds values. > > Signed-off-by: Nikunj A Dadhania > --- > target-ppc/helper.h | 1 + >

Re: [Qemu-devel] [PATCH 03/14] target-ppc: Use float64 arg in helper_compute_fprf()

On Thu, Jan 05, 2017 at 04:56:08PM +0530, Nikunj A Dadhania wrote: > From: Bharata B Rao > > Use float64 argument instead of unit64_t in helper_compute_fprf() > This allows code in helper_compute_fprf() to be reused later to > work with float128 argument too. > >

Re: [Qemu-devel] [PATCH 7/8] io: remove Error parameter from QIOTask thread worker

On 01/05/2017 10:03 AM, Daniel P. Berrange wrote: > Now that task objects have a directly associated error, > there's no need for an an Error **errp parameter to > the QIOTask thread worker function. It already has a > QIOTask object, so can directly set the error on it. > > Signed-off-by: Daniel

[Qemu-devel] [PATCH v2 3/4] prep: add IBM RS/6000 7020 (40p) memory controller

Signed-off-by: Hervé Poussineau --- default-configs/ppc-softmmu.mak | 1 + hw/ppc/Makefile.objs| 1 + hw/ppc/rs6000_mc.c | 232 hw/ppc/trace-events | 7 ++ 4 files changed, 241 insertions(+)

[Qemu-devel] [PATCH v2 1/4] prep: do not use global variable to access nvram

Signed-off-by: Hervé Poussineau --- hw/ppc/prep.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index 054af1e..9fb89d3 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -339,13 +339,13 @@ static PortioList

[Qemu-devel] [PATCH v2 2/4] prep: add PReP System I/O

This device is a partial duplicate of System I/O device available in hw/ppc/prep.c This new one doesn't have all the Motorola-specific registers. The old one should be deprecated and removed with the 'prep' machine. Partial documentation available at

Re: [Qemu-devel] [PATCH 6/8] io: change the QIOTask callback signature

On 01/05/2017 10:03 AM, Daniel P. Berrange wrote: > Currently the QIOTaskFunc signature takes an Object * for > the source, and an Error * for any error. We also need to > be able to provide a result pointer. Rather than continue > to add parameters to QIOTaskFunc, remove the existing > ones and

[Qemu-devel] [PATCH v2 4/4] prep: add IBM RS/6000 7020 (40p) machine emulation

Machine supports both Open Hack'Ware and OpenBIOS. Open Hack'Ware is the default because OpenBIOS is currently unable to boot PReP boot partitions or PReP kernels. Signed-off-by: Hervé Poussineau --- default-configs/ppc-softmmu.mak | 1 + hw/ppc/prep.c

Re: [Qemu-devel] [Qemu-ppc] [PATCH v4 1/6] target-ppc: Implement unsigned quadword left/right shift and unit tests

On 01/05/2017 03:45 PM, jos...@linux.vnet.ibm.com wrote: >> >>> +{ 0, 0, 0ULL, 0, 200, false }, >> >> If you are going to support shifts larger than 127, your testsuite >> should include a shift of a non-zero number. Also, if you are going to >> implicitly truncate the shift value into

Re: [Qemu-devel] [Qemu-ppc] [PATCH v4 1/6] target-ppc: Implement unsigned quadword left/right shift and unit tests

Hello Eric, Thank you very much for your review. Please, read my responses and questions below. Happy 2017. On Tue, Jan 03, 2017 at 09:20:37AM -0600, Eric Blake wrote: > On 12/19/2016 10:47 AM, Jose Ricardo Ziviani wrote: > > This commit implements functions to right and left shifts and the > >

[Qemu-devel] [PATCH v2 0/4] ppc: add a IBM 40p machine (RS/6000, PReP)

Hi, This patchset adds the emulation of the IBM RS/6000 7020 (40p). The real machine is able to run AIX (up to 4.3.3), Windows NT (up to 4.0 SP1), the beta of OS/2 PowerPC, Solaris, Linux, NetBSD/PReP ... I've tested current emulation with Open Hack'Ware, OpenBIOS and official firmware.

Re: [Qemu-devel] [PATCH] [m25p80] Abort in case we overrun the internal data buffer

Le 05/01/2017 à 21:51, Peter Maydell a écrit : So what would be the preferred behavior? Asserting (and ending Qemu) Resetting (and hiding the misbehavior). If the guest can trigger this behaviour, then we should not assert or abort or otherwise cause QEMU to exit. The preferred behaviour is:

Re: [Qemu-devel] [PATCH v5 3/4] Plumb the HAXM-based hardware acceleration support

On 05/01/2017 15:01, Paolo Bonzini wrote: > > > On 05/01/2017 14:50, Vincent Palatin wrote: >> Sorry I missed it. >> I move it to qemu_cpu_kick() as asked in the Darwin patch. >> >>> Apart from the above change, can you check if there are some less >>> heavyeight methods to force an exit? I

Re: [Qemu-devel] [PATCH 5/8] io: add ability to associate an error with a task

On 01/05/2017 10:03 AM, Daniel P. Berrange wrote: > Currently when a task fails, the error is never explicitly > associated with the task object, it is just passed along > through the completion callback. This adds ability to s/adds/adds the/ > explicitly associate an error with the task. > >

Re: [Qemu-devel] [PATCH 4/6] prep: QOM'ify System I/O

Le 05/01/2017 à 01:41, David Gibson a écrit : On Wed, Jan 04, 2017 at 10:17:10PM +0100, Hervé Poussineau wrote: Le 03/01/2017 à 05:45, David Gibson a écrit : On Thu, Dec 29, 2016 at 11:12:14PM +0100, Hervé Poussineau wrote: Part of the functionality is copied from hw/ppc/prep.c. Also add

Re: [Qemu-devel] [PATCH] [m25p80] Abort in case we overrun the internal data buffer

On 5 January 2017 at 20:18, Jean-Christophe DUBOIS wrote: > Le 05/01/2017 à 21:04, mar.krzeminski a écrit : >> Peter Maydell wrote: >>> If these are "can't happen unless some other part of QEMU >>> is buggy" cases, then we can just assert(): >>> (If they're "could happen if

Re: [Qemu-devel] [PATCH 4/8] io: add ability to associate an opaque "result" with with a task

On 01/05/2017 10:03 AM, Daniel P. Berrange wrote: > Currently there is no data associated with a successful > task completion. This adds an opaque pointer to the task > to store an arbitrary result. > > Signed-off-by: Daniel P. Berrange > --- > include/io/task.h | 27

Re: [Qemu-devel] [kvm-unit-tests PATCH 2/2] run_tests: allow run tests in parallel

2017-01-05 10:35+0800, Peter Xu: > On Wed, Jan 04, 2017 at 03:55:42PM +0100, Radim Krčmář wrote: >> > I didn't notice the "-n" parameter for "wait", otherwise I won't >> > bother using SIGUSR1 at all. :) >> >> (Btw. why couldn't you use SIGCHLD?) > > My understanding: > > SIGCHLD is used by

Re: [Qemu-devel] [PATCH 3/8] io: fix typo in docs for QIOTask

On 01/05/2017 10:03 AM, Daniel P. Berrange wrote: > The GDestroyNotify parameter is already a pointer, so does > not need a '*' suffix on the type. > > Signed-off-by: Daniel P. Berrange > --- > include/io/task.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-)

[Qemu-devel] [PATCH v3] fsl_etsec: Fix Tx BD ring wrapping handling

Current code that handles Tx buffer desciprtor ring scanning employs the following algorithm: 1. Restore current buffer descriptor pointer from TBPTRn 2. Process current descriptor 3. If current descriptor has BD_WRAP flag set set current descriptor pointer to

Re: [Qemu-devel] [PATCH] [m25p80] Abort in case we overrun the internal data buffer

Le 05/01/2017 à 21:04, mar.krzeminski a écrit : Hi Peter, W dniu 05.01.2017 o 19:38, Peter Maydell pisze: On 3 January 2017 at 21:17, Jean-Christophe Dubois wrote: Signed-off-by: Jean-Christophe Dubois --- hw/block/m25p80.c | 19

Re: [Qemu-devel] [PATCH] [m25p80] Abort in case we overrun the internal data buffer

Hi Peter, W dniu 05.01.2017 o 19:38, Peter Maydell pisze: On 3 January 2017 at 21:17, Jean-Christophe Dubois wrote: Signed-off-by: Jean-Christophe Dubois --- hw/block/m25p80.c | 19 +-- 1 file changed, 17 insertions(+), 2

Re: [Qemu-devel] [PATCH v2] fsl_etsec: Fix Tx BD ring wrapping handling

Hi, Your series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20170105195349.28031-1-andrew.smir...@gmail.com Subject: [Qemu-devel] [PATCH v2] fsl_etsec: Fix Tx BD ring wrapping handling === TEST SCRIPT BEGIN === #!/bin/bash BASE=base

[Qemu-devel] [PATCH v2] fsl_etsec: Fix Tx BD ring wrapping handling

Current code that handles Tx buffer desciprtor ring scanning employs the following algorithm: 1. Restore current buffer descriptor pointer from TBPTRn 2. Process current descriptor 3. If current descriptor has BD_WRAP flag set set current descriptor pointer to

Re: [Qemu-devel] [PATCH] vexpress fix flash device-width

Am 05.01.2017 um 19:32 schrieb Peter Maydell: On 22 December 2016 at 14:02, David Engraf wrote: The current implementation uses width = 4 and device-width = 2 for the flash configuration. When using u-boot or Linux, the flash is detected as 32 x 16 bit, thus the sector

Re: [Qemu-devel] [kvm-unit-tests PATCH v2 2/2] run_tests: allow run tests in parallel

2017-01-05 11:07+0800, Peter Xu: > On Wed, Jan 04, 2017 at 04:09:39PM +0100, Radim Krčmář wrote: >> 2017-01-03 18:10+0800, Peter Xu: >> > run_task.sh is getting slow. This patch is trying to make it faster by >> > running the tests concurrently. >> > >> > We provide a new parameter "-j" for the

Re: [Qemu-devel] [PATCH] [m25p80] Abort in case we overrun the internal data buffer

On 3 January 2017 at 21:17, Jean-Christophe Dubois wrote: > Signed-off-by: Jean-Christophe Dubois > --- > hw/block/m25p80.c | 19 +-- > 1 file changed, 17 insertions(+), 2 deletions(-) > > diff --git a/hw/block/m25p80.c

Re: [Qemu-devel] [PATCH] vexpress fix flash device-width

On 22 December 2016 at 14:02, David Engraf wrote: > The current implementation uses width = 4 and device-width = 2 for the flash > configuration. When using u-boot or Linux, the flash is detected as 32 x 16 > bit, thus the sector size is doubled to 512 KB. When u-boot

Re: [Qemu-devel] [PATCH v6 06/17] qapi: rework qapi Exception

Hi - Original Message - > Marc-André Lureau writes: > > > Use a base class QAPIError, and QAPIParseError for parser errors and > > QAPISemError for semantic errors, suggested by Markus Armbruster. > > > > Signed-off-by: Marc-André Lureau

Re: [Qemu-devel] [PATCH v2 6/6] ARM BE32 watchpoint fix.

On 7 December 2016 at 14:49, Julian Brown wrote: > In BE32 mode, sub-word size watchpoints can fail to trigger because the > address of the access is adjusted in the opcode helpers before being > compared with the watchpoint registers. This patch reverses the address >

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