Use the softfloat api for fused multiply-add. As we are using the fused
multiply-add, the intermediate result for setting VXISI is not
available.
Signed-off-by: Nikunj A Dadhania
---
target/ppc/fpu_helper.c | 201 +++-
1 file changed, 29 insertions(+),
On 03/01/2017 06:14 AM, Jason Wang wrote:
On 2017年03月01日 11:23, Michael S. Tsirkin wrote:
On Wed, Mar 01, 2017 at 10:36:35AM +0800, Peter Xu wrote:
On Tue, Feb 28, 2017 at 04:42:25PM +0200, Marcel Apfelbaum wrote:
On 02/24/2017 06:29 AM, Peter Xu wrote:
Intel vIOMMU devices are created with
> From: Konrad Rzeszutek Wilk [mailto:konrad.w...@oracle.com]
> Sent: Wednesday, March 01, 2017 6:07 AM
>
> On Wed, Nov 30, 2016 at 08:49:24AM +, Liu, Yi L wrote:
> > What's changed from v2:
> > a) Detailed feature description
> > b) refine description in "Address translation in virtual SVM"
>
Eric Blake writes:
> On 02/28/2017 03:27 PM, Markus Armbruster wrote:
>> Additionally permit non-negative integers as key components. A
>> dictionary's keys must either be all integers or none. If all keys
>> are integers, convert the dictionary to a list. The set of keys must
>> be [0,N].
>>
getrampagesize() returns the largest supported page size and mainly
used to know if huge pages are enabled.
However is implemented in target-ppc/kvm.c and not available
in TCG or other architectures.
This renames and moves gethugepagesize() to mmap-alloc.c where
fd-based analog of it is already i
From: Mike Nawrocki
This patch extends support for the `dump-guest-memory` command to the
32-bit PowerPC architecture. It relies on the assumption that a 64-bit
guest will not dump a 32-bit core file (and vice versa).
[dwg: I suspect this patch won't cover all cases, in particular a
32-bit machi
From: Cédric Le Goater
Also introduce a xics_icp_get() helper to simplify the changes.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics.c | 32 ++--
hw/intc/xics_spapr.c| 17 +
hw/ppc/spapr.c | 2 +-
On Tue, 2017-02-28 at 14:19 +1100, David Gibson wrote:
> On Tue, Feb 28, 2017 at 01:25:17PM +1100, Suraj Jitindar Singh wrote:
> >
> > On Tue, 2017-02-28 at 11:28 +1100, David Gibson wrote:
> > >
> > > s/HTP/HPT/ in subject line.
> > >
> > >
> > > On Thu, Feb 23, 2017 at 05:00:01PM +1100, Sam B
From: Cédric Le Goater
This is not used anymore.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
hw/intc/xics.c| 8
hw/ppc/spapr.c| 1 -
include/hw/ppc/xics.h | 2 --
3 files changed, 11 deletions(-)
diff --git a/hw/intc/xic
From: Cédric Le Goater
The reset of the ICS objects is currently handled by XICS but this can
be done for each individual ICS. This also reduces the use of the XICS
list of ICS.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
hw/intc/xics.c | 5 -
From: Cédric Le Goater
'ICPState *' variables are currently named 'ss'. This is confusing, so
let's give them an appropriate name: 'icp'.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics.c | 154 ++---
hw/intc/xic
From: Cédric Le Goater
Let's add two new handlers for ICPs. One is to get an ICP object from
a server number and a second is to resend the irqs when needed.
The icp_resend() handler is a temporary workaround needed by the
ics-simple post_load() handler. It will be removed when the post_load
port
From: Cédric Le Goater
The reset of the ICP objects is currently handled by XICS but this can
be done for each individual ICP.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics.c | 18 --
hw/ppc/spapr.c | 1 +
2 files changed, 1 insertion(+), 18 del
From: Cédric Le Goater
It provides a better monitor output of the ICP and ICS objects, else
the objects are printed out of order.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics.c| 20 ++--
hw/ppc/spapr.c| 17 +
incl
From: Cédric Le Goater
The cpu_setup() handler is currently under the XICSState class but it
really belongs under ICPState as it is setting up an individual vCPU.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics.c| 8 +++
hw/intc/xics_kvm.c| 58 +++
From: Cédric Le Goater
The XICSState classes are not used anymore. They have now been fully
deprecated by the XICSFabric QOM interface. Do the cleanups.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics.c | 11 ---
hw/intc/xics_kvm.c | 13 ---
From: Cédric Le Goater
Today, the ICP (Interrupt Controller Presenter) objects are created by
the 'nr_servers' property handler of the XICS object and a class
handler. They are realized in the XICS object realize routine.
Let's simplify the process by creating the ICP objects along with the
XICS
From: Cédric Le Goater
Today, the ICS (Interrupt Controller Source) object is created and
realized by the init and realize routines of the XICS object, but some
of the parameters are only known at the machine level.
These parameters are passed from the sPAPR machine to the ICS object
in a rather
From: Cédric Le Goater
The ICS object uses a post_load() handler which is implicitly relying
on the fact that the internal state of the ICS and ICP objects has
been restored but this is not guaranteed. So, let's move the code
under the post_load() handler of the machine where we know the objects
From: Cédric Le Goater
The kernel ICP file descriptor is the only reason behind the
KVMXICSState class and it's in the way of more cleanups. Let's make it
a static for the moment and move forward.
If this is problem, we could use an attribute under the sPAPR machine
later on.
Signed-off-by: Céd
From: Cédric Le Goater
Add 'ics_get' and 'ics_resend' handlers to the sPAPR machine. These
are relatively simple for a single ICS.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
hw/intc/xics.c| 2 +-
hw/ppc/spapr.c| 18 +
From: Cédric Le Goater
There is nothing left related to the XICS object in the realize
functions of the KVMXICSState and XICSState class. So adapt the
interfaces to call these routines directly from the sPAPR machine init
sequence.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
--
CPUPPCState includes fields htab_base and htab_mask which store the base
address (GPA) and size (as a mask) of the guest's hashed page table (HPT).
These are set when the SDR1 register is updated.
Keeping these in sync with the SDR1 is actually a little bit fiddly, and
probably not useful for perf
From: Cédric Le Goater
spapr_dt_xics() only needs the number of servers to build the device
tree nodes. Let's change the routine interface to reflect that.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics_spapr.c | 4 ++--
hw/ppc/spapr.c| 2 +-
include/hw/
From: Nikunj A Dadhania
Add helper_div_compute_ov() in the int_helper for updating the overflow
flags.
For Divide Word:
SO, OV, and OV32 bits reflects overflow of the 32-bit result
For Divide DoubleWord:
SO, OV, and OV32 bits reflects overflow of the 64-bit result
Signed-off-by: Nikunj A Dadha
From: Cédric Le Goater
The cpu_setup() handler currently takes a 'XICSState *' argument to
grab the kernel ICP file descriptor. This interface can be simplified
by using the 'xics' backlink of the ICP object.
This change is also required by subsequent patches which makes use of
the QOM interface
The pseries machine type implements the behaviour of a PAPR compliant
hypervisor, without actually executing such a hypervisor on the virtual
CPU. To do this we need some hooks in the CPU code to make hypervisor
facilities get redirected to the machine instead of emulated internally.
For hypercal
From: Cédric Le Goater
A list of ICS objects was introduced under the XICS object for the
PowerNV machine but, for the sPAPR machine, it brings extra complexity
as there is only a single ICS. To simplify the code, let's add the ICS
pointer under the sPAPR machine and try to reduce the use of this
From: Cédric Le Goater
This is, again, to reduce the use of the list of ICS objects. Let's
make each individual ICS and ICP object an InterruptStatsProvider and
remove this same interface from XICSState.
The InterruptStatsProvider will be moved at the machine level after
the XICS cleanups are co
From: Cédric Le Goater
This is the last step to remove the XICSState abstraction and have the
machine hold all the objects related to interrupts : ICSs and ICPs.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 17 -
include/hw/ppc/spapr
Currently xics - the component of the IBM POWER interrupt controller
representing the overall interrupt fabric / architecture is
represented as a descendent of SysBusDevice. However, this is not
really correct - the xics presents nothing in MMIO space so it should
be an "unattached" device in the
From: Greg Kurz
Since commit 1d2d974244c6 "spapr_pci: enumerate and add PCI device tree", QEMU
populates the PCI device tree in the opposite order compared to SLOF.
Before 1d2d974244c6:
Populating /pci@8002000
00 (D) : 1af4 1000virtio [ net ]
From: Nikunj A Dadhania
For Multiply Word:
SO, OV, and OV32 bits reflects overflow of the 32-bit result
For Multiply DoubleWord:
SO, OV, and OV32 bits reflects overflow of the 64-bit result
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
targe
From: Cédric Le Goater
Also change the ICPState 'xics' backlink to be a XICSFabric, this
removes the need of using qdev_get_machine() to get the QOM interface
in some of the routines.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics.c| 20 +++---
From: Cédric Le Goater
It is not used anymore now that we have the QOM interface for XICS.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
hw/intc/xics.c| 12
include/hw/ppc/xics.h | 1 -
2 files changed, 13 deletions(-)
diff -
From: Nikunj A Dadhania
mcrxrx: Move to CR from XER Extended
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/translate.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc
Accesses to the hashed page table (HPT) are complicated by the fact that
the HPT could be in one of three places:
1) Within guest memory - when we're emulating a full guest CPU at the
hardware level (e.g. powernv, mac99, g3beige)
2) Within qemu, but outside guest memory - when we're emu
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
hw/intc/xics.c | 5 +++--
hw/ppc/spapr_events.c | 6 +++---
hw/ppc/spapr_pci.c | 2 +-
include/hw/pci-host/spapr.h | 2 +-
include/hw/ppc/spapr_vio.h |
SDR_64_HTABORG, which indicates the bits of the SDR1 register to use for
the base of a 64-bit machine's hashed page table (HPT) isn't correct. It
includes the top 46 bits of the register, but in fact the top 4 bits must
be zero (according to the ISA v2.07). No actual implementation has
supported
When a 'pseries' guest is running with KVM-HV, the guest's hashed page
table (HPT) is stored within the host kernel, so it is not directly
accessible to qemu. Most of the time, qemu doesn't need to access it:
we're using the hardware MMU, and KVM itself implements the guest
hypercalls for manipula
From: Cédric Le Goater
This interface provides two simple handlers. One is to get an ICS
(Interrupt Source Controller) object from an irq number and a second
to resend the irqs when needed.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
hw/intc/xics
From: Nikunj A Dadhania
* SO and OV reflects overflow of the 64-bit result in 64-bit mode and
overflow of the low-order 32-bit result in 32-bit mode
* OV32 reflects overflow of the low-order 32-bit independent of the mode
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
tar
From: Nikunj A Dadhania
POWER ISA 3.0 adds CA32 and OV32 status in 64-bit mode. Add the flags
and corresponding defines.
Moreover, CA32 is updated when CA is updated and OV32 is updated when OV
is updated.
Arithmetic instructions:
* Addition and Substractions:
addic, addic., subfic
From: Nikunj A Dadhania
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/translate.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 16f422f..d4d9941 100644
From: Nikunj A Dadhania
Adds routine to compute ca32 - gen_op_arith_compute_ca32
For 64-bit mode use the compute ca32 routine. While for 32-bit mode, CA
and CA32 will have same value.
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/
From: Suraj Jitindar Singh
The function ppc_hash64_set_sdr1 basically checked the htabsize and set an
error if it was too big, otherwise it just stored the value in SPR_SDR1.
Given that the only function which calls ppc_hash64_set_sdr1() is
ppc_store_sdr1(), why not handle the checking in ppc_st
From: Laurent Vivier
To allow QEMU to add PCI entries in device tree,
we must have a more exhaustive list of PCI class IDs.
This patch synchronizes as much as possible with
pci_ids.h and add some missing IDs from SLOF.
Signed-off-by: Laurent Vivier
Reviewed-by: Michael S. Tsirkin
Reviewed-by:
From: Laurent Vivier
When DT node names for PCI devices are generated by SLOF,
they are generated according to the type of the device
(for instance, ethernet for virtio-net-pci device).
Node name for hotplugged devices is generated by QEMU.
This patch adds the mechanic to QEMU to create the node
cpu_ppc_set_papr() sets up various aspects of CPU state for use with PAPR
paravirtualized guests. However, it doesn't set the virtual hypervisor,
so callers must also call cpu_ppc_set_vhyp() so that PAPR hypercalls are
handled properly. This is a bit silly, so fold setting the virtual
hypervisor
* Standardize on 'ptex' instead of 'pte_index' for HPTE index variables
for consistency and brevity
* Avoid variables named 'index'; shadowing index(3) from libc can lead to
surprising bugs if the variable is removed, because compiler errors
might not appear for remaining references
* C
From: Nikunj A Dadhania
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/translate.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index eba83ef..e083082
The following changes since commit e7c83a885f865128ae3cf1946f8cb538b63cbfba:
vhost-user: delay vhost_user_stop (2017-02-28 19:11:15 +)
are available in the git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-2.9-20170301
for you to fetch changes up to 356bb70ed1a8a741413d5
At present the SDR1 register - the base of the system's hashed page table
(HPT) - is represented as an SPR with supervisor read and write permission.
However, on CPUs which have a hypervisor mode, the SDR1 is a hypervisor
only resource. Change the permission checking on the SPR to reflect this.
N
From: Nikunj A Dadhania
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/Makefile.objs | 1 +
target/ppc/cpu.c | 36
target/ppc/cpu.h | 14 ++
3 files changed, 39 insert
From: Greg Kurz
Some systems can already provide more than 255 hardware threads.
Bumping the QEMU limit to 1024 seems reasonable:
- it has no visible overhead in top;
- the limit itself has no effect on hot paths.
Cc: Greg Kurz
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: David Gibson
From: Nikunj A Dadhania
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/translate.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 3ba2616..b09e16f 10
From: Nikunj A Dadhania
Removes duplicate code and will be useful for consolidating flags
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/int_helper.c | 34 +-
1 file changed, 13 insertions(+), 21 deletions(-)
diff --git a/target/pp
On 02/27/2017 10:41 AM, Marc-André Lureau wrote:
Instead of flushing the buffer byte by byte, call qemu_chr_be_write()
with as much byte possible accepted by the front-end.
Factor out buffer flushing in a common function udp_chr_flush_buffer().
Signed-off-by: Marc-André Lureau
Reviewed-by: P
On 02/27/2017 10:41 AM, Marc-André Lureau wrote:
g_strdup(NULL) returns NULL already.
Signed-off-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
---
chardev/char.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/chardev/char.c b/chardev/char.c
index 558fd8b31
On 2017年03月01日 11:23, Michael S. Tsirkin wrote:
On Wed, Mar 01, 2017 at 10:36:35AM +0800, Peter Xu wrote:
On Tue, Feb 28, 2017 at 04:42:25PM +0200, Marcel Apfelbaum wrote:
On 02/24/2017 06:29 AM, Peter Xu wrote:
Intel vIOMMU devices are created with "-device" parameter, while here
actually w
Commit c611c76417f5 ("virtio: add MemoryListener to cache ring
translations") registers a memory listener to dma_as. This may not
work when IOMMU is enabled: dma_as(bus_master_as) were initialized in
pcibus_machine_done() after virtio_realize(). This will cause a
segfault. Fixing this by using pci_
On Wed, Mar 01, 2017 at 12:06:14PM +1100, David Gibson wrote:
> On Tue, Feb 28, 2017 at 07:12:53PM +1100, Alexey Kardashevskiy wrote:
> > On 10/02/17 11:41, David Gibson wrote:
> > > On Thu, Feb 09, 2017 at 12:48:19PM +0100, Paolo Bonzini wrote:
> > >>
> > >>
> > >> On 09/02/2017 06:43, Alexey Kard
On Tue, Feb 28, 2017 at 06:56:47PM -0600, Michael Roth wrote:
> In certain cases, such as PCI-passthrough with VFIO, we cannot offload
> MMIO accesses to KVM unless the BAR alignment matches the host. This
> patch, in conjunction with a separately submitted patch for SLOF
> which allows for control
On 2017/2/28 1:10, Stefan Hajnoczi wrote:
On Fri, Jan 20, 2017 at 11:47:56AM +0800, zhanghailiang wrote:
@@ -119,12 +136,31 @@ static int replication_open(BlockDriverState *bs, QDict
*options,
"The option mode's value should be primary or secondary");
goto fail;
On Wed, Mar 01, 2017 at 10:36:35AM +0800, Peter Xu wrote:
> On Tue, Feb 28, 2017 at 04:42:25PM +0200, Marcel Apfelbaum wrote:
> > On 02/24/2017 06:29 AM, Peter Xu wrote:
> > >Intel vIOMMU devices are created with "-device" parameter, while here
> > >actually we need to make sure the dmar device be
on 2017/3/1 8:35, David Gibson wrote:
On Tue, Feb 28, 2017 at 06:12:56PM +0800, Yongji Xie wrote:
on 2017/2/28 8:41, David Gibson wrote:
On Mon, Feb 27, 2017 at 12:52:44PM +0800, Yongji Xie wrote:
At the moment ram device's memory regions are DEVICE_NATIVE_ENDIAN. It's
incorrect. This memory
On 2017/2/28 0:46, Stefan Hajnoczi wrote:
On Fri, Jan 20, 2017 at 11:47:55AM +0800, zhanghailiang wrote:
+Secondary:
+ -drive
if=none,driver=qcow2,file.filename=/mnt/ramfs/hidden_disk.img,id=hidden_disk0,\
+backing.driver=raw,backing.file.filename=1.raw \
+ -drive if=virtio,id=active-di
On 02/28/2017 04:55 AM, Pavel Dovgalyuk wrote:
[meta-comment]
> This patch enables making snapshots with blkreplay used in
> block devices.
> This function is required to make bdrv_snapshot_goto without
> calling .bdrv_open which is not implemented.
>
> v2: updated commit message
The v2 informa
On 02/27/2017 07:41 AM, Marc-André Lureau wrote:
> The function simply alias and hides the real event function.
s/alias/aliases/
>
> Signed-off-by: Marc-André Lureau
> ---
> include/sysemu/char.h | 1 -
> chardev/char-pty.c| 2 +-
> chardev/char-socket.c | 2 +-
> chardev/char.c
On 02/28/2017 06:29 AM, Daniel P. Berrange wrote:
> The only functional difference between the GENERATED_HEADERS
> and GENERATED_SOURCES variables is that 'Makefile' has a
> dependancy on GENERATED_HEADERS, causing generated header files
s/dependancy/dependency/
> to be created immediatey at the
On Tue, Feb 28, 2017 at 04:42:25PM +0200, Marcel Apfelbaum wrote:
> On 02/24/2017 06:29 AM, Peter Xu wrote:
> >Intel vIOMMU devices are created with "-device" parameter, while here
> >actually we need to make sure the dmar device be created before other
> >PCI devices (like vfio-pci) so that we kno
On Tue, Feb 28, 2017 at 08:32:17AM -0500, Mike Nawrocki wrote:
> Signed-off-by: Mike Nawrocki
>
> Sorry, I was only testing against the ppc-softmmu and ppc64-softmmu targets.
> I've now validated that this compiles against the following targets:
> ppc-softmmu,ppc64-softmmu,ppcemb-softmmu,s390x-s
On Tue, Feb 28, 2017 at 11:22:54AM +0100, Laurent Vivier wrote:
> Le 28/02/2017 à 02:09, David Gibson a écrit :
> > On Wed, Feb 01, 2017 at 09:43:57PM +0100, Laurent Vivier wrote:
> >> Le 31/01/2017 à 23:05, Jose Ricardo Ziviani a écrit :
> >>> A segfault is noticed when an emulated program uses an
On Mon, Feb 27, 2017 at 11:20:16PM +0100, Greg Kurz wrote:
> David,
>
> Any chances to have this in 2.9 ?
Yes. I've put it in my tree and I'm hoping to send a pull request
shortly. Actually, I was hoping to send it yesterday, but hit a bug
during testing which I'm now chasing.
>
> On Wed, 22
On Wed, Mar 01, 2017 at 11:16:02AM +1100, David Gibson wrote:
> On Mon, Feb 27, 2017 at 10:11:57AM +, Peter Maydell wrote:
> > On 27 February 2017 at 01:05, David Gibson
> > wrote:
> > > On Fri, Feb 24, 2017 at 10:35:35AM +, Peter Maydell wrote:
> > >> On 24 February 2017 at 00:16, David
On Tue, Feb 28, 2017 at 07:12:53PM +1100, Alexey Kardashevskiy wrote:
> On 10/02/17 11:41, David Gibson wrote:
> > On Thu, Feb 09, 2017 at 12:48:19PM +0100, Paolo Bonzini wrote:
> >>
> >>
> >> On 09/02/2017 06:43, Alexey Kardashevskiy wrote:
> >>> On 03/01/17 10:34, David Gibson wrote:
> On Th
On Tue, Feb 28, 2017 at 06:12:56PM +0800, Yongji Xie wrote:
> on 2017/2/28 8:41, David Gibson wrote:
>
> > On Mon, Feb 27, 2017 at 12:52:44PM +0800, Yongji Xie wrote:
> > > At the moment ram device's memory regions are DEVICE_NATIVE_ENDIAN. It's
> > > incorrect. This memory region is backed by a M
On Mon, Feb 27, 2017 at 10:11:57AM +, Peter Maydell wrote:
> On 27 February 2017 at 01:05, David Gibson
> wrote:
> > On Fri, Feb 24, 2017 at 10:35:35AM +, Peter Maydell wrote:
> >> On 24 February 2017 at 00:16, David Gibson
> >> wrote:
> >> > Ok, I've pushed libfdt upstream patches to (
On 2017/3/1 0:14, Andrea Arcangeli wrote:
Hello,
On Tue, Feb 28, 2017 at 09:48:26AM +0800, Hailiang Zhang wrote:
Yes, for current implementing of live snapshot, it supports tcg,
but does not support kvm mode, the reason i have mentioned above,
if you try to implement it, i think you need to sta
** Changed in: qemu
Status: In Progress => Fix Committed
** Changed in: qemu
Assignee: Timothy Pearson (kb9vqf) => pranith (bobby-prani)
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1591
Hello John, Paolo,
2017-03-01 8:47 GMT+08:00 John Snow :
>
>
> On 02/09/2017 02:04 AM, Li Qiang wrote:
> > As the pci ahci can be hotplug and unplug, in the ahci unrealize
> > function it should free all the resource once allocated in the
> > realized function. This patch adds two cleanup functio
In certain cases, such as PCI-passthrough with VFIO, we cannot offload
MMIO accesses to KVM unless the BAR alignment matches the host. This
patch, in conjunction with a separately submitted patch for SLOF
which allows for control of this via the device-tree, allows us to
set this alignment via QEMU
On 02/09/2017 02:04 AM, Li Qiang wrote:
> As the pci ahci can be hotplug and unplug, in the ahci unrealize
> function it should free all the resource once allocated in the
> realized function. This patch adds two cleanup function.
>
So, the peculiarities of the current arrangement of QDEV reali
On 02/28/2017 07:35 PM, John Snow wrote:
>
>
> On 02/09/2017 02:04 AM, Li Qiang wrote:
>> This can avoid memory leak when hotunplug the ahci device.
>>
>> Signed-off-by: Li Qiang
>> ---
>> hw/ide/ahci.c | 8
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/hw/ide/ahci.c b/hw/ide
On 02/09/2017 02:04 AM, Li Qiang wrote:
> This can avoid memory leak when hotunplug the ahci device.
>
> Signed-off-by: Li Qiang
> ---
> hw/ide/ahci.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
> index 3c19bda..56f68a8 100644
> --- a/hw/ide/
On Tue, Feb 28, 2017 at 4:33 PM, Richard Henderson wrote:
> Only one this week. Pranith didn't mention which compiler version,
> but I can imagine gcc7 or clang warning of such a thing.
>
I apologize for missing this information in the patch. The warning was
from clang master.
Thanks,
--
Pranit
On 02/28/2017 03:52 PM, Jyoti Panwar wrote:
> how can i started?? coding in this organisation.
Here's some useful links:
http://wiki.qemu-project.org/Contribute/SubmitAPatch
http://wiki.qemu-project.org/BiteSizedTasks
My general advice (not just for this list, but any project): subscribe
to the
On 02/27/2017 05:04 AM, Marc-André Lureau wrote:
> Hi
>
> On Tue, Feb 21, 2017 at 6:27 PM Marc-André Lureau <
> marcandre.lur...@redhat.com> wrote:
>
>> After this series removing a few memory leaks, make check with ASAN
>> enabled gives a "clean" run with x86_64-softmmu target (there are
>> warn
On 02/21/2017 08:14 AM, Marc-André Lureau wrote:
> Use qvirtio_pci_device_find_slot() to avoid leaking the non-hp
> device. Add assert() to avoid further leaks in the future.
>
> Use qvirtio_pci_device_free() to correctly free QVirtioPCIDevice.
Yep, the hunk I mentioned in 28/30 probably belongs
On 02/21/2017 08:14 AM, Marc-André Lureau wrote:
> Allows to specify which slot to look for the device.
"Allow[s] to ${verb}" is not idiomatic; it's missing a subject. But
"Allows $subject to" (as in "allows someone to" or "allows me to") is
wordy, compared to just saying "Allows ${verb}ing". I'
On 02/28/2017 11:01 PM, Eric Bischoff wrote:
From: Eric Bischoff
LPD = LOAD PAIR DISJOINT
Fourth patch
---
target/s390x/insn-data.def | 4 ++-
target/s390x/translate.c | 63 ++
2 files changed, 66 insertions(+), 1 deletion(-)
Oh, I'm also missin
On 02/21/2017 08:14 AM, Marc-André Lureau wrote:
> Spotted by ASAN.
>
> Signed-off-by: Marc-André Lureau
> ---
> tests/tco-test.c | 35 +--
> 1 file changed, 21 insertions(+), 14 deletions(-)
>
Reviewed-by: Eric Blake
--
Eric Blake eblake redhat com+1-9
On 02/21/2017 08:14 AM, Marc-André Lureau wrote:
> Spotted by ASAN.
>
> Signed-off-by: Marc-André Lureau
> ---
> tests/libqos/virtio-pci.h | 2 ++
> tests/libqos/virtio-pci.c | 6 ++
> tests/vhost-user-test.c | 11 +++
> 3 files changed, 15 insertions(+), 4 deletions(-)
>
Revie
On 02/21/2017 08:14 AM, Marc-André Lureau wrote:
> Spotted by ASAN.
>
> Signed-off-by: Marc-André Lureau
> ---
> tests/q35-test.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/tests/q35-test.c b/tests/q35-test.c
> index 763fe3d6ae..e010d781e7 100644
> --- a/tests/q35-test.c
> +++
On 02/28/2017 03:27 PM, Markus Armbruster wrote:
> Additionally permit non-negative integers as key components. A
> dictionary's keys must either be all integers or none. If all keys
> are integers, convert the dictionary to a list. The set of keys must
> be [0,N].
>
> +static void test_keyval
> From: no-re...@patchew.org [mailto:no-re...@patchew.org]
> Sent: Tuesday, 28 February 2017 14:13
>
> Hi,
>
> This series failed build test on s390x host. Please find the details below.
[..]
> /var/tmp/patchew-tester-tmp-64adnjjr/src/target/arm/helper.c:931:23:
> error: ‘pmreg_access_ccntr’ defi
On 28 February 2017 at 21:58, Andrew Baumann
wrote:
> On a successful long-descriptor translation, PAR_EL1 bits 56:63 are
> expected to report the memory attributes of the page. However, the
> page table walker (get_phys_addr()) does not currently retrieve these
> attributes. Rather than leaving t
On Mon, Feb 27, 2017 at 1:22 AM, Daniel P. Berrange wrote:
> On Fri, Feb 24, 2017 at 03:30:21PM -0800, ashish mittal wrote:
>> Thanks!
>>
>> I hope the following is in line with what you suggested -
>
> Yes, that looks suitable for password auth
>
Thanks!
>>
>> We will error out in case either of
On 28 February 2017 at 21:34, John Snow wrote:
>
>
> On 02/28/2017 01:24 PM, Gerd Hoffmann wrote:
>> On Di, 2017-02-28 at 11:48 -0500, John Snow wrote:
>>>
>>> On 02/28/2017 04:06 AM, Gerd Hoffmann wrote:
Hi,
Here comes the seabios update for qemu 2.9,
the just tagged 1.10.2
Additionally permit non-negative integers as key components. A
dictionary's keys must either be all integers or none. If all keys
are integers, convert the dictionary to a list. The set of keys must
be [0,N].
Examples:
* list.1=goner,list.0=null,list.1=eins,list.2=zwei
is equivalent to JSON
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