On 04/24/2017 11:48 AM, Jason Wang wrote:
On 2017年04月20日 14:39, Zhang Chen wrote:
If user use -device virtio-net-pci, virtio-net driver will add a header
to raw net packet that colo-proxy can't handle it. COLO-proxy just
focus on the packet payload, so we skip the virtio-net header to compar
Hi all,
Recently, I found migration failed when enable vPMU.
migrate vPMU state was introduced in linux-3.10 + qemu-1.7.
As long as enable vPMU, qemu will save / load the
vmstate_msr_architectural_pmu(msr_global_ctrl) register during the migration.
But global_ctrl generated based on cpuid(0xA),
This is a re-post, I didn't send it to all relevant mailing lists before...
Original below.
Hi everyone,
I have an interesting issue with DAX and KVM - I'm trying to boot a VM
with its memory mapped to a DAX-mounted file (kernel 4.9).
The use case is a bit wacky but I'm trying to recreate somet
On Fri, 04/21 15:51, Kevin Wolf wrote:
> Am 21.04.2017 um 05:55 hat Fam Zheng geschrieben:
> > qemu-img and qemu-io commands when guest is running need "-U" option,
> > add it.
> >
> > Signed-off-by: Fam Zheng
> > ---
> > tests/qemu-iotests/030 | 24
> > 1 file changed,
On Fri, 04/21 15:25, Kevin Wolf wrote:
> Am 21.04.2017 um 05:55 hat Fam Zheng geschrieben:
> > Similar to share-rw qdev property, this will force the opened images to
> > allow shared write permission of other programs.
> >
> > Signed-off-by: Fam Zheng
>
> General observation: We were considerin
On 2017/4/24 12:13, Jason Wang wrote:
On 2017年04月20日 15:46, zhanghailiang wrote:
If some errors happen before main_loop is initialized in colo
compare thread, qemu will go into finalizing process where
we call g_main_loop_quit(s->main_loop), if main_loop is NULL, there
will be an error report:
On 2017/4/24 12:10, Jason Wang wrote:
On 2017年04月20日 15:46, zhanghailiang wrote:
We call qemu_chr_fe_set_handlers() in colo-compare thread, it is used
to detach watched fd from default main context, so it has chance to
handle the same watched fd with main thread concurrently, which will
trigger
On Fri, 04/21 10:37, Eric Blake wrote:
> On 04/20/2017 10:55 PM, Fam Zheng wrote:
> > Signed-off-by: Fam Zheng
> > ---
> > qemu-img-cmds.hx | 48
> > 1 file changed, 24 insertions(+), 24 deletions(-)
> >
> > diff --git a/qemu-img-cmds.hx b/qemu-im
From: Zhang Chen
Optimize two trace events as one, adjust print format make
it easy to read. rename trace_colo_compare_pkt_info_src/dst
to trace_colo_compare_tcp_info.
Signed-off-by: Zhang Chen
Signed-off-by: Jason Wang
---
net/colo-compare.c | 29 +
net/trace-even
From: Cédric Le Goater
NC-SI (Network Controller Sideband Interface) enables a BMC to manage
a set of NICs on a system. This model takes the simplest approach and
reverses the NC-SI packets to pretend a NIC is present and exercise
the Linux driver.
The NCSI header file comes from mainline Linux
From: Cédric Le Goater
This adds comments on the Basic mode control and status registers bit
definitions. It also adds a couple of bits for 1000BASE-T and the
RealTek 8211E PHY for the FTGMAC100 model to use.
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Ja
From: Cédric Le Goater
The FTGMAC100 device is an Ethernet controller with DMA function that
can be found on Aspeed SoCs (which include NCSI).
It is fully compliant with IEEE 802.3 specification for 10/100 Mbps
Ethernet and IEEE 802.3z specification for 1000 Mbps Ethernet and
includes Reduced Me
From: Cédric Le Goater
The Aspeed SoCs have a different definition of the end of the ring
buffer bit. Add a property to specify which set of bits should be used
by the NIC.
Signed-off-by: Cédric Le Goater
Signed-off-by: Jason Wang
---
hw/net/ftgmac100.c | 17 +++--
include
From: Zhang Chen
In this patch we support packet that have tcp options field.
Add tcp options field check, If the packet have options
field we just skip it and compare tcp payload,
Avoid unnecessary checkpoint, optimize performance.
Signed-off-by: Zhang Chen
Signed-off-by: Jason Wang
---
net/
From: Cédric Le Goater
There is a second NIC but we do not use it for the moment. We use the
'aspeed' property to tune the definition of the end of ring buffer bit
for the Aspeed SoCs.
Signed-off-by: Cédric Le Goater
Signed-off-by: Jason Wang
---
hw/arm/aspeed_soc.c | 21 +
From: Zhang Chen
If colo-compare find one old packet,we can notify colo-frame
do checkpoint, no need continue find more old packet here.
Signed-off-by: Zhang Chen
Signed-off-by: Jason Wang
---
net/colo-compare.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --gi
The following changes since commit 32c7e0ab755745e961f1772e95cac381cc68769d:
Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170421'
into staging (2017-04-21 15:59:27 +0100)
are available in the git repository at:
https://github.com/jasowang/qemu.git tags/net-pull-reques
On Thu, Apr 20, 2017 at 09:05:28PM -0500, Scott Wood wrote:
> I recently left Freescale/NXP, and even before that it'd been a few years
> since I was actively involved in KVM/QEMU work.
>
> Signed-off-by: Scott Wood
> ---
> Sorry for the resend -- fixed mailing list address.
Applied to my ppc-fo
On Sun, Apr 23, 2017 at 08:08:23PM -0700, no-re...@patchew.org wrote:
> Hi,
>
> This series seems to have some coding style problems. See output below for
> more information:
>
> Message-id: 20170424015927.8933-1-da...@gibson.dropbear.id.au
> Subject: [Qemu-devel] [PULL 00/47] ppc-for-2.10 queue
On 2017年04月20日 15:46, zhanghailiang wrote:
If some errors happen before main_loop is initialized in colo
compare thread, qemu will go into finalizing process where
we call g_main_loop_quit(s->main_loop), if main_loop is NULL, there
will be an error report:
"(process:14861): GLib-CRITICAL **: g_
On 2017年04月20日 15:46, zhanghailiang wrote:
We call qemu_chr_fe_set_handlers() in colo-compare thread, it is used
to detach watched fd from default main context, so it has chance to
handle the same watched fd with main thread concurrently, which will
trigger an error report:
"qemu-char.c:918: io
On 2017年04月20日 14:39, Zhang Chen wrote:
If user use -device virtio-net-pci, virtio-net driver will add a header
to raw net packet that colo-proxy can't handle it. COLO-proxy just
focus on the packet payload, so we skip the virtio-net header to compare
the sent packet that primary guest's to sec
On 2017年04月18日 10:20, Zhang Chen wrote:
In the first patch, we add tcp options support to optimize compare performance.
and another patch simplified code and adjust trace print format.
Zhang Chen (2):
COLO-compare: Optimize tcp compare for option field
COLO-compare: Optimize tcp compare
On 2017年04月21日 16:22, Zhang Chen wrote:
On 04/21/2017 12:10 PM, Jason Wang wrote:
On 2017年04月21日 11:48, Zhang Chen wrote:
On 04/20/2017 02:43 PM, Jason Wang wrote:
On 2017年04月18日 10:20, Zhang Chen wrote:
In this patch we support packet that have tcp options field.
Add tcp options fi
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20170424015927.8933-1-da...@gibson.dropbear.id.au
Subject: [Qemu-devel] [PULL 00/47] ppc-for-2.10 queue 20170424
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(
This makes a small step fixing one of many style problems that exist in
the older ppc code. This removes spaces between function (or macro) name
and the following '('.
Signed-off-by: David Gibson
---
target/ppc/translate_init.c | 372 ++--
1 file changed,
From: Cédric Le Goater
The default LPC bus of a multichip system is on chip 0. It's
recognized by the firmware (skiboot) using a "primary" property in the
device tree.
We introduce a pnv_chip_lpc_offset() routine to locate the LPC node of
a chip and set the property directly from the machine lev
From: Cédric Le Goater
xics_system_init() does not need 'nr_servers' anymore as it is only
used to define the 'interrupt-controller' node in the device tree. So
let's just compute the value when calling spapr_dt_xics().
This also gives us an opportunity to simplify the xics_system_init()
routine
From: Cédric Le Goater
This patch provides a simple FRU support for the BMC simulator. FRUs
are loaded from a file which name is specified in the object
properties, each entry having a fixed size, also specified in the
properties. If the file is unknown or not accessible for some reason,
a unique
From: Benjamin Herrenschmidt
It adds the Naples chip which supports proper LPC interrupts via the
LPC controller rather than via an external CPLD.
Signed-off-by: Benjamin Herrenschmidt
[clg: - updated for qemu-2.9
- ported on latest PowerNV patchset
- moved the IRQ handler in pnv_lp
From: Cédric Le Goater
It will be used to fill the message buffer with custom events expected
by some systems. Typically, an Open PowerNV platform guest is notified
with an OEM SEL message before a shutdown or a reboot.
Signed-off-by: Cédric Le Goater
Acked-by: Corey Minyard
Signed-off-by: Dav
From: Bernhard Kaindl
This patch registers mfspr 259 for Book3S and e500 family cores
following this research:
mfspr 259 provides read-only mapped user access to SPRG3(SPR 275) according to:
- PowerISA 2.02, Book III (documents implementation starting with POWER4+ @ p20)
- IBM PowerPC 970MP RIS
From: Anton Blanchard
gdb refuses to parse QEMU memory dumps because struct PPCElfPrstatus
is the wrong size. Fix it.
Signed-off-by: Anton Blanchard
Fixes: e62fbc54d459 ("target-ppc: dump-guest-memory support")
Signed-off-by: David Gibson
---
target/ppc/arch_dump.c | 2 +-
1 file changed, 1 i
From: Cédric Le Goater
The code could be common to any ISA device but we are missing the IO
length.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/hw/pp
From: Cédric Le Goater
The Processor Service Interface (PSI) Controller is one of the engines
of the "Bridge" unit which connects the different interfaces to the
Power Processor.
This adds just enough of the PSI bridge to handle various on-chip and
the one external interrupt. The rest of PSI has
From: Suraj Jitindar Singh
The PIDR (process id register) is used to store the id of the currently
running process, which is used to select the process table entry used to
perform address translation. This means that when we write to this register
all the translations in the TLB become outdated a
From: Cédric Le Goater
Skiboot, the firmware for the PowerNV platform, expects the BMC to
provide some specific IPMI sensors. These sensors are exposed in the
device tree and their values are updated by the firmware at boot time.
Sensors of interest are :
"FW Boot Progress"
"Boo
From: Cédric Le Goater
This provides a new ICPState object for the PowerNV machine (POWER8).
Access to the Interrupt Management area is done though a memory
region. It contains the registers of the Interrupt Control Presenters
of each thread which are used to accept, return, forward interrupts in
From: Cédric Le Goater
This is an empty shell that we will use to include nodes in the device
tree for ISA devices. We expect RTC, UART and IPMI BT devices.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 28 +++
From: Benjamin Herrenschmidt
The OCC is an on-chip microcontroller based on a ppc405 core used
for various power management tasks. It comes with a pile of additional
hardware sitting on the PIB (aka XSCOM bus). At this point we don't
emulate it (nor plan to do so). However there is one facility w
From: Cédric Le Goater
OpenPOWER systems expect to be notified with such an event before a
shutdown or a reboot. An OEM SEL message is sent with specific
identifiers and a user data containing the request : OFF or REBOOT.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Signed-off-by:
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 8ab5bb1..dfa21e4 100644
--- a/hw/ppc/pnv.c
+++
From: Cédric Le Goater
Each thread of a core is linked to an ICP. This allocates a PnvICPState
object before the PowerPCCPU object is realized and lets the XICSFabric
do the store under the 'intc' backlink when xics_cpu_setup() is
called.
This modeling removes the need of maintaining an array of
From: Cédric Le Goater
The IPMI BMC simulator populates the sdr/sensor tables with a minimal
set of entries (Watchdog). But some qemu platforms might want to use
extra entries for their custom needs.
This patch modifies slighty the initializing routine to take into
account a larger set read from
From: Cédric Le Goater
Some controllers (ICP, PSI) have a base register address which is
calculated using the chip id.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
include/hw/ppc/pnv.h | 12 +++-
1 file changed, 11 insertions(+), 1 deletio
From: Sam Bobroff
Add the new node, /chosen/ibm,arch-vec-5-platform-support to the
device tree. This allows the guest to determine which modes are
supported by the hypervisor.
Update the option vector processing in h_client_architecture_support()
to handle the new MMU bits. This allows guests to
From: Cédric Le Goater
Today, the ICPState array of the sPAPR machine is indexed with
'cpu_index' of the CPUState. This numbering of CPUs is internal to
QEMU and the guest only knows about what is exposed in the device
tree, that is the 'cpu_dt_id'. This is why sPAPR uses the helper
xics_get_cpu_
From: Cédric Le Goater
This patch exposes a new IPMI routine to query a sdr entry from the
sdr table maintained by the IPMI BMC simulator. The API is very
similar to the internal sdr_find_entry() routine and should be used
the same way to query one or all sdrs.
A typical use would be to loop on
From: Cédric Le Goater
A XICSFabric QOM interface is used by the XICS layer to manipulate the
ICP and ICS objects. Let's define the associated handlers for the
PowerNV machine. All handlers should be defined even if there is no
ICS under the PowerNV machine yet.
Signed-off-by: Cédric Le Goater
From: Cédric Le Goater
Today, all the ICPs are created before the CPUs, stored in an array
under the sPAPR machine and linked to the CPU when the core threads
are realized. This modeling brings some complexity when a lookup in
the array is required and it can be simplified by allocating the ICPs
From: Cédric Le Goater
OpenPOWER systems use a BT device to communicate with the BMC.
Provide support for it.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
default-configs/ppc64-softmmu.mak | 4
1 file changed, 4 insertions(+)
diff --git a/default-configs/ppc64-softmmu
From: Cédric Le Goater
When an ipmi-bt device [1] is defined on the ISA bus, we need to
populate the device tree with the object properties. Such devices are
created with the command line options :
-device ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10
[1] https://lists.gnu.org/arc
From: Suraj Jitindar Singh
The ibm,processor-radix-AP-encodings device tree property of the cpu node
is used to specify the radix mode supported page sizes of the processor
to the guest os. Contained in the top 3 bits of the msb is the actual
page size (AP) encoding associated with the correspond
From: Bharata B Rao
Recent commits that re-organized ICPState object missed to destroy
the object when CPU is unrealized. Fix this so that CPU unplug
doesn't abort QEMU.
Signed-off-by: Bharata B Rao
Reviewed-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/spapr_cpu_core.c | 1 +
From: Cédric Le Goater
This is the second step to abstract the IRQ 'server' number of the
XICS layer. Now that the prereq cleanups have been done in the
previous patch, we can move down the 'cpu_dt_id' to 'cpu_index'
mapping in the sPAPR machine handler.
Signed-off-by: Cédric Le Goater
Reviewed
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 0a0cfe3..f3623ee 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -33,6 +33,8 @@
#include
From: Alexey Kardashevskiy
This enables in-kernel handling of H_PUT_TCE_INDIRECT and
H_STUFF_TCE hypercalls. The host kernel support is there since v4.6,
in particular d3695aa4f452
("KVM: PPC: Add support for multiple-TCE hcalls").
H_PUT_TCE is already accelerated and does not need any special e
From: Cédric Le Goater
This provides to a PowerNV chip (POWER8) access to the Interrupt
Management area, which contains the registers of the Interrupt Control
Presenters of each thread. These are used to accept, return, forward
interrupts in the system.
This area is modeled with a per-chip conta
From: Alexey Kardashevskiy
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: David Gibson
---
hw/ppc/spapr_pci.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 097ebdd..e7567e2 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -50,
From: Suraj Jitindar Singh
The use of the new in memory tables introduced in ISAv3.00 for translation,
also referred to as process tables, requires the introduction of 3 new
H-CALLs; H_REGISTER_PROCESS_TABLE, H_CLEAN_SLB, and H_INVALIDATE_PID.
Add shells for each of these and register them as th
From: Sam Bobroff
In the next patch, spapr_fixup_cpu_dt() will need to call
spapr_populate_pa_features() so move it's definition up without making
any other changes.
Signed-off-by: Sam Bobroff
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 122 ---
From: Cédric Le Goater
It will be used by derived classes in PowerNV for customization.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
hw/intc/xics.c| 5 +
include/hw/ppc/xics.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/hw/in
From: Sam Bobroff
Query and cache the value of two new KVM capabilities that indicate
KVM's support for new radix and hash modes of the MMU.
Signed-off-by: Sam Bobroff
Signed-off-by: David Gibson
---
target/ppc/kvm.c | 14 ++
target/ppc/kvm_ppc.h | 12
2 files cha
From: Suraj Jitindar Singh
The H_REGISTER_PROCESS_TABLE H_CALL is used by a guest to indicate to the
hypervisor where in memory its process table is and how translation should
be performed using this process table.
Provide the implementation of this H_CALL for a guest.
We first check for invali
From: Sam Bobroff
Use the new ioctl, KVM_PPC_GET_RMMU_INFO, to fetch radix MMU
information from KVM and present the page encodings in the device tree
under ibm,processor-radix-AP-encodings. This provides page size
information to the guest which is necessary for it to use radix mode.
Signed-off-b
From: Sam Bobroff
For a little while around 4.9, Linux kernels that saw the radix bit in
ibm,pa-features would attempt to set up the MMU as if they were a
hypervisor, even if they were a guest, which would cause them to
crash.
Work around this by detecting pre-ISA 3.0 guests by their lack of tha
From: Alexey Kardashevskiy
If a page size used by QEMU is not enabled in the PHB IOMMU page mask,
in-kernel acceleration of TCE handling won't be enabled and performance
might be slower than expected.
This prints a warning if system page size is not enabled. This should
print a warning if huge p
From: Cédric Le Goater
Also use an 'sPAPRRTCState' attribute under the sPAPR machine to hold
the RTC object. Overall, these changes remove an unnecessary and
implicit dependency on SysBus.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 16
The following changes since commit 32c7e0ab755745e961f1772e95cac381cc68769d:
Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170421'
into staging (2017-04-21 15:59:27 +0100)
are available in the git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-2.10-20170
From: Alexey Kardashevskiy
KVM_CAP_SPAPR_TCE capability allows creating TCE tables in KVM which
allows having in-kernel acceleration for H_PUT_TCE_xxx hypercalls.
However it only supports 32bit DMA windows at zero bus offset.
There is a new KVM_CAP_SPAPR_TCE_64 capability which supports 64bit
wi
From: Thomas Huth
The devices that are derived from TYPE_PNV_CHIP currently show up
as "uncategorized" devices in the help text of "-device ?". Since
they obviously are related to the CPU, let's put them into the
CPU category instead.
Signed-off-by: Thomas Huth
Signed-off-by: David Gibson
---
From: Sam Bobroff
On Power8 hosts it is currently theoretically possible for QEMU/KVM-HV guests
to receive a ibm,pa-features property indicating that HTM support is available
when it is not. The situation would occur if the platform firmware of
a Power8 host cleared the HTM bit of the ibm,pa-fea
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 35db949..de5db75 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -3158,18 +3158,37 @@ static const TypeInfo spapr_m
David Gibson wrote on 04/23/2017 06:17:22
PM:
> From: David Gibson
> To: Aaron Larson
> Cc: ag...@suse.de, qemu-devel@nongnu.org, qemu-...@nongnu.org
> Date: 04/23/2017 06:54 PM
> Subject: Re: Subject: [PATCH] target-ppc: Add global timer group A to
open-pic.
>
> On Fri, Apr 21, 2017 at 02:5
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: cover.1492986468.git.sho...@gmail.com
Subject: [Qemu-devel] [PATCH v2 0/9] Openrisc misc features / fixes
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log
On Fri, Apr 21, 2017 at 02:58:23PM -0700, Aaron Larson wrote:
> Add global timer group A to open-pic. This patch is still somewhat
> dubious because I'm not sure how to determine what QEMU wants for the
> timer frequency. Suggestions solicited.
This commit message really needs some more context.
On 04/23/2017 07:47 PM, Aurelien Jarno wrote:
On 2017-04-23 19:38, Philippe Mathieu-Daudé wrote:
Hi Aurelien!
Why don't lock inside s390_virtio_hypercall() directly round the diag500
dispatch call?
s390_virtio_hypercall is shared between TCG and KVM. For KVM the lock is
already done before ca
On 2017-04-23 19:38, Philippe Mathieu-Daudé wrote:
> Hi Aurelien!
>
> Why don't lock inside s390_virtio_hypercall() directly round the diag500
> dispatch call?
s390_virtio_hypercall is shared between TCG and KVM. For KVM the lock is
already done before calling s390_virtio_hypercall in kvm_arch_ha
Previously serialization did not persist the tlb, timer, pic and other
key state items. This meant snapshotting and restoring a running os
would crash. After adding these I am able to take snapshots of a
running linux os and restore at a later time.
I am currently not trying to maintain capatibil
In openRISC we are implementing the shadow registers as a 2d array.
Using this target long method rather than direct 32-bit alternatives is
consistent with the rest of our vm state serialization logic.
Signed-off-by: Stafford Horne
---
include/migration/cpu.h | 7 +++
1 file changed, 7 inser
For openrisc we implement tlb state as a 2d array of tlb entry structs.
This is added to allow easy storing of state of 2d arrays.
Signed-off-by: Stafford Horne
---
include/migration/vmstate.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/include/migration/vmstate.h b/incl
On 23.04.2017 12:19, Peter Maydell wrote:
> On 23 April 2017 at 00:27, Kamil Rytarowski wrote:
>> I noted a call for NetBSD maintainers in the 2.9.0 release notes.
>>
>> I'm willing to attach a NetBSD machine to CI cluster and volunteer basic
>> maintenance. I'm mostly interested in NetBSD as host
From: Tim 'mithro' Ansell
Exception Prefix High (EPH) control bit of the Supervision Register
(SR).
The significant bits (31-12) of the vector offset address for each
exception depend on the setting of the Supervision Register (SR)'s EPH
bit and the Exception Vector Base Address Register (EVBAR)
These are used to identify the processor in SMP system. Their
definition has been defined in verilog cores but it not yet part of the
spec but it will be soon.
The proposal for this is available:
https://openrisc.io/proposals/core-identifier-and-number-of-cores
Reviewed-by: Richard Henderson
Shadow registers are part of the openrisc spec along with sr[cid], as
part of the fast context switching feature. When exceptions occur,
instead of having to save registers to the stack if enabled the CID will
increment and a new set of registers will be available.
This patch only implements shad
From: Tim 'mithro' Ansell
Exception Vector Base Address Register (EVBAR) - This optional register
can be used to apply an offset to the exception vector addresses.
The significant bits (31-12) of the vector offset address for each
exception depend on the setting of the Supervision Register (SR)'
When debugging in gdb you might want to inspect instructions in mapped
pages or in exception vectors like 0x800 etc. This was previously not
possible in qemu since the *get_phys_page_debug() routine only looked
into the data tlb.
Change to fall back to look into instruction tlb and plain physical
The features property has stored the exact same thing as the cpucfgr
spr. Remove the feature enum and property as it is not needed.
In order to preserve the behavior or keeping features accross reset this
patch moves cpucfgr into the non reset region of the state struct. Since
the cpucfgr is read
Hello,
I have got a few response on the last series and have fixed them up. Also
I have dropped the shutdown patch.
These patches I added while working on upcoming openrisc smp support. This
does not allow for SMP openrisc on qemu "yet" but it does help to allow
booting of an SMP kernel on the
Hi Aurelien!
Why don't lock inside s390_virtio_hypercall() directly round the diag500
dispatch call?
regards,
Phil.
On 04/23/2017 07:32 PM, Aurelien Jarno wrote:
s390_virtio_hypercall can trigger IO events and interrupts, most notably
when using virtio-ccw devices.
Reviewed-by: Alexander G
From: Philipp Kern
According to "CPU Signaling and Response", "Signal-Processor Orders",
the order field is bit position 56-63. Without this, the Linux
guest kernel is sometimes unable to stop emulation and enters
an infinite loop of "XXX unknown sigp: 0x0005".
Signed-off-by: Philipp
s390_virtio_hypercall can trigger IO events and interrupts, most notably
when using virtio-ccw devices.
Reviewed-by: Alexander Graf
Signed-off-by: Aurelien Jarno
---
target/s390x/misc_helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_h
On 2017-04-23 19:19, Alexander Graf wrote:
>
>
> > Am 23.04.2017 um 18:08 schrieb Aurelien Jarno :
> >
> > s390_virtio_hypercall can trigger IO events and interrupts, most notably
> > when using virtio-ccw devices.
> >
> > Signed-off-by: Aurelien Jarno
> > ---
> > roms/qemu-palcode |
The OpenRISC architecture has the Power Management Register (PMR)
special purpose register to manage cpu power states. The interesting
modes are:
* Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt
* Sleep Mode (SME) - Stop cpu and all units - wake on interrupt
* Suspend Model
27.02.2017 22:36, Thomas Huth wrote:
> On 25.01.2017 21:45, Thomas Huth wrote:
>> When running QEMU with "-M none -device loader,file=kernel.elf", it
>> currently crashes with a segmentation fault, because the "none"-machine
>> does not have any CPU by default and the generic loader code tries
>> t
07.02.2017 16:27, Fam Zheng wrote:
> Laszlo spotted and studied this wasteful "if". He pointed out:
>
> The original virtio_blk_free_request needed an "if" as it accesses one
> field, since 671ec3f05655 ("virtio-blk: Convert VirtIOBlockReq.elem to
> pointer", 2014-06-11); later on in f897bf751fbd
08.03.2017 15:13, Thomas Huth wrote:
> There are some broken URLs in the qemu-doc which reference tools that
> are not available at their original location anymore. Fortunately, they
> have been mirrored to archive.org, so point to that location instead.
Applied to -trivial, thanks!
/mjt
14.03.2017 19:59, Andreas Grapentin wrote:
> QEMU_BUILD_BUG_ON should use C11's _Static_assert, if the compiler supports
> it,
> to provide more readable messages on failure.
...
Applied to -trivial, with trivial commit comment fix. Thanks!
/mjt
21.03.2017 04:53, Eric Blake wrote:
> On 03/20/2017 08:39 PM, wangguang wrote:
>> Subject: [PATCH]COLO:Fix spell error in Colo doc
>
> I added qemu-trivial in v4; you should keep it in the loop.
>
> Still missing a space after ':' in the subject line, and still the
> awkward duplication of the su
> Am 23.04.2017 um 18:08 schrieb Aurelien Jarno :
>
> s390_virtio_hypercall can trigger IO events and interrupts, most notably
> when using virtio-ccw devices.
>
> Signed-off-by: Aurelien Jarno
> ---
> roms/qemu-palcode | 2 +-
> roms/seabios | 2 +-
> target/s390x/misc_he
1 - 100 of 116 matches
Mail list logo
