07.05.2017 00:30, FONNEMANN Mark write:
> Hello-
>
> I am trying to shares files between Windows host and Linux guest using
> slirp’s built-in SMB server.
There's no such thing as "slirp built-in SMB Server". Qemu does not have an SMB
server
built-in, qemu uses samba to provide smb functionalit
On 05/14/2017 02:18 AM, Kamil Rytarowski wrote:
Ensure that C99 macros are defined regardless of the inclusion order of
headers in vixl. This is required at least on NetBSD.
The vixl/globals.h headers defines __STDC_CONSTANT_MACROS and must be
included before other system headers.
This file def
On 04/26/2017 02:13 PM, Peter Maydell wrote:
We were setting the VBPR1 field of VMCR_EL2 to icv_min_vbpr()
on reset, but this is not correct. The field should reset to
the minimum value of ICV_BPR0_EL1 plus one.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_cpuif.c | 2 +-
1 file changed,
On 04/26/2017 02:13 PM, Peter Maydell wrote:
icc_bpr_write() was not enforcing that writing a value below the
minimum for the BPR should behave as if the BPR was set to the
minimum value. This doesn't make a difference for the secure
BPRs (since we define the minimum for the QEMU implementation
a
Ensure that C99 macros are defined regardless of the inclusion order of
headers in vixl. This is required at least on NetBSD.
The vixl/globals.h headers defines __STDC_CONSTANT_MACROS and must be
included before other system headers.
This file defines unconditionally the following macros, without
Hi Peter,
On 04/26/2017 02:13 PM, Peter Maydell wrote:
When we calculate the mask to use to get the group priority from
an interrupt priority, the way that NS BPR1 is handled differs
from how BPR0 and S BPR1 work -- a BPR1 value of 1 means
the group priority is in bits [7:1], whereas for BPR0 an
Hi Peter
I found it can't backup the guest RAM when i run simple ram test code with
errors which can't backing storage for guest RAM with integratorcp, the
commander is:
qemu-system-arm -M integratorcp -m 1 -semihosting -nographic -mem-path mem.txt
-kernel build/emu_ram_test.elf
i wrote the
>I am trying to shares files between Windows host and Linux guest using slirp’s
>built-in SMB server.
>I start QEMU 2.9.0 using the following:
>
>C:\Program Files\qemu>qemu-system-i386.exe -readconfig
>\Users\mfonnemann\qemu.cfg -net nic -net user,smb=\Users\mfonnemann\smb
>
>I then try to mount
>From 7f74f048f135d9c9c230a9e90f72451c841c6d35 Mon Sep 17 00:00:00 2001
From: John Bradley
Date: Sat, 13 May 2017 23:07:47 +0100
Subject: [PATCH] Changes to Broadcom(BCM) files and Raspberry Pi files.
Addition of PanelEmu
The files add the ability to attach, via TCP, a panel emulator
The include
Is this just me. I got the following message from 2 different SMTP servers.
Google & Yahoo when sending via GIT mail. Mail to myself worked.
Your message wasn't delivered to qemu-devel@nongnu.org because the address
couldn't be found. Check for typos or unnecessary spaces and try again. John
Br
On 05/02/2017 07:05 PM, Alistair Francis wrote:
On Tue, Apr 25, 2017 at 5:06 AM, Peter Maydell wrote:
When identifying the DFSR format for an alignment fault, use
the mmu index that we are passed, rather than calling cpu_mmu_index()
to get the mmu index for the current CPU state. This doesn't a
On 05/03/2017 06:30 PM, Alistair Francis wrote:
On Tue, Apr 25, 2017 at 5:07 AM, Peter Maydell wrote:
From: Michael Davidsaver
Improve the "-d mmu" tracing for the PMSAv7 MPU translation
process as an aid in debugging guest MPU configurations:
* fix a missing newline for a guest-error log
*
On 04/25/2017 09:07 AM, Peter Maydell wrote:
Now that we enforce both:
* pmsav7_dregion == 0 implies has_mpu == false
* PMSA with has_mpu == false means SCTLR.M cannot be set
we can remove a check on pmsav7_dregion from get_phys_addr_pmsav7(),
because we can only reach this code path if the MPU
On 05/03/2017 06:30 PM, Alistair Francis wrote:
On Tue, Apr 25, 2017 at 5:07 AM, Peter Maydell wrote:
If the CPU is a PMSA config with no MPU implemented, then the
SCTLR.M bit should be RAZ/WI, so that the guest can never
turn on the non-existent MPU.
Signed-off-by: Peter Maydell
Reviewed-b
On 04/25/2017 09:07 AM, Peter Maydell wrote:
All M profile CPUs are PMSA, so set the feature bit.
(We haven't actually implemented the M profile MPU register
interface yet, but setting this feature bit gives us closer
to correct behaviour for the MPU-disabled case.)
Signed-off-by: Peter Maydell
On 04/25/2017 09:07 AM, Peter Maydell wrote:
Fix the handling of QOM properties for PMSA CPUs with no MPU:
Allow no-MPU to be specified by either:
* has-mpu = false
* pmsav7_dregion = 0
and make setting one imply the other. Don't clear the PMSA
feature bit in this situation.
Signed-off-by: Pe
Hi Peter,
On 04/25/2017 09:07 AM, Peter Maydell wrote:
ARM CPUs come in two flavours:
* proper MMU ("VMSA")
* only an MPU ("PMSA")
For PMSA, the MPU may be implemented, or not (in which case there
is default "always acts the same" behaviour, but it isn't guest
programmable).
QEMU is a bit con
Hello,
I will give it a try and submit as a new patch.
On 14.05.2017 00:04, Philippe Mathieu-Daudé wrote:
> Hi Kamil,
>
> I think it is safer to add it in disas/libvixl/Makefile.objs where
> QEMU_CFLAGS are tuned for libvixl.
> This way you don't need to modify upstream libvixl.
>
> Regards,
>
On 05/10/2017 05:32 AM, guangrong.x...@gmail.com wrote:
From: Xiao Guangrong
Any tick policy specified on other platforms rather on TARGET_I386
will fall back to LOST_TICK_POLICY_DISCARD silently, this patch makes
sure only TARGET_I386 can enable LOST_TICK_POLICY_SLEW
After that, we can enable
On 05/10/2017 05:32 AM, guangrong.x...@gmail.com wrote:
From: Xiao Guangrong
If the code purely depends on LOST_TICK_POLICY_SLEW, we can simply
drop '#ifdef TARGET_I386' as only x86 can enable this tick policy
Signed-off-by: Xiao Guangrong
Reviewed-by: Philippe Mathieu-Daudé
---
hw/time
Hi Philippe and Aurelien,
You are right. I have created a simple SYSBUS using sysbus_create_simple
at 0x1800 and now my read function works!
Thanks for help. I am attaching my code if you are interested.
Vinicius
2017-05-13 18:57 GMT-03:00 Philippe Mathieu-Daudé :
> Hi Vinicius,
>
> On 201
Hi Kamil,
I think it is safer to add it in disas/libvixl/Makefile.objs where
QEMU_CFLAGS are tuned for libvixl.
This way you don't need to modify upstream libvixl.
Regards,
Phil.
On 05/12/2017 10:54 PM, Kamil Rytarowski wrote:
The __STDC_CONSTANT_MACROS symbol must be defined before includi
Hi Vinicius,
On 2017-05-12 19:52, Vinicius Maciel wrote:
Hi all,
I'm trying to emulate a MIPS 74Kc using a custom machine in order to run a
CFE bootloader from broadcom. The CPU is Broadcom BCM5357. The problem
Here is your problem, there is no such model in QEMU.
happens when Qemu calcula
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH 00/17] qobject/qapi: add uint type
Type: series
Message-id: 20170509173559.31598-1-marcandre.lur...@redhat.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=
Hi Zhang
On 05/11/2017 10:41 PM, Zhang Chen wrote:
Add vnet_hdr_len and using_vnet_hdr arguments in NetClientState
that make othermodule get real vnet_hdr_len easily.
Signed-off-by: Zhang Chen
---
include/net/net.h | 2 ++
net/net.c | 2 ++
2 files changed, 4 insertions(+)
diff --git
On 05/12/2017 01:00 PM, Juan Quintela wrote:
Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by: Philippe Mathieu-Daudé
--
Minor rearrangements due to rebase
---
include/migration/migration.h | 1 -
migration/block.c | 1 +
migration/colo-comm.c
On 05/12/2017 09:46 PM, Kamil Rytarowski wrote:
ivshmem-server makes use of the POSIX shared memory object interfaces.
This library is provided on NetBSD in -lrt (POSIX Real-time Library).
Add ./configure check if there is needed -lrt linking for shm_open()
and if so use it. Introduce new configu
Hi Mao,
You can use shorter patch subject "net/rocker" instead of
"hw/net/rocker/rocker".
On 05/12/2017 05:35 AM, Mao Zhongyi wrote:
Convert pci device .init() to .realize(). Also improve -device rocker
error reporting. Because when -device rocker fails, it first reports
a specific error, the
On 05/09/2017 02:35 PM, Marc-André Lureau wrote:
Use a more specific bool type.
Signed-off-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
---
hw/acpi/ich9.c | 24
hw/acpi/piix4.c | 8
hw/i386/acpi-build.c | 5 +++--
3 files changed
On 04/25/2017 07:04 PM, Juan Quintela wrote:
Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by: Philippe Mathieu-Daudé
--
Minor rearrangements due to rebase
Signed-off-by: Juan Quintela
---
include/migration/migration.h | 1 -
migration/block.c |
On 04/25/2017 07:04 PM, Juan Quintela wrote:
Signed-off-by: Juan Quintela
Reviewed-by: Philippe Mathieu-Daudé
---
hw/core/qdev.c | 1 -
include/hw/acpi/memory_hotplug.h | 1 -
include/hw/acpi/pcihp.h | 1 -
include/hw/pci/shpc.h| 1 -
include/net/net.
On 04/18/2017 02:13 AM, Stefan Weil wrote:
Am 18.04.2017 um 03:33 schrieb Eric Blake:
Rework the debug define so that we always get -Wformat checking,
even when debugging is disabled.
Signed-off-by: Eric Blake
---
Reviewed-by: Stefan Weil
Reviewed-by: Philippe Mathieu-Daudé
block/vd
On 2017-05-12 19:52, Vinicius Maciel wrote:
> Hi all,
>
> I'm trying to emulate a MIPS 74Kc using a custom machine in order to run a
> CFE bootloader from broadcom. The CPU is Broadcom BCM5357. The problem
> happens when Qemu calculates physaddr inside io_readx(), cputlb.c:line 784
>
> physaddr =
From: Prem Mallappa
Introduces the SMMUv3 derived model. This is based on
System MMUv3 specification (v17).
Signed-off-by: Prem Mallappa
Signed-off-by: Eric Auger
---
v3 -> v4
- smmu_irq_update
- fix hash key allocation
- set smmu_iommu_ops
- set SMMU_REG_CR0,
- smmuv3_translate: ret.perm not
From: Prem Mallappa
This patch builds the smmuv3 node in the ACPI IORT table.
The RID space of the root complex, which spans 0x0-0x1
maps to streamid space 0x0-0x1 in smmuv3, which in turn
maps to deviceid space 0x0-0x1 in the ITS group.
The guest must feature the IOMMU probe deferr
Introduces the base device and class for the ARM smmu.
Implements VMSAv8-64 table lookup and translation. VMSAv8-32
is not yet implemented.
For VFIO integration we will need to notify mapping changes
of an input range and skipped unmapped regions. table walk
helper allows.
Signed-off-by: Eric Aug
From: Prem Mallappa
Add code to instantiate an smmu-v3 in mach-virt. A new boolean flag
is introduced in VirtMachineState to allow this instantiation. It
is currently false.
Signed-off-by: Prem Mallappa
Signed-off-by: Eric Auger
---
v2 -> v3:
- vbi was removed. Use vms instead
- migrate to n
This series introduces the emulation code for ARM SMMUv3.
This is the continuation of Prem's work [1].
This v4 is yet another visibility step as many restrictions apply
to the model at the moment:
- only VMSAv8-64 is supported (no VMSAv8-32)
- only stage 1 has been tested (Block PTE still needs to
The new machine type allows smmuv3 instantiation. A new option
is introduced to turn the feature on/off (off by default).
Signed-off-by: Eric Auger
---
Another alternative would be to use the -device option as
done on x86. As the smmu is a sysbus device, we would need to
use the platform bus fr
The instruction "lock nopl (%rax)" should raise an exception. However,
we don't do that since we do not check for lock prefix for nop
instructions. The following patch adds this check and makes the
behavior similar to hardware.
Signed-off-by: Pranith Kumar
---
target/i386/translate.c | 3 +++
1
Hi all,
I'm trying to emulate a MIPS 74Kc using a custom machine in order to run a
CFE bootloader from broadcom. The CPU is Broadcom BCM5357. The problem
happens when Qemu calculates physaddr inside io_readx(), cputlb.c:line 784
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
After run this lin
I had two problems with QEMU on macOS:
1) Sometimes when alt-tabbing to QEMU it would act as if the 'a' key
was pressed so I'd get 'a'.
2) Using Sikuli to programatically send keys to the QEMU window text
like "foo_bar" would come out as "fooa-bar".
They looked similar and af
Now that ctx->flags has been split, it becomes clear that
DELAY_SLOT_CLEARME has not impact on the code generation: in both case
ctx->envflags is cleared, either by clearing all the flags, or by
setting it to 0. This is left-over from pre-TCG era.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by:
This doesn't change the generated code on x86, but optimizes it on most
RISC architectures and makes the code simpler to read.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target/sh4/translate.c | 9 +++--
1 file changed, 3 insertions
Using extr and avoiding intermediate temps.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target/sh4/translate.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
ind
synco is a SH4-A only instruction.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target/sh4/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 7a50
There is a confusion (and not only in the SH4 target) between tb->flags,
env->flags and ctx->flags. To avoid it, split ctx->flags into
ctx->tbflags and ctx->envflags. ctx->tbflags stays unchanged during the
whole TB translation, while ctx->envflags evolves and is kept in sync
with env->flags using
There is no need to save flags when entering and exiting the delay slot.
They can be saved only when reaching the end of the TB. If the TB is
interrupted before by an exception, they will be restored using
restore_state_to_opc.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
ta
DELAY_SLOT_TRUE is used as a dynamic condition for the branch after the
delay slot instruction. It is not used in code generation, so there is
no need to including in the TB state.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target/sh4/c
Instead of using one bit of the env flags to store the condition of the
next delay slot, use a separate global. It simplifies reading and
writing the flags variable and also removes some confusion between
ctx->envflags and env->flags.
Note that the global is first transfered to a temp in order to
In case of exception, there is no need to call tcg_gen_exit_tb as the
exception helper won't return.
Also fix a few cases where BS_BRANCH is called instead of BS_EXCP.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target/sh4/translate.c |
When stopping the translation because the state has changed, goto_tb
should not be used as it might link TB with different flags.
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Aurelien Jarno
---
target/sh4/translate.c | 5 +++--
1 file changed, 3 insertions(
SH4 requires that memory accesses are naturally aligned, except for the
SH4-A movua.l instructions which can do unaligned loads.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target/sh4/cpu.c | 1 +
target/sh4/cpu.h | 4
Use cpu_loop_exit_restore when using cpu_restore_state and cpu_loop_exit
together.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target/sh4/op_helper.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper
At the same time change the comment describing the instruction the same
way than other instruction, so that the code is easier to read and search.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target/sh4/translate.c | 26 +++---
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Aurelien Jarno
---
target/sh4/translate.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 8cee7d333f..a4c7a0895b 100644
--- a/targ
We only emulate UP SH4, however as the tas.b instruction is used in the GNU
libc, this improve linux-user emulation.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target/sh4/translate.c | 19 +++
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/t
The following changes since commit ecc1f5adeec4e3324d1b695a7c54e3967c526949:
maintainers: Add myself as linux-user reviewer (2017-05-11 13:31:11 -0400)
are available in the git repository at:
git://git.aurel32.net/qemu.git tags/pull-target-sh4-20170513
for you to fetch changes up to
On Fri, May 12, 2017 at 05:02:44PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 05/12/2017 03:28 AM, David Gibson wrote:
> > On Fri, May 05, 2017 at 05:47:46PM -0300, Daniel Henrique Barboza wrote:
> > > From: Jianjun Duan
> > >
> > > In racing situations between hotplug events and migration
On Fri, May 12, 2017 at 09:34:33AM -0500, alar...@ddci.com wrote:
> David Gibson wrote on 05/12/2017 01:52:04
> AM:
>
> > From: David Gibson
> > To: Aaron Larson
> > Cc: ag...@suse.de, qemu-devel@nongnu.org, qemu-...@nongnu.org
> > Date: 05/12/2017 01:52 AM
> > Subject: Re: [PATCH v2] target-p
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