[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1038070
Title:
> qemu-kvm-
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1067517
Title:
qemu dosn't
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1307281
Title:
qemu crash
This updates the current MemoryRegionOps for the bar 1 memory region
from using the old_mmio accessors to the .read and .write accessors.
Signed-off-by: Matt Parker
---
hw/net/rtl8139.c | 60 +++-
1 file changed, 16 insertions(+), 44 deletions(
This updates the current MemoryRegionOps for the bar 1 memory region
from using the old_mmio accessors to the .read and .write accessors.
Signed-off-by: Matt Parker
---
hw/net/rtl8139.c | 60 +++-
1 file changed, 16 insertions(+), 44 deletions(
> The keycodemap project[1] provides a database mapping between
> many different keysym/keycode/scancode sets, along with a
> tool to generate mapping/lookup tables in various programming
> languages. It is already used by GTK-VNC, SPICE-GTK and
> libvirt.
>
> This series enables its use in QEMU,
On 08/12/2017 09:29 AM, Alistair Francis wrote:
> Now we aren't ever checking cpu_exclusive_high. Is it even worth having?
We are checking cpu_exclusive_high for 64-bit STXP.
See paired_cmpxchg64_{l,b}e in target/arm/helper-a64.c.
r~
On Sat, Aug 12, 2017 at 8:41 AM, Richard Henderson wrote:
> SetExclusiveMonitors in the pseudocode is on the address + width,
> and says nothing about the manner of the load. Therefore
>
> ldxpw0, w1, [x2]
> vs
> ldxrx0, [x2]
>
> must record the same metadata so that eithe
Instead of copying addr to a local temp, reuse the value (which we
have just compared as equal) already saved in cpu_exclusive_addr.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 26 +-
1 file changed, 9 insertions(+), 17 deletions(-)
diff --git a/tar
SetExclusiveMonitors in the pseudocode is on the address + width,
and says nothing about the manner of the load. Therefore
ldxpw0, w1, [x2]
vs
ldxrx0, [x2]
must record the same metadata so that either may pair with
stxpw3, w0, w1, [x2]
vs
stxrw3,
Hi Eric,
On 08/12/2017 08:41 AM, Eric Blake wrote:
Here's an idea: Instead of using struct ip6 { ... } QEMU_PACKED, use
struct ip6 {
...
};
QEMU_BUG_ON(sizeof(struct ip6) != 32);
so that the compiler explicitly chokes if it introduced any padding, and
then we know all our accesses are natural
On 08/11/2017 03:17 PM, Alistair Francis wrote:
> When we perform the atomic_cmpxchg operation we want to perform the
> operation on a pair of 32-bit registers. Previously we were just passing
> the register size in which was set to MO_32. This would result in the
> high register to be ignored. To
On Sat, Aug 12, 2017 at 4:42 AM, Edgar E. Iglesias
wrote:
> On Sat, Aug 12, 2017 at 11:24:30AM +0100, Peter Maydell wrote:
>> On 11 August 2017 at 23:17, Alistair Francis
>> wrote:
>> > I found some issues with the way exclusive store was working. This patch
>> > series seems to fix the test case
On Sat, Aug 12, 2017 at 10:38:10AM +0200, Thomas Huth wrote:
> QEMU currently crashes when the user tries to add a spapr-cpu-core
> on a non-pseries machine:
>
> $ qemu-system-ppc64 -S -machine ppce500,accel=tcg \
> -device POWER5+_v2.1-spapr-cpu-core
> hw/ppc/spapr_cpu_core.c:
On 08/12/2017 06:47 AM, Samuel Thibault wrote:
> Eric Blake, on sam. 12 août 2017 06:41:30 -0500, wrote:
>> Here's an idea: Instead of using struct ip6 { ... } QEMU_PACKED, use
>>
>> struct ip6 {
>> ...
>> };
>> QEMU_BUG_ON(sizeof(struct ip6) != 32);
>
> That's an interesting way indeed. I howev
Eric Blake, on sam. 12 août 2017 06:41:30 -0500, wrote:
> Here's an idea: Instead of using struct ip6 { ... } QEMU_PACKED, use
>
> struct ip6 {
> ...
> };
> QEMU_BUG_ON(sizeof(struct ip6) != 32);
That's an interesting way indeed. I however wonder whether there may be
not-so-uncommon systems whe
On Sat, Aug 12, 2017 at 11:24:30AM +0100, Peter Maydell wrote:
> On 11 August 2017 at 23:17, Alistair Francis
> wrote:
> > I found some issues with the way exclusive store was working. This patch
> > series seems to fix the test cases that were failing for me.
> >
> > The first patch is just a sim
On 08/12/2017 06:29 AM, Samuel Thibault wrote:
>>
>> Alignment is architecture-dependent, and the compiler
>> can't know the alignment requirements for every
>> architecture.
>
> Sure.
True, but we can at least guess alignments that don't require padding,
and then be told by the compiler if our g
On Fri, Aug 11, 2017 at 03:17:38PM -0700, Alistair Francis wrote:
> Expose the tcg_gen_ext_i32() and tcg_gen_ext_i64() functions.
>
> Signed-off-by: Alistair Francis
> Reviewed-by: Richard Henderson
Reviewed-by: Edgar E. Iglesias
> ---
>
> Although I no longer am using these functions I hav
On Fri, Aug 11, 2017 at 03:17:36PM -0700, Alistair Francis wrote:
> Acording to the ARM ARM exclusive loads require the same allignment as
> exclusive stores. Let's update the memops used for the load to match
> that of the store. This adds the alignment requirement to the memops.
>
> Signed-off-b
On Fri, Aug 11, 2017 at 03:17:41PM -0700, Alistair Francis wrote:
> When we perform the atomic_cmpxchg operation we want to perform the
> operation on a pair of 32-bit registers. Previously we were just passing
> the register size in which was set to MO_32. This would result in the
> high register
Peter Maydell, on sam. 12 août 2017 12:18:16 +0100, wrote:
> On 12 August 2017 at 12:04, Samuel Thibault wrote:
> > Peter Maydell, on sam. 12 août 2017 11:53:20 +0100, wrote:
> >> The utility of the warning is that it means you get told
> >> about stuff that might break on other architectures.
> >
On 12 August 2017 at 12:04, Samuel Thibault wrote:
> Peter Maydell, on sam. 12 août 2017 11:53:20 +0100, wrote:
>> The utility of the warning is that it means you get told
>> about stuff that might break on other architectures.
>
> Sure, I understand that. But here all fields are aligned on their
Peter Maydell, on sam. 12 août 2017 11:53:20 +0100, wrote:
> The utility of the warning is that it means you get told
> about stuff that might break on other architectures.
Sure, I understand that. But here all fields are aligned on their size
inside the packed structure. So there can't be alignme
On 11 August 2017 at 22:58, Samuel Thibault wrote:
> Hello,
>
> Programmingkid, on jeu. 10 août 2017 16:44:19 -0400, wrote:
>> While compiling I saw these error messages:
>>
>> slirp/ip6_icmp.c:79:32: warning: taking address of packed member 'ip_src' of
>> class or
>> structure 'ip6' may re
On 11 August 2017 at 23:17, Alistair Francis
wrote:
> I found some issues with the way exclusive store was working. This patch
> series seems to fix the test cases that were failing for me.
>
> The first patch is just a simple adjustment.
>
> The third patch fixes the main bug I was seeing.
>
> Th
On Sat, 12 Aug 2017 10:38:10 +0200
Thomas Huth wrote:
> QEMU currently crashes when the user tries to add a spapr-cpu-core
> on a non-pseries machine:
>
> $ qemu-system-ppc64 -S -machine ppce500,accel=tcg \
> -device POWER5+_v2.1-spapr-cpu-core
> hw/ppc/spapr_cpu_core.c:178:s
QEMU currently crashes when the user tries to add a spapr-cpu-core
on a non-pseries machine:
$ qemu-system-ppc64 -S -machine ppce500,accel=tcg \
-device POWER5+_v2.1-spapr-cpu-core
hw/ppc/spapr_cpu_core.c:178:spapr_cpu_core_realize_child:
Object 0x55cee1f55160 is not an instanc
> -Original Message-
> From: alistai...@gmail.com [mailto:alistai...@gmail.com] On Behalf Of
> Alistair Francis
> Sent: Friday, August 11, 2017 4:23 PM
> To: Alistair Francis ; Portia Stephens
>
> Cc: qemu-devel@nongnu.org Developers ;
> Peter Maydell ; Edgar Iglesias
> ; Edgar Iglesias ;
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