This moves pci_dev->name initialization earlier so
pci_dev->bus_master_as could get a name instead of an empty string.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Alexey Kardashevskiy
---
Changes:
v2:
* fixed mistype in the commit log
* added "rb"
---
hw/pci/pci.c | 2 +-
1 file change
On Fri, Oct 13, 2017 at 11:14:03AM -0600, Alex Williamson wrote:
> On Fri, 13 Oct 2017 18:01:44 +0100
> "Dr. David Alan Gilbert" wrote:
>
> > * Prasad Singamsetty (prasad.singamse...@oracle.com) wrote:
> > > Hi,
> > >
> > > I am new to the alias. I have some questions on this subject
> > > and s
On Sun, Oct 15, 2017 at 02:24:17PM +1100, Alexey Kardashevskiy wrote:
> On 03/10/17 13:10, Alexey Kardashevskiy wrote:
> > On 15/09/17 16:35, Alexey Kardashevskiy wrote:
> >> This moves pci_dev->name initialization earlier so
> >> pci_dev->bus_master_as could get a name instead of an empty string.
From: Laurent Vivier
Since 4458fb3a79 (pc: Eliminate pc_default_machine_options()),
hot_add_cpu is set in pc_machine_class_init(), so we don't
need to set it in pc_q35_machine_options(), pc_i440fx_machine_options()
and xenfv_machine_options(), except to clear it in
pc_i440fx_1_4_machine_opt().
S
From: Eduardo Habkost
We don't touch isapc when we change guest ABI and add new entries
to PC_COMPAT_* or new PCMachineClass compat flags. This means
isapc never guaranteed guest ABI and cross-QEMU-version live
migration compatibility. There's no point in keeping code for
kvm-pv-eoi and APIC ID
On 15/10/17 14:31, Michael S. Tsirkin wrote:
> On Sun, Oct 15, 2017 at 02:24:17PM +1100, Alexey Kardashevskiy wrote:
>> On 03/10/17 13:10, Alexey Kardashevskiy wrote:
>>> On 15/09/17 16:35, Alexey Kardashevskiy wrote:
This moves pci_dev->name initialization earlier so
pci_dev->bus_master_
On Sun, Oct 15, 2017 at 02:24:17PM +1100, Alexey Kardashevskiy wrote:
> On 03/10/17 13:10, Alexey Kardashevskiy wrote:
> > On 15/09/17 16:35, Alexey Kardashevskiy wrote:
> >> This moves pci_dev->name initialization earlier so
> >> pci_dev->bus_master_as could get a name instead of an empty string.
From: Eduardo Habkost
xen-pt doesn't set the is_express field, but is supposed to be
able to handle PCI Express devices too. Mark it as hybrid.
Suggested-by: Jan Beulich
Signed-off-by: Eduardo Habkost
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/xen/xen_pt.c | 1
From: Eduardo Habkost
Add INTERFACE_CONVENTIONAL_PCI_DEVICE to all direct subtypes of
TYPE_PCI_DEVICE, except:
1) The ones that already have INTERFACE_PCIE_DEVICE set:
* base-xhci
* e1000e
* nvme
* pvscsi
* vfio-pci
* virtio-pci
* vmxnet3
2) base-pci-bridge
Not all PCI bridges are Conventiona
From: Wolfgang Bumiller
While changing the s/g list allocation, commit 3b3b0628
also changed the descriptor counting to count iovec entries
as split by cpu_physical_memory_map(). Previously only the
actual descriptor entries were counted and the split into
the iovec happened afterwards in virtque
From: Alexey Kardashevskiy
The modern bar is accessed now via yet another address space created just
for that purpose and it does not really need FlatView and dispatch tree
as it has a single memory region so it is just a waste of memory. Things
get even worse when there are dozens or hundreds of
From: Eduardo Habkost
The following devices support both PCI Express and Conventional
PCI, by including special code to handle the QEMU_PCI_CAP_EXPRESS
flag and/or conditional pcie_endpoint_cap_init() calls:
* vfio-pci (is_express=1, but legacy PCI handled by
vfio_populate_device())
* vmxnet3
From: Eduardo Habkost
Make sure we don't forget to add the Conventional PCI or PCI
Express interface names on PCI device classes in the future.
Signed-off-by: Eduardo Habkost
Revieed-by: David Gibson
Reviewed-by: Marcel Apfelbaum
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsir
From: Matt Redfearn
PCIe busses are always little endian, so set the endianness of the
memory region to little endian rather than native such that operations
work as expected on big endian targets.
Signed-off-by: Matt Redfearn
Reviewed-by: Marcel Apfelbaum
Reviewed-by: Michael S. Tsirkin
Sign
From: Marcel Apfelbaum
IO_LIMIT and IO_BASE registers should not be writable if
gen_pcie_root_port's io-reserve property is set to 0.
The COMMAND register should have the IO flag read only.
Signed-off-by: Marcel Apfelbaum
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
From: Eduardo Habkost
Those two interfaces will be used to indicate which device types
support Conventional PCI or PCI Express buses. Management
software will be able to use the qom-list-types QMP command to
query that information.
Signed-off-by: Eduardo Habkost
Reviewed-by: David Gibson
Revi
From: Mark Cave-Ayland
Whilst the underlying PCI bridge implementation supports 32-bit PCI IO
accesses, unfortunately they are truncated at the legacy 64K limit.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
-
From: Eduardo Habkost
Change all devices that set is_express=1 to implement
INTERFACE_PCIE_DEVICE.
Cc: Keith Busch
Cc: Kevin Wolf
Cc: Max Reitz
Cc: Dmitry Fleytman
Cc: Jason Wang
Cc: "Michael S. Tsirkin"
Cc: Marcel Apfelbaum
Cc: Paul Burton
Cc: Paolo Bonzini
Cc: Hannes Reinecke
Cc: qem
From: Marc-André Lureau
Proposing myself, since I have some familiarity with the code now.
Signed-off-by: Marc-André Lureau
Acked-by: Laszlo Ersek
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git
From: Aleksandr Bezzubikov
QEMU with the pcie-pci-bridge device crashes if the guest board doesn't support
MSI,
e.g. 'qemu-system-ppc64 -M prep -device pcie-pci-bridge'.
This is caused by wrong pcie-pci-bridge instantiation error handling. This
patch fixes this issue
by falling back to legacy I
From: "Dr. David Alan Gilbert"
Convert the 'modern_state' part of virtio-pci to modern migration
macros.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/virtio/virtio-pci.c | 108 +
On 03/10/17 13:10, Alexey Kardashevskiy wrote:
> On 15/09/17 16:35, Alexey Kardashevskiy wrote:
>> This moves pci_dev->name initialization earlier so
>> pci_dev->bus_master_as could get a name instead of an empty string.
>>
>> Signed-off-by: Alexey Kardashevskiy
>> Reviewed-by: Philippe Mathieu-Da
From: Marc-André Lureau
Reintroduce the write callback that was removed when write support was
removed in commit 023e3148567ac898c7258138f8e86c3c2bb40d07.
Contrary to the previous callback implementation, the write_cb
callback is called whenever a write happened, so handlers must be
ready to han
From: Marc-André Lureau
kdump header provides offset and size of the vmcoreinfo content,
append it if available (skip the ELF note header).
crash-7.1.9 was the first version that started looking in the
vmcoreinfo data for phys_base instead of in the kdump_sub_header.
Signed-off-by: Marc-André L
From: Marc-André Lureau
Add a vmcoreinfo ELF note in the dump if vmcoreinfo device has the
memory location details.
Signed-off-by: Marc-André Lureau
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
scripts/dump-guest-memory.py | 61 +++
From: Thomas Huth
The pxe-test is a very good test to excercise NICs, thus we should use
it to test all NICs that can be used by the BIOS for booting via network.
However, to avoid that the default testing time increases too much, the
additional NICs are only tested in the "make check SPEED=slow"
From: Marc-André Lureau
If the guest note is VMCOREINFO, try to get phys_base from it.
Signed-off-by: Marc-André Lureau
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
docs/specs/vmcoreinfo.txt | 8 +++
dump.c| 56 +++
From: Marc-André Lureau
Read the guest ELF PT_NOTE from guest memory when fw_cfg
etc/vmcoreinfo entry provides the location, and write it as an
additional note in the dump.
Signed-off-by: Marc-André Lureau
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
include/sysemu/d
From: Eduardo Habkost
On commit f8cd1b02 ("pci: Convert to realize"), no error_set*()
call was added for the pcie_chassis_add_slot() error case.
pcie_chassis_add_slot() errors get ignored, making QEMU crash
later. e.g.:
$ qemu-system-x86_64 -device ioh3420 -device xio3130-downstream
qemu-sy
From: Felipe Franciosi
vhost_log_put() is called to decomission the dirty log between qemu and
a vhost device when stopping the device. Such a call can happen from
migration_completion().
Present code sets dev->log_size to zero too early in vhost_log_put(),
causing the sync check to always retur
From: Mao Zhongyi
ioh3420_interrupts_init() pass error message to local_err, then
propagate it to errp by error_propagate(), which is not necessary.
So eliminate it and pass errp directly instead of local_err.
Cc: "Michael S. Tsirkin"
Cc: Marcel Apfelbaum
Signed-off-by: Mao Zhongyi
Reviewed-b
From: Marc-André Lureau
See docs/specs/vmcoreinfo.txt for details.
"etc/vmcoreinfo" fw_cfg entry is added when using "-device vmcoreinfo".
Signed-off-by: Marc-André Lureau
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
docs/specs/vmcoreinfo.txt| 41 +++
The following changes since commit f90ea7ba7c5ae7010ee0ce062207ae42530f57d6:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20171012'
into staging (2017-10-12 17:06:50 +0100)
are available in the git repository at:
git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags
Hi,
This series failed build test on s390x host. Please find the details below.
Type: series
Message-id: 1508004545-28578-1-git-send-email-mark.cave-ayl...@ilande.co.uk
Subject: [Qemu-devel] [PATCHv2 00/13] sun4m: sparc32_dma tidy-ups
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will b
On Tue, Oct 10, 2017 at 03:01:10PM -0300, Eduardo Habkost wrote:
> On Tue, Oct 10, 2017 at 04:06:28PM +0100, Daniel P. Berrange wrote:
> > On Tue, Oct 10, 2017 at 05:00:18PM +0200, Marc-André Lureau wrote:
> > > Hi
> > >
> > > On Tue, Oct 10, 2017 at 10:31 AM, Daniel P. Berrange
> > > wrote:
> >
On Tue, Oct 10, 2017 at 03:01:10PM -0300, Eduardo Habkost wrote:
> On Tue, Oct 10, 2017 at 04:06:28PM +0100, Daniel P. Berrange wrote:
> > On Tue, Oct 10, 2017 at 05:00:18PM +0200, Marc-André Lureau wrote:
> > > Hi
> > >
> > > On Tue, Oct 10, 2017 at 10:31 AM, Daniel P. Berrange
> > > wrote:
> >
On Fri, Oct 13, 2017 at 01:31:44PM +0200, Greg Kurz wrote:
> The current code assumes that only the CPU core object holds a
> reference on each individual CPU object, and happily frees their
> allocated memory when the core is unrealized. This is dangerous
> as some other code can legitimely keep a
From: Vladimir Sementsov-Ogievskiy
In following patch nbd_receive_reply will be used both for simple
and structured reply header receiving.
NBDReply is altered into union of simple reply header and structured
reply chunk header, simple error translation moved to block/nbd-client
to be consistent
From: Vladimir Sementsov-Ogievskiy
Split out nbd_request_simple_option to be reused for structured reply
option.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Eric Blake
---
v4: reduce redundant traces, typo fix in commit message
---
nbd/client.c | 69 +++
From: Vladimir Sementsov-Ogievskiy
Minimal implementation of structured read: one structured reply chunk,
no segmentation.
Minimal structured error implementation: no text message.
Support DF flag, but just ignore it, as there is no segmentation any
way.
Signed-off-by: Vladimir Sementsov-Ogievsk
Upcoming patches will implement the NBD structured reply
extension [1] for both client and server roles. Declare the
constants, structs, and lookup routines that will be valuable
whether the server or client code is backported in isolation.
This includes moving one constant from an internal heade
An upcoming change to block/nbd-client.c will want to read the
tail of a structured reply chunk directly from the wire. Move
this function to make it easier.
Based on a patch from Vladimir Sementsov-Ogievskiy.
Signed-off-by: Eric Blake
---
include/block/nbd.h | 10 ++
nbd/nbd-internal.
This is needed in preparation for structured reply handling,
as we will be performing the translation from NBD error to
system errno value higher in the stack at block/nbd-client.c.
---
include/block/nbd.h | 13 +
nbd/nbd-internal.h | 12
nbd/client.c| 32
The NBD spec permits including a human-readable error string if
structured replies are in force, so we might as well send the
client the message that we logged on any error.
Signed-off-by: Eric Blake
---
nbd/server.c | 22 --
nbd/trace-events | 2 +-
2 files changed, 17
As mentioned in my review of Vladimir's v3 of this series [1],
I had enough tweaks during my review that it's easier to repost
things for another round of discussion, adding some of my patches
in between his. I did not include his 13/13 "nbd: Minimal structured
read for client", where I had a lot
NBD errors were originally sent over the wire based on Linux errno
values; but not all the world is Linux, and not all platforms share
the same values. Since a number isn't very easy to decipher on all
platforms, update the trace messages to include the name of NBD
errors being sent/received over
From: Vladimir Sementsov-Ogievskiy
Send qiov via qio_channel_writev_all instead of calling nbd_write twice
with a cork.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Message-Id: <20171012095319.136610-8-vsement...@virtuozzo.com>
[eblake: rebase to tweaks earlier in series]
Signed-off-by: Eric Bla
From: Vladimir Sementsov-Ogievskiy
Prepare indenting for the following commit.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
Message-Id: <20171012095319.136610-9-vsement...@virtuozzo.com>
Signed-off-by: Eric Blake
---
include/block/nbd.h | 15 ---
nbd/nbd-in
From: Vladimir Sementsov-Ogievskiy
NBDReply structure will be upgraded in future patches to handle both
simple and structured replies and will be used only in the client
Signed-off-by: Vladimir Sementsov-Ogievskiy
Message-Id: <20171012095319.136610-6-vsement...@virtuozzo.com>
[eblake: rebase to
From: Vladimir Sementsov-Ogievskiy
Pass client and buffer (*data) parameters directly, to make the function
consistent with further structured reply sending functions.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Message-Id: <20171012095319.136610-7-vsement...@virtuozzo.com>
Signed-off-by: Eric
From: Vladimir Sementsov-Ogievskiy
To be consistent when their _structured_ analogs will be introduced.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
Message-Id: <20171012095319.136610-4-vsement...@virtuozzo.com>
[eblake: also tweak trace message contents]
Signed-off-by:
From: Vladimir Sementsov-Ogievskiy
Also improve the assertion: check that qiov is NULL for other commands
than CMD_READ and CMD_WRITE.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
Message-Id: <20171012095319.136610-2-vsement...@virtuozzo.com>
Signed-off-by: Eric Blake
-
From: Vladimir Sementsov-Ogievskiy
Use packed structure instead of pointer arithmetics.
Also, merge two redundant traces into one.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Message-Id: <20171012095319.136610-5-vsement...@virtuozzo.com>
[eblake: tweak and mention impact on traces, fix errp us
From: Vladimir Sementsov-Ogievskiy
Pass handle parameter directly, as the whole request isn't needed.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
Message-Id: <20171012095319.136610-3-vsement...@virtuozzo.com>
Signed-off-by: Eric Blake
---
block/nbd-client.c | 8 --
The following changes since commit f90ea7ba7c5ae7010ee0ce062207ae42530f57d6:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20171012'
into staging (2017-10-12 17:06:50 +0100)
are available in the git repository at:
git://repo.or.cz/qemu/ericb.git tags/pull-nbd-2017-10-1
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
Message-Id: <20171006235023.11952-22-f4...@amsat.org>
Signed-off-by: Eric Blake
---
nbd/server.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/nbd/server.c b/nbd/server.c
index 993ade30bb..b74cc6ab7e 100644
---
On Fri, Oct 13, 2017 at 03:53:26PM +0800, Haozhong Zhang wrote:
> On 10/12/17 17:45 +0200, Paolo Bonzini wrote:
> > On 12/10/2017 14:45, Haozhong Zhang wrote:
> > > Basically, QEMU builds two ROMs for guest, /rom@etc/acpi/tables and
> > > /rom@etc/table-loader. The former is unstructured to guest,
On Fri, Oct 13, 2017 at 03:46:39PM -0700, Stefano Stabellini wrote:
> On Fri, 13 Oct 2017, Jan Beulich wrote:
> > >>> On 13.10.17 at 13:13, wrote:
> > > To Jan, Andrew, Stefano and Anthony,
> > >
> > > what do you think about allowing QEMU to build the entire guest ACPI
> > > and letting SeaBIOS
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1508006342-5304-1-git-send-email-mark.cave-ayl...@ilande.co.uk
Subject: [Qemu-devel] [PATCHv3 00/13] sun4m: sparc32_dma tidy-ups
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=b
This makes it possible to reference the esp device from the espdma device as
required, and by wiring up the device ourselves in sun4m.c we can drop use
of the esp_init() function.
Signed-off-by: Mark Cave-Ayland
---
hw/dma/sparc32_dma.c | 26 ++
hw/sparc/sun4m
Create a new SPARC32_DMA container object (including an appropriate container
memory region) and add instances of the SPARC32_ESPDMA_DEVICE and
SPARC32_LEDMA_DEVICE as child objects. The benefit is that most of the gpio
wiring complexity between esp/espdma and lance/ledma is now hidden within the
S
This is surprisingly useful when trying to debug DMA issues.
Signed-off-by: Mark Cave-Ayland
---
hw/dma/sparc32_dma.c |8
hw/dma/trace-events |8
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c
index bb7d70a..f
This enables them to be used outside of lance.c.
Signed-off-by: Mark Cave-Ayland
CC: Jason Wang
---
hw/net/lance.c |9 -
include/hw/sparc/sun4m.h | 13 +
2 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/hw/net/lance.c b/hw/net/lance.c
index 92b
This makes it possible to reference the lance device from the ledma device as
required.
Signed-off-by: Mark Cave-Ayland
---
hw/dma/sparc32_dma.c | 23 ++-
hw/sparc/sun4m.c | 31 +++
include/hw/sparc/sparc32_dma.h |3
This hack originated from before the memory region API was introduced, and
increased the size of the ledma DMA device to capture incorrect accesses
beyond the end of the ledma device. A full analysis can be found on Artyom's
blog at
http://tyom.blogspot.co.uk/2010/10/bug-in-all-solaris-versions-af
Also update the function names to match as appropriate. While we're
here rename the type from sparc32_dma to sparc32-dma in order to
match the current QOM convention.
Signed-off-by: Mark Cave-Ayland
---
hw/dma/sparc32_dma.c | 67 +-
hw/sparc/sun4
This enables them to be used outside of esp.c.
Signed-off-by: Mark Cave-Ayland
CC: Paolo Bonzini
---
hw/scsi/esp.c | 13 -
include/hw/scsi/esp.h | 14 ++
2 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 22c2
This is in preparation to allow the type to be used elsewhere.
Signed-off-by: Mark Cave-Ayland
---
hw/dma/sun4m_iommu.c | 14 --
include/hw/sparc/sun4m.h | 16
2 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/hw/dma/sun4m_iommu.c b/hw/dma/sun4
Due to slight differences in behaviour accessing the registers for the
esp and le devices, create two separate SPARC32_DMA_DEVICE types and
update the sun4m machine to use.
Note that by using different device types we already know the size of
the register block and the value of is_ledma at init ti
This enables us to remove the last remaining (opaque) qdev property. Whilst we
are here, also update iommu_init() to use TYPE_SUN4M_IOMMU instead of a
hardcoded string.
Signed-off-by: Mark Cave-Ayland
---
hw/dma/sparc32_dma.c | 13 +
hw/sparc/sun4m.c |4 ++--
2 files change
This patchset aims to tidy-up the sparc32_dma code by improving the
modelling of the espdma/ledma devices using both QOM and the memory
API which didn't exist when the code was first written.
The result is that it is now possible to remove both the iommu_opaque
and is_ledma workarounds from the co
By using the sysbus interface it is possible to wire up the esp/le devices
to the sun4m DMA controller directly during sun4m_hw_init() instead of
passing qemu_irqs into the sparc32_dma_init() function.
This is an intermediate step to allow further reorganisation as more logic
is moved into the rel
Signed-off-by: Mark Cave-Ayland
---
hw/dma/sparc32_dma.c | 34 --
include/hw/sparc/sparc32_dma.h | 37 +
2 files changed, 37 insertions(+), 34 deletions(-)
diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c
i
Hi,
This series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 1508004545-28578-1-git-send-email-mark.cave-ayl...@ilande.co.uk
Subject: [Qemu-devel] [PATCHv2 00/13]
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1508004545-28578-1-git-send-email-mark.cave-ayl...@ilande.co.uk
Subject: [Qemu-devel] [PATCHv2 00/13] sun4m: sparc32_dma tidy-ups
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=
Signed-off-by: Mark Cave-Ayland
---
hw/dma/sun4m_iommu.c | 62 ++
include/hw/sparc/sun4m.h |5
2 files changed, 67 insertions(+)
diff --git a/hw/dma/sun4m_iommu.c b/hw/dma/sun4m_iommu.c
index 840064b..ce21a22 100644
--- a/hw/dma/sun4m_io
Signed-off-by: Mark Cave-Ayland
---
hw/dma/sparc32_dma.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c
index fbb072a..5438831 100644
--- a/hw/dma/sparc32_dma.c
+++ b/hw/dma/sparc32_dma.c
@@ -29,6 +29,7 @@
#inc
With the switch to the IOMMU memory region and DMA API, this is no longer
required.
Signed-off-by: Mark Cave-Ayland
---
hw/dma/sun4m_iommu.c | 33 -
include/hw/sparc/sun4m.h | 16
2 files changed, 49 deletions(-)
diff --git a/hw/dma/sun4m
The original sun4m IOMMU/DMA code dates from before the introduction of the QEMU
memory region API (in particular IOMMU memory regions) and the DMA API.
This patchset removes these sun4m-specific implementations and replaces them
with
the more up-to-date QEMU APIs instead.
Signed-off-by: Mark Ca
This hack originated from before the memory region API was introduced, and
increased the size of the ledma DMA device to capture incorrect accesses
beyond the end of the ledma device. A full analysis can be found on Artyom's
blog at
http://tyom.blogspot.co.uk/2010/10/bug-in-all-solaris-versions-af
This makes it possible to reference the lance device from the ledma device as
required.
Signed-off-by: Mark Cave-Ayland
---
hw/dma/sparc32_dma.c | 23 ++-
hw/sparc/sun4m.c | 31 +++
include/hw/sparc/sparc32_dma.h |3
This enables them to be used outside of lance.c.
Signed-off-by: Mark Cave-Ayland
CC: Jason Wang
---
hw/net/lance.c |9 -
include/hw/sparc/sun4m.h | 13 +
2 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/hw/net/lance.c b/hw/net/lance.c
index 92b
This makes it possible to reference the esp device from the espdma device as
required, and by wiring up the device ourselves in sun4m.c we can drop use
of the esp_init() function.
Signed-off-by: Mark Cave-Ayland
---
hw/dma/sparc32_dma.c | 26 ++
hw/sparc/sun4m
This is in preparation to allow the type to be used elsewhere.
Signed-off-by: Mark Cave-Ayland
---
hw/dma/sun4m_iommu.c | 14 --
include/hw/sparc/sun4m.h | 16
2 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/hw/dma/sun4m_iommu.c b/hw/dma/sun4
This is surprisingly useful when trying to debug DMA issues.
Signed-off-by: Mark Cave-Ayland
---
hw/dma/sparc32_dma.c |8
hw/dma/trace-events |8
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c
index bb7d70a..f
Create a new SPARC32_DMA container object (including an appropriate container
memory region) and add instances of the SPARC32_ESPDMA_DEVICE and
SPARC32_LEDMA_DEVICE as child objects. The benefit is that most of the gpio
wiring complexity between esp/espdma and lance/ledma is now hidden within the
S
Signed-off-by: Mark Cave-Ayland
---
hw/dma/sparc32_dma.c | 34 --
include/hw/sparc/sparc32_dma.h | 37 +
2 files changed, 37 insertions(+), 34 deletions(-)
diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c
i
Also update the function names to match as appropriate. While we're
here rename the type from sparc32_dma to sparc32-dma in order to
match the current QOM convention.
Signed-off-by: Mark Cave-Ayland
---
hw/dma/sparc32_dma.c | 67 +-
hw/sparc/sun4
This enables them to be used outside of esp.c.
Signed-off-by: Mark Cave-Ayland
CC: Paolo Bonzini
---
hw/scsi/esp.c | 13 -
include/hw/scsi/esp.h | 13 +
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 22c2d
This enables us to remove the last remaining (opaque) qdev property. Whilst we
are here, also update iommu_init() to use TYPE_SUN4M_IOMMU instead of a
hardcoded string.
Signed-off-by: Mark Cave-Ayland
---
hw/dma/sparc32_dma.c | 13 +
hw/sparc/sun4m.c |4 ++--
2 files change
Due to slight differences in behaviour accessing the registers for the
esp and le devices, create two separate SPARC32_DMA_DEVICE types and
update the sun4m machine to use.
Note that by using different device types we already know the size of
the register block and the value of is_ledma at init ti
This patchset aims to tidy-up the sparc32_dma code by improving the
modelling of the espdma/ledma devices using both QOM and the memory
API which didn't exist when the code was first written.
The result is that it is now possible to remove both the iommu_opaque
and is_ledma workarounds from the co
By using the sysbus interface it is possible to wire up the esp/le devices
to the sun4m DMA controller directly during sun4m_hw_init() instead of
passing qemu_irqs into the sparc32_dma_init() function.
This is an intermediate step to allow further reorganisation as more logic
is moved into the rel
On 10/10/17 09:21, Artyom Tarasenko wrote:
> On Mon, Oct 9, 2017 at 11:06 PM, Mark Cave-Ayland
> wrote:
>> This patchset aims to tidy-up the sparc32_dma code by improving the
>> modelling of the espdma/ledma devices using both QOM and the memory
>> API which didn't exist when the code was first w
On 14 October 2017 at 17:38, Philippe Mathieu-Daudé wrote:
>>> Hello, is it possible to run (or rebuild modifying build flags) QEMU
>>> without support for X11 window system integration?
>>
>> ./configure --disable-gtk --disable-sdl --disable-opengl
>
> Is there some interest in adding a simpler -
Hi Paolo,
On 10/12/2017 10:54 AM, Paolo Bonzini wrote:
> Add trace events to the PCH watchdog timer, it can be useful to see how
> the guest is using it.
>
> Signed-off-by: Paolo Bonzini
> ---
> hw/acpi/tco.c| 11 +--
> hw/acpi/trace-events | 4
> 2 files changed, 13 inser
Hi Stefan,
On 10/13/2017 02:48 AM, Stefan Weil wrote:
> diff --git a/util/oslib-posix.c b/util/oslib-posix.c
> index 80086c549f..beef148c96 100644
> --- a/util/oslib-posix.c
> +++ b/util/oslib-posix.c
> @@ -59,8 +59,8 @@
>
> struct MemsetThread {
> char *addr;
> -uint64_t numpages;
> -
>> Hello, is it possible to run (or rebuild modifying build flags) QEMU
>> without support for X11 window system integration?
>
> ./configure --disable-gtk --disable-sdl --disable-opengl
Is there some interest in adding a simpler --disable-x11 option?
Cc: trivial
On 10/13/2017 06:30 PM, Emilio G. Cota wrote:
> The header file was introduced by fbcc3e5 ("qemu-thread: optimize QemuLockCnt
> with futexes on Linux", 2017-01-16) without header guards. Add them.
>
> Signed-off-by: Emilio G. Cota
Reviewed-by: Philippe Mathieu-Daudé
> ---
> inclu
On 14 October 2017 at 00:21, Eduardo Habkost wrote:
> I don't believe the spec restricts that, but I don't see why it
> would be useful to load an ELF file that doesn't match the target
> architecture (e.g. loading non-x86 ELF files on a x86 machine
> like PC).
Agreed. If we have non i386 boards
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