On Macintosh keyboards there is a key called fn that is used to give the
function keys more functionality. Does this key exist in the keyboard keys
database?
Also could keys F16 to F24 (Q_KEY_CODE_F16 to Q_KEY_CODE_F24) be added to the
database?
Thank you.
It was only for userspace i8259. Move it to general code so that
kvm-i8259 can also use it in the future.
Signed-off-by: Peter Xu
---
hw/intc/i8259.c | 37 +
hw/intc/i8259_common.c | 41 +
inclu
Let's leverage the i8259 common code for kvm-i8259 too.
I think it's still possible that stats can lost when i8259 is in kernel
and meanwhile when irqfd is used, e.g., by vfio or vhost devices.
However that should be rare IMHO since they should be using MSIs mostly
if they really want performance
Now both classes (i8259, i8259-kvm) support this. Move this upper to
the common class code.
Signed-off-by: Peter Xu
---
hw/i386/kvm/i8259.c| 7 ---
hw/intc/i8259.c| 7 ---
hw/intc/i8259_common.c | 7 +++
3 files changed, 7 insertions(+), 14 deletions(-)
diff --git a/hw/
It's mostly a cleanup, but patch 4 allows kvm-i8259 to support "info
pic" and "info irq" too.
I'm thinking whether it'll be good to move on this work to spread
these commands to IOAPICs too, by removing "info ioapic" command and
let "info pic" dump the things altogether (after all I think ioapic i
One thing to mention is that in pic_set_irq() I need to uncomment a few
lines in the macros to make sure IRQ value calculation is correct.
Signed-off-by: Peter Xu
---
hw/intc/i8259.c | 26 +++---
hw/intc/trace-events | 7 +++
2 files changed, 18 insertions(+), 15 de
It's not really scary to even enable it forever. After all it's i8259,
and it's even not the kernel one.
Then we can remove quite a few of lines to make it cleaner. And "info
irq" will always work for it.
Signed-off-by: Peter Xu
---
hw/intc/i8259.c | 18 +-
1 file changed, 1 i
I haven't remembered to reset those interrupts in a year, but I also
haven't remembered to update my drivers in about as long, so I could be
still on the right setting. I've also been on AMD for that year, and I
don't remember whether this bug applies to modern AMD cards.
--
You received this bug
Updating NVIDIA drivers in the guest also seems to disable MSI for some
reason. Oddly enough I did not run into the host hard locking though.
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https://bugs.launchpad.net/bugs/1580459
Tit
Enabling MSI interrupts works for me. One note is that Windows updates
will sometimes revert the changes so if this starts breaking after an
update you may need to re-apply the registry changes.
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devel-ml, which is subscribed
On 12/08/2017 07:46 PM, John Snow wrote:
>
>
> On 11/22/2017 09:08 PM, Max Reitz wrote:
>> Tests 080, 130, 137, and 176 simply do not work with compat=0.10 for the
>> reasons stated there.
>>
>> 177 is a bit more interesting: Originally, it was actually very much
>> intended to work with compat=
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> +static void multifd_new_channel_async(QIOTask *task, gpointer opaque)
>> +{
>> +MultiFDSendParams *p = opaque;
>> +QIOChannel *sioc = QIO_CHANNEL(qio_task_get_source(task));
>> +Error *local_err;
>
> Do
On 12/09/2017 06:31 AM, Vladimir Sementsov-Ogievskiy wrote:
> 07.12.2017 23:30, Eric Blake wrote:
>> We are gradually moving away from sector-based interfaces, towards
>> byte-based. Update the parallels driver accordingly. Note that
>> the internal function block_status() is still sector-based,
On Friday, December 8, 2017 4:34 PM, Stefan Hajnoczi wrote:
> On Fri, Dec 8, 2017 at 6:43 AM, Wei Wang wrote:
> > On 12/08/2017 07:54 AM, Michael S. Tsirkin wrote:
> >>
> >> On Thu, Dec 07, 2017 at 06:28:19PM +, Stefan Hajnoczi wrote:
> >>>
> >>> On Thu, Dec 7, 2017 at 5:38 PM, Michael S. Tsir
On Friday, December 8, 2017 10:28 PM, Michael S. Tsirkin wrote:
> On Fri, Dec 08, 2017 at 06:08:05AM +, Stefan Hajnoczi wrote:
> > On Thu, Dec 7, 2017 at 11:54 PM, Michael S. Tsirkin
> wrote:
> > > On Thu, Dec 07, 2017 at 06:28:19PM +, Stefan Hajnoczi wrote:
> > >> On Thu, Dec 7, 2017 at 5
> +static const VMStateDescription vmstate_spapr_xive = {
> +.name = TYPE_SPAPR_XIVE,
> +.version_id = 1,
> +.minimum_version_id = 1,
> +.needed = vmstate_spapr_xive_needed,
> +.fields = (VMStateField[]) {
> +VMSTATE_UINT32_EQUAL(nr_irqs, sPAPRXive, NULL),
> +VMS
07.12.2017 23:30, Eric Blake wrote:
We are gradually moving away from sector-based interfaces, towards
byte-based. Update the vpc driver accordingly. Drop the now-unused
get_sector_offset().
Signed-off-by: Eric Blake
---
v5: fix incorrect rounding in 'map' and bad loop condition [Vladimir]
v
09.12.2017 13:15, Vladimir Sementsov-Ogievskiy wrote:
07.12.2017 23:30, Eric Blake wrote:
We are gradually moving away from sector-based interfaces, towards
byte-based. Now that the block layer exposes byte-based allocation,
it's time to tackle the drivers. Add a new callback that operates
on a
07.12.2017 23:30, Eric Blake wrote:
We are gradually moving away from sector-based interfaces, towards
byte-based. Now that all drivers have been updated to provide the
byte-based .bdrv_co_block_status(), we can delete the sector-based
interface.
Signed-off-by: Eric Blake
Reviewed-by: Vladim
07.12.2017 23:30, Eric Blake wrote:
We are gradually moving away from sector-based interfaces, towards
byte-based. Update the vmdk driver accordingly. Drop the
now-unused vmdk_find_index_in_cluster().
Also, fix a pre-existing bug: if find_extent() fails (unlikely,
since the block layer did a b
07.12.2017 23:30, Eric Blake wrote:
We are gradually moving away from sector-based interfaces, towards
byte-based. Update the parallels driver accordingly. Note that
the internal function block_status() is still sector-based, because
it is still in use by other sector-based functions; but that'
07.12.2017 23:30, Eric Blake wrote:
We are gradually moving away from sector-based interfaces, towards
byte-based. Update the gluster driver accordingly.
In want_zero mode, we continue to report fine-grained hole
information (the caller wants as much mapping detail as possible);
but when not in
07.12.2017 23:30, Eric Blake wrote:
We are gradually moving away from sector-based interfaces, towards
byte-based. Update the file protocol driver accordingly.
In want_zero mode, we continue to report fine-grained hole
information (the caller wants as much mapping detail as possible);
but when
On Fri 08 Dec 2017 08:13:48 PM CET, John Snow wrote:
qemu_io('-f', iotests.imgfmt,
-'-c', 'write -P %d %d %d' % (i, i*1024*1024, num_kb *
1024),
+'-c', 'write -P 0xFF %dk %dk' % (i * 512, num_kb),
>>>
>>> I guess changing f
07.12.2017 23:30, Eric Blake wrote:
We are gradually moving away from sector-based interfaces, towards
byte-based. Now that the block layer exposes byte-based allocation,
it's time to tackle the drivers. Add a new callback that operates
on as small as byte boundaries. Subsequent patches will the
08.12.2017 20:33, Dr. David Alan Gilbert wrote:
* Vladimir Sementsov-Ogievskiy (vsement...@virtuozzo.com) wrote:
Allow user to specify name for new export, to not reuse internal
node name and to not show it to clients.
This also allows creating several exports per device.
Signed-off-by: Vladim
Marc-André Lureau writes:
> Signed-off-by: Marc-André Lureau
> ---
> tests/Makefile.include| 2 ++
> tests/qapi-schema/struct-if-invalid.err | 1 +
> tests/qapi-schema/struct-if-invalid.exit | 1 +
> tests/qapi-schema/struct-if-invalid.json | 3 +++
> tests/qapi-sche
Signed-off-by: Cédric Le Goater
---
hw/ppc/spapr.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 867c9d759f3b..e52c510812d9 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -989,10 +989,11 @@ static void spa
On sPAPR, the creation of the interrupt presenter depends on some of
the machine attributes. When the XIVE exploitation interrupt mode is
available, this will get more complex. So provide a machine-level
helper to isolate the process and hide the details to the sPAPR core
realize function.
Signed-
The XIVE object has its own set of qirqs which is to be used when the
XIVE exploitation interrupt mode is activated.
Signed-off-by: Cédric Le Goater
---
Changes since v1:
- introduced a spapr_xive_qirq() helper
hw/intc/spapr_xive.c| 12
hw/ppc/spapr.c | 4
The XIVE interface for the guest is described in the device tree under
the "interrupt-controller" node. A couple of new properties are
specific to XIVE :
- "reg"
contains the base address and size of the thread interrupt
managnement areas (TIMA), also called rings, for the User level and
The sPAPRXive object is designed to be always available, so it is
created unconditionally on newer machines. Depending on the
configuration and the guest capabilities, the CAS negotiation process
will decide which interrupt mode to activate: legacy or XIVE
exploitation.
The XIVE model makes use of
The different XIVE virtualization engines (sources and event queues)
are configured with a set of Hypervisor calls :
- H_INT_GET_SOURCE_INFO
used to obtain the address of the MMIO page of the Event State
Buffer (PQ bits) entry associated with the source.
- H_INT_SET_SOURCE_CONFIG
ass
The XIVE exploitation interrupt mode will be enabled for newer
machines and disabled for older ones. Also provide a command line
machine option to switch XIVE off on newer machines if needed.
Signed-off-by: Cédric Le Goater
---
hw/intc/spapr_xive.c | 10 ++
hw/ppc/spapr.c | 35
The 'sent' status of the LSI interrupt source is modeled with the 'P'
bit of the ESB and the assertion status of the source is maintained in
an array under the main sPAPRXive object. The type of the source is
stored in the same array for practical reasons.
The OS will use the H_INT_GET_SOURCE_INFO
When the XIVE exploitation interrupt mode is activated, the machine
needs to expose to the guest the MMIO regions used by the controller :
- Event State Buffers
- Thread Interrupt Management Area for the OS and User views
Migration will also need to reflect the current interrupt mode in use.
Modify the InterruptStatsProvider output to reflect the interrupt mode
currently in use by the machine.
Signed-off-by: Cédric Le Goater
---
hw/ppc/spapr.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 4d7a3d64e51e..867c9d7
Once an event has been routed, the XIVE virtualization presenter
engine raises the bit corresponding to the priority of the pending
interrupt in the register IBP (Interrupt Pending Buffer). The Pending
Interrupt Priority Register (PIPR) is also updated using the IPB. It
contains the priority of the
With the POWER9 processor comes a new interrupt controller called
XIVE. It is composed of three sub-engines :
- Interrupt Virtualization Source Engine (IVSE). These are in PHBs,
in the main controller for the IPIS and in the PSI host
bridge. They are configured to feed the IVRE with even
Each interrupt mode has its own specific interrupt presenter object,
that we store under the CPU object, one for XICS and one for XIVE. The
active presenter, corresponding to the current interrupt mode, is
simply selected with a lookup on the children of the CPU.
Migration and CPU hotplug also nee
This command offers the possibility for the O/S to adjust the IPB to
allow a CPU to process event queues of other priorities during one
physical interrupt cycle. This is not currently used by the XIVE
support for sPAPR in Linux but it is by the hypervisor.
More from Ben :
It's a way to avoid th
The Event Queue Descriptor (EQD) table, also known as Event
Notification Descriptor (END), is an internal table of the XIVE
virtualization routing engine. It specifies on which Event Queue the
event data should be posted when an exception occurs (later on pulled
by the OS) and which Virtual Process
Signed-off-by: Cédric Le Goater
---
include/sysemu/dma.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
index c228c6651360..74a9558af39c 100644
--- a/include/sysemu/dma.h
+++ b/include/sysemu/dma.h
@@ -153,12 +153,12 @@ static i
If a triggered event is let through by the XIVE virtualization routing
engine, the Event Queue data defined in the associated IVE is pushed
in the in-memory event queue. The latter is a circular buffer provided
by the OS using the H_INT_SET_QUEUE_CONFIG hcall, one per server and
priority couple. Ea
Once an event has been routed by the IVRE, it reaches the XIVE
virtualization presentation engine which, simply speaking, raises one
bit in the Interrupt Pending Buffer (IBP) register corresponding to
the priority of the pending interrupt. This indicates there is an
event pending in one of the 8 pr
Each XIVE interrupt source is associated with a two bit state machine
called an Event State Buffer (ESB) : the first bit "P" means that an
interrupt is "pending" and waiting for an EOI and the bit "Q" (queued)
means a new interrupt was triggered while another was still pending.
When an event is tr
Hello,
On a POWER9 sPAPR machine, the Client Architecture Support (CAS)
negotiation process determines whether the guest operates with an
interrupt controller using the XICS legacy model, as found on POWER8,
or in XIVE exploitation mode, the newer POWER9 interrupt model. XIVE
is a complex interrup
Marc-André Lureau writes:
> check_type() will now accept a DICT { 'type': TYPENAME, 'if': ... }
> instead of a TYPENAME. This is the case in various situations where
> implicit object types are allowed such as commands/events arguments
> and return type, base and branches of union & alternate.
U
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