On Fri, 12/29 14:48, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/sd/sdhci.c | 19 ---
> 1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index ad5853d527..06a1ec6f91 100644
> --- a/hw/sd/sdhci.c
On Fri, 12/29 14:48, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Alistair Francis
> ---
> hw/sd/sdhci.c | 22 ++
> 1 file changed, 14 insertions(+), 8 deletions(-)
>
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index 38d82b4c61..ad5
On Fri, 12/29 14:48, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/sd/sdhci.c | 22 ++
> 1 file changed, 14 insertions(+), 8 deletions(-)
>
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index a11469fbca..38d82b4c61 100644
> --- a/hw/sd/sdhc
On Fri, 12/29 14:48, Philippe Mathieu-Daudé wrote:
> add sysbus/pci/sdbus separator comments to keep it clearer
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/sd/sdhci.c | 21 ++---
> 1 file changed, 10 insertions(+), 11 deletions(-)
>
> diff --git a/hw/sd/sdhci.c b/hw/sd/
On 01/02/2018 04:44 PM, Michael Clark wrote:
> +target_ulong mode = env->priv;
> +if (access_type != MMU_INST_FETCH) {
> +if (get_field(env->mstatus, MSTATUS_MPRV)) {
> +mode = get_field(env->mstatus, MSTATUS_MPP);
> +}
> +}
> +if (env->priv_ver >= PRIV_V
On Thu, Dec 28, 2017 at 06:22:55PM +0100, Igor Mammedov wrote:
>
> As were suggested at (1) and at bof session where we discussed subj,
> I'm posting variant with late numa 'configuration' i.e. when QEMU is
> started with '-S' option in paused state and numa is configured via
> monitor/QMP before
The major work for migration iterations are to move RAM/block/... data
via qemu_savevm_state_iterate(). Generalize those part into a single
function.
Signed-off-by: Peter Xu
---
migration/migration.c | 90 +++
1 file changed, 55 insertions(+), 35
This patch only moved the last part of migration_thread() into a new
function migration_iteration_finish() to make it much shorter. With
previous works to remove some local variables, now it's fairly easy to
do that.
Signed-off-by: Peter Xu
---
migration/migration.c | 80 +++
Generalize the calculation part when migration complete into a
function to simplify migration_thread().
Signed-off-by: Peter Xu
---
migration/migration.c | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/migration/migration.c b/migration/migration.c
It converts the old if clauses into switch, explicitly mentions the
possible migration states. The old nested "if"s are not clear on what
we do on different states.
Signed-off-by: Peter Xu
---
migration/migration.c | 32 +---
1 file changed, 21 insertions(+), 11 dele
We have quite a few lines in migration_thread() that calculates some
statistics for the migration interations. Isolate it into a single
function to improve readability.
Signed-off-by: Peter Xu
---
migration/migration.c | 82 +--
migration/migratio
Firstly, it was passed around. Let's just move it into MigrationState
just like many other variables as state of migration.
One thing to mention is that for postcopy, we actually don't need this
knowledge at all since postcopy can't resume a VM even if it fails (we
can see that from the old code
Introduce MigrationState.vm_down_start_time to replace the local
variable "start_time" in migration_thread to avoid passing things around.
Signed-off-by: Peter Xu
---
migration/migration.c | 12
migration/migration.h | 2 ++
2 files changed, 6 insertions(+), 8 deletions(-)
diff --
Moving existing callers all into migrate_fd_cleanup(). It simplifies
migration_thread() a bit.
Signed-off-by: Peter Xu
---
migration/migration.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/migration/migration.c b/migration/migration.c
index 0ee4b4c27c..edbda43
It was used either to:
1. store initial timestamp of migration start, and
2. store total time used by last migration
Let's provide two parameters for each of them. Mix use of the two is
slightly misleading.
Signed-off-by: Peter Xu
---
migration/migration.c | 13 +++--
migration/migrat
It's only used once, clean it up a bit.
Signed-off-by: Peter Xu
---
migration/migration.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/migration/migration.c b/migration/migration.c
index edbda43246..20f7565527 100644
--- a/migration/migration.c
+++ b/migration/migration.
When reaching here if we are still "active" it means we must be in colo
state. Assert it instead of check it in if condition.
Finally I want to use "switch" here rather than lots of complicated if
clauses.
Signed-off-by: Peter Xu
---
migration/migration.c | 3 ++-
1 file changed, 2 insertions(
Firstly this series is something as a first attempt of me to cleanup
some migration code. It may not be a good idea, but I still think it
worth a try, so I posted it. Let me know if any of you don't like it,
so I can stop. At least after the series the migration_thread()
function can be far shor
On 01/02/2018 04:44 PM, Michael Clark wrote:
> Define RISC-V ELF machine EM_RISCV 243
>
> Signed-off-by: Michael Clark
> ---
> include/elf.h | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Richard Henderson
r~
On 01/02/2018 04:44 PM, Michael Clark wrote:
> Add Michael Clark, Sagar Karandikar and Bastian Koppelmann as
> RISC-V Maintainers.
>
> Signed-off-by: Michael Clark
> ---
> MAINTAINERS | 10 ++
> 1 file changed, 10 insertions(+)
Reviewed-by: Richard Henderson
r~
On 01/02/2018 04:44 PM, Michael Clark wrote:
> +static const char *rv_ireg_name_sym[] = {
> +"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
> +"s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
> +"a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
>
On 01/02/2018 04:44 PM, Michael Clark wrote:
> +#ifdef CONFIG_USER_ONLY
> +static bool riscv_cpu_has_work(CPUState *cs)
> +{
> +return 0;
> +}
> +#else
> +static bool riscv_cpu_has_work(CPUState *cs)
> +{
> +return cs->interrupt_request & CPU_INTERRUPT_HARD;
> +}
> +#endif
There's no need
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1087411
Title:
pseries mac
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1188018
Title:
qemu monito
From: Cédric Le Goater
The 'pnv' prefix is now used for all and the routines populating the
device tree start with 'pnv_dt'. The handler of the PnvXScomInterface
is also renamed to 'dt_xscom' which should reflect that it is
populating the device tree under the 'xscom@' node of the chip.
Signed-o
From: Greg Kurz
These two are definitely warnings. Let's use the appropriate API.
Signed-off-by: Greg Kurz
Signed-off-by: David Gibson
---
hw/ppc/spapr_pci.c | 6 +++---
hw/ppc/spapr_pci_vfio.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/spapr_pci.c b/hw
From: BALATON Zoltan
This is a common generic PCI SATA controller that is also used in PCs
but more importantly guests running on the Sam460ex board prefer this
card and have a driver for it (unlike for other SATA controllers
already emulated).
Signed-off-by: BALATON Zoltan
Acked-by: John Snow
We currently have some conditionals in the spapr device tree code to decide
whether or not to advertise the availability of the VMX (aka Altivec) and
VSX vector extensions to the guest, based on whether the guest cpu has
those features.
This can lead to confusion and subtle failures on migration,
From: BALATON Zoltan
Enough to please U-Boot and make it able to detect SDRAM SPD EEPROMs
Signed-off-by: François Revol
Signed-off-by: BALATON Zoltan
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
hw/i2c/ppc4xx_i2c.c | 198 +---
inc
From: BALATON Zoltan
These are not really implemented (just return zero or default values)
but add these so guests accessing them can run.
Signed-off-by: BALATON Zoltan
Signed-off-by: David Gibson
---
hw/display/sm501.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/hw
Because PAPR is a paravirtual environment access to certain CPU (or other)
facilities can be blocked by the hypervisor. PAPR provides ways to
advertise in the device tree whether or not those features are available to
the guest.
In some places we automatically determine whether to make a feature
From: Cédric Le Goater
Also introduce utilities to manipulate bitmasks (originaly from OPAL)
which be will be used in the model of the XIVE interrupt controller.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/pnv_lpc.c| 10 -
target/ppc/cpu.h| 5
Now that the "pseries" machine type implements optional capabilities (well,
one so far) there's the possibility of having different capabilities
available at either end of a migration. Although arguably a user error,
it would be nice to catch this situation and fail as gracefully as we can.
This
This adds an spapr capability bit for Hardware Transactional Memory. It is
enabled by default for pseries-2.11 and earlier machine types. with POWER8
or later CPUs (as it must be, since earlier qemu versions would implicitly
allow it). However it is disabled by default for the latest pseries-2.12
From: BALATON Zoltan
These were forgotten when adding panel layer support in ffd39257018
"SM501 emulation for R2D-SH4".
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
[dwg: Added reference to earlier commit in message]
Signed-off-by: David Gibson
---
hw/display/sm501.c | 1
Decimal Floating Point has been available on POWER7 and later (server)
cpus. However, it can be disabled on the hypervisor, meaning that it's
not available to guests.
We currently handle this by conditionally advertising DFP support in the
device tree depending on whether the guest CPU model supp
When constructing the "host" cpu class we modify whether the VMX and VSX
vector extensions and DFP (Decimal Floating Point) are available
based on whether KVM can support those instructions. This can depend on
policy in the host kernel as well as on the actual host cpu capabilities.
However, the
From: "pbonz...@redhat.com"
We know that only one bit (in addition to SO) is going to be set in
the condition register, so do two movconds instead of three setconds,
three shifts and two ORs.
For ppc64-linux-user, the code size reduction is around 5% and the
performance improvement slightly less
Peter, the pull request this supersedes apparently failed your tests
on an arm32 host, so it's very likely this one does as well. I've
been unable to reproduce the problem on a handful of arm32 machines I
was able to borrow access to, and I'm beginning to suspect the problem
is something specific
> -Original Message-
> From: Liu, Changpeng
> Sent: Wednesday, January 3, 2018 10:07 AM
> To: 'Marc-André Lureau'
> Cc: QEMU ; Harris, James R ;
> Michael S. Tsirkin ; Stefan Hajnoczi ;
> Paolo Bonzini ; Felipe Franciosi
> Subject: RE: [Qemu-devel] [PATCH v8 4/4] contrib/vhost-user-blk:
Igor,
Thanks for the review and comments.
On 2017/12/28 22:58, Igor Mammedov wrote:
> On Thu, 28 Dec 2017 13:54:17 +0800
> Dongjiu Geng wrote:
>
>> Support this feature since version 2.10, disable it by
>> default in the old version.
> patch should go before acpi tables are actually added,
>
On 2017/12/28 22:53, Igor Mammedov wrote:
> On Thu, 28 Dec 2017 13:54:16 +0800
> Dongjiu Geng wrote:
>
>> In ARM platform we implements a notification of error events
>> via a GPIO pin. For this GPIO-signaled events, we choose GPIO
>> pin 4 for hardware error device (PNP0C33), So _E04 should be
>
On Tue, Jan 02, 2018 at 10:17:25PM +0100, Stefan Priebe - Profihost AG wrote:
>
> Am 02.01.2018 um 18:04 schrieb Wei Xu:
> > On Tue, Jan 02, 2018 at 04:24:33PM +0100, Stefan Priebe - Profihost AG
> > wrote:
> >> Hi,
> >> Am 02.01.2018 um 15:20 schrieb Wei Xu:
> >>> On Tue, Jan 02, 2018 at 12:17:2
On 01/02/18 18:02 +0200, Michael S. Tsirkin wrote:
> On Wed, Dec 27, 2017 at 02:56:20PM +0800, Haozhong Zhang wrote:
> > When a file supporting DAX is used as vNVDIMM backend, mmap it with
> > MAP_SYNC flag in addition can guarantee the persistence of guest write
> > to the backend file without oth
On Wed, 01/03 15:54, Michael Clark wrote:
> On Wed, Jan 3, 2018 at 3:41 PM, Fam Zheng wrote:
>
> > On Wed, 01/03 15:00, Michael Clark wrote:
> > > So it's essentially one error, the single line case pattern for
> > > table-driven decode which flags for long lines and asks to separate break
> > >
On Wed, Jan 3, 2018 at 3:41 PM, Fam Zheng wrote:
> On Wed, 01/03 15:00, Michael Clark wrote:
> > So it's essentially one error, the single line case pattern for
> > table-driven decode which flags for long lines and asks to separate break
> > onto its own line.
> >
> > We have actually reduced th
On Wed, 01/03 15:00, Michael Clark wrote:
> So it's essentially one error, the single line case pattern for
> table-driven decode which flags for long lines and asks to separate break
> onto its own line.
>
> We have actually reduced the readability of other parts of the code to
> conform to this
On Tue, Jan 02, 2018 at 03:19:38PM +, Dr. David Alan Gilbert wrote:
> * Vladimir Sementsov-Ogievskiy (vsement...@virtuozzo.com) wrote:
> > 28.12.2017 05:19, Peter Xu wrote:
> > > On Wed, Dec 27, 2017 at 03:25:23PM +0300, Vladimir Sementsov-Ogievskiy
> > > wrote:
> > > > Hi all!
> > > >
> > >
Matthew Wilcox wrote:
> The radix tree convention is objectively awful, which is why I'm working
> to change it. Specifying the GFP flags at radix tree initialisation time
> rather than allocation time leads to all kinds of confusion. The preload
> API is a pretty awful workaround, and it will go
It's a replacement of g_timeout_add[_seconds]() for chardevs. Chardevs
now can have dedicated gcontext, we should always bind chardev tasks
onto those gcontext rather than the default main context. Since there
are quite a few of g_timeout_add[_seconds]() callers, a new function
qemu_chr_timeout_a
Hi Igor,
sorry for my late response due to new year holiday.
On 2017/12/28 22:18, Igor Mammedov wrote:
> On Thu, 28 Dec 2017 13:54:11 +0800
> Dongjiu Geng wrote:
>
>> This implements APEI GHES Table generation and record CPER in
>> runtime via fw_cfg blobs.Now we only support two types of GHE
v2:
- add r-bs
- fix patch 3 on some s->ms conversion [Marc-André]
There were existing work that tried to allow chardev to be run in a
dedicated gcontext rather than the default main context/thread.
Basically that work passed in the correct gcontext during
g_source_attach(). However, I found some
It's a replacement of g_timeout_add[_seconds]() for chardevs. Chardevs
now can have dedicated gcontext, we should always bind chardev tasks
onto those gcontext rather than the default main context. Since there
are quite a few of g_timeout_add[_seconds]() callers, a new function
qemu_chr_timeout_a
Hi, you can close this bug.
Ken
Sent from Yahoo Mail on Android
On Tue, Jan 2, 2018 at 11:19 AM, Thomas Huth<1158...@bugs.launchpad.net>
wrote: Triaging old bug tickets... can you still reproduce this issue with the
latest version of QEMU? Or could we close this ticket nowadays?
** Change
The idle task will be attached to main gcontext even if the chardev
backend is running in another gcontext. Fix the only caller by
extending the g_idle_add() logic into the more powerful
g_source_attach(). It's basically g_idle_add_full() implementation, but
with the chardev's gcontext passed in.
In commit 6bbb6c0644 ("chardev: use per-dev context for
io_add_watch_poll", 2017-09-22) all the chardev watches are converted to
use per-chardev gcontext to support chardev to be run outside default
main thread. However that's still missing one call from the frontend
code. Touch that up.
Reviewe
On Mon, 12/18 22:01, Fam Zheng wrote:
> Because usb-storage creates an internal scsi device, we should propagate
> options. We already do so for bootindex etc, but failed to take care of
> share-rw. Fix it in an apparent way: add a new parameter to
> scsi_bus_legacy_add_drive and pass in s->conf.sh
On Tue, 01/02 21:58, Roy Shterman wrote:
> Hi all,
>
> I'm trying to get VM started with libiscsi (iSCSI initiator) device. Every
> thing seems good from iSCSI point of view, but I'm stuck in VM boot,
> "Booting from Hard Disk".
> Any idea what can get wrong? how I can assure that the boot itself
> -Original Message-
> From: Marc-André Lureau [mailto:marcandre.lur...@gmail.com]
> Sent: Tuesday, January 2, 2018 11:44 PM
> To: Liu, Changpeng
> Cc: QEMU ; Harris, James R ;
> Michael S. Tsirkin ; Stefan Hajnoczi ;
> Paolo Bonzini ; Felipe Franciosi
> Subject: Re: [Qemu-devel] [PATCH
On Tue, Jan 02, 2018 at 05:10:01PM +0100, Marc-André Lureau wrote:
> Hi
>
> On Thu, Dec 28, 2017 at 8:29 AM, Peter Xu wrote:
> > It's a replacement of g_timeout_add[_seconds]() for chardevs. Chardevs
> > now can have dedicated gcontext, we should always bind chardev tasks
> > onto those gcontext
On 12/31/17 17:55 +0200, Michael S. Tsirkin wrote:
> On Mon, Dec 25, 2017 at 09:06:10AM +0800, Haozhong Zhang wrote:
> > The new function pmem_persistent() flushes the previous cached writes
> > on the specified memory buffer, which ensures the write persistence if
> > the buffer is in persistent m
So it's essentially one error, the single line case pattern for
table-driven decode which flags for long lines and asks to separate break
onto its own line.
We have actually reduced the readability of other parts of the code to
conform to this specific rule. In fact I spent a day and a half with
c
Hi Igor,
> -Original Message-
> From: Igor Mammedov [mailto:imamm...@redhat.com]
> Sent: Tuesday, January 02, 2018 11:46 PM
> To: Zhoujian (jay)
> Cc: qemu-devel@nongnu.org; Huangweidong (C) ;
> m...@redhat.com; wangxin (U) ; Gonglei (Arei)
> ; Liuzhe (Ahriy, Euler)
> Subject: Re: [Qemu-
Hi famz,
If you read the patch logs, you'll see we mention that two of the patches
don't pass checkpatch. The checkpatch warnings are in the patch comments.
[0004/0021] RISC-V Disassembler violates some select standards for brevity.
It is repetitive machine generated code. LOC will blow up.
[0021
> -Original Message-
> From: Marc-André Lureau [mailto:marcandre.lur...@gmail.com]
> Sent: Tuesday, January 2, 2018 11:30 PM
> To: Liu, Changpeng
> Cc: QEMU ; Harris, James R ;
> Michael S. Tsirkin ; Stefan Hajnoczi ;
> Paolo Bonzini ; Felipe Franciosi
> Subject: Re: [Qemu-devel] [PATCH
> -Original Message-
> From: Marc-André Lureau [mailto:marcandre.lur...@gmail.com]
> Sent: Tuesday, January 2, 2018 11:20 PM
> To: Liu, Changpeng
> Cc: QEMU ; Harris, James R ;
> Michael S. Tsirkin ; Stefan Hajnoczi ;
> Paolo Bonzini ; Felipe Franciosi
> Subject: Re: [Qemu-devel] [PATCH
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1514940265-18093-1-git-send-email-...@sifive.com
Subject: [Qemu-devel] [PATCH v1 00/21] RISC-V QEMU Port Submission v1
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
to
On 01/02/2018 09:15 PM, Alistair Francis wrote:
> We are making progress here. Do you think it would be worth splitting
> out the earlier patches that have been reviewed so far so they can be
> merged? A 42 patch series it pretty daunting and most of the first 20
> are pretty straightforward and ha
On Mon, Dec 18, 2017 at 06:35:12PM +0100, Thomas Huth wrote:
> It's a deprecated dummy device since QEMU v2.6.0. That should have
> been enough time to allow the users to update their scripts in case
> they still use it, so let's remove this legacy code now.
>
> Signed-off-by: Thomas Huth
I'm af
The CLINT (Core Local Interruptor) device provides real-time clock, timer
and interprocessor interrupts based on SiFive's CLINT specification.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_clint.c | 312
include/hw/riscv/sifive_clint.h | 56 ++
This adds RISC-V into the build system enabling the following targets:
- riscv32-softmmu
- riscv64-softmmu
- riscv32-linux-user
- riscv64-linux-user
This adds defaults configs for RISC-V, enables the build for the RISC-V
CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'
scri
This provides a RISC-V Board compatible with the the SiFive U500 SDK.
The following machine is implemented:
- 'sifive_u500'; CLINT, PLIC, UART, device-tree
Signed-off-by: Michael Clark
---
hw/riscv/sifive_u500.c | 338 +
include/hw/riscv/sifive_u5
This provides a RISC-V Board compatible with the the SiFive E300 SDK.
The following machine is implemented:
- 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM
Signed-off-by: Michael Clark
---
hw/riscv/sifive_e300.c | 232 +
include/hw/riscv/
TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
RISC-V code generator has complete coverage for the Base ISA v2.2,
Privileged ISA v1.9.1 and Privileged ISA v1.10:
- RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
- RISC-V Instruction Set Manual Volume II: Privile
QEMU model of the UART on the SiFive E300 and U500 series SOCs.
BBL supports the SiFive UART for early console access via the SBI
(Supervisor Binary Interface) and the linux kernel SBI console.
The SiFive UART implements the pre qom legacy interface consistent
with the 16550a UART in 'hw/char/seri
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO.
The following machine is implemented:
- 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree
Signed-off-by: Michael Clark
---
hw/riscv/virt.c | 364
include/hw/riscv/virt
Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate
register reads made by the SDK BSP.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_prci.c | 107 +
include/hw/riscv/sifive_prci.h | 43 +
2 files changed, 150
RISC-V machines compatble with Spike aka riscv-isa-sim, the RISC-V
Instruction Set Simulator. The following machines are implemented:
- 'spike_v1.9'; HTIF console, config-string, Privileged ISA Version 1.9.1
- 'spike_v1.10'; HTIF console, device-tree, Privileged ISA Version 1.10
Signed-off-by: Mi
Implements the physical memory protection extension as specified in
Privileged ISA Version 1.10.
Signed-off-by: Michael Clark
---
target/riscv/pmp.c | 381 +
target/riscv/pmp.h | 70 ++
2 files changed, 451 insertions(+)
create mode 1
Holds the state of a heterogenous array of RISC-V hardware threads.
Signed-off-by: Michael Clark
---
hw/riscv/riscv_hart.c | 95 +++
include/hw/riscv/riscv_hart.h | 45
2 files changed, 140 insertions(+)
create mode 100644 hw/
HTIF (Host Target Interface) provides console emulation for QEMU. HTIF
allows identical copies of BBL (Berkeley Boot Loader) and linux to run
on both Spike and QEMU. BBL provides HTIF console access via the
SBI (Supervisor Binary Interface) and the linux kernel SBI console.
The HTIF interface read
The PLIC (Platform Level Interrupt Controller) device provides a
parameterizable interrupt controller based on SiFive's PLIC specification.
Signed-off-by: Michael Clark
---
hw/riscv/sifive_plic.c | 558 +
include/hw/riscv/sifive_plic.h | 91 ++
The RISC-V disassembler has no dependencies outside of the 'disas'
directory so it can be applied independently. The majority of the
disassembler is machine-generated from instruction set metadata:
- https://github.com/michaeljclark/riscv-meta
Expected checkpatch errors for consistency and brevit
Helper routines for FPU instructions and NaN definitions.
Signed-off-by: Michael Clark
---
fpu/softfloat-specialize.h | 7 +-
target/riscv/fpu_helper.c | 591 +
2 files changed, 595 insertions(+), 3 deletions(-)
create mode 100644 target/riscv/fpu_
GDB Register read and write routines.
Signed-off-by: Michael Clark
---
target/riscv/gdbstub.c | 59 ++
1 file changed, 59 insertions(+)
create mode 100644 target/riscv/gdbstub.c
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
new fil
Implementation of linux user emulation for RISC-V.
Signed-off-by: Michael Clark
---
linux-user/elfload.c | 22 +++
linux-user/main.c | 130 -
linux-user/riscv/syscall_nr.h | 275 +++
linux-user/riscv/target_cpu.h
Privileged control and status register helpers and page fault handling.
Signed-off-by: Michael Clark
---
target/riscv/helper.c| 494 +
target/riscv/helper.h| 78 ++
target/riscv/op_helper.c | 707 +++
3 file
Add Michael Clark, Sagar Karandikar and Bastian Koppelmann as
RISC-V Maintainers.
Signed-off-by: Michael Clark
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 73a..09a1314 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -209,6 +20
Add CPU state header, CPU definitions and initialization routines
Signed-off-by: Michael Clark
---
target/riscv/cpu.c | 338 +++
target/riscv/cpu.h | 363 ++
target/riscv/cpu_bits.h | 411 ++
QEMU RISC-V Emulation Support (RV64GC, RV32GC)
*** Background ***
"RISC-V is an open, free ISA enabling a new era of processor innovation
through open standard collaboration. Born in academia and research,
RISC-V ISA delivers a new level of free, extensible software and
hardware freedom on archit
Define RISC-V ELF machine EM_RISCV 243
Signed-off-by: Michael Clark
---
include/elf.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index e8a515c..8e457fc 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -112,6 +112,8 @@ typedef int64_t Elf64_Sxword;
#d
On Thu, Dec 21, 2017 at 04:40:19PM +0800, Liu, Yi L wrote:
> On Wed, Dec 20, 2017 at 10:18:16PM +1100, David Gibson wrote:
> > On Wed, Dec 20, 2017 at 02:47:30PM +0800, Liu, Yi L wrote:
> > > On Mon, Dec 18, 2017 at 10:35:31PM +1100, David Gibson wrote:
> > > > On Wed, Nov 15, 2017 at 03:16:32PM +0
On Tue, Jan 02, 2018 at 05:13:09PM +1100, Alexey Kardashevskiy wrote:
> On 11/12/17 17:20, Alexey Kardashevskiy wrote:
> > On 09/11/17 17:38, David Gibson wrote:
> >> On Tue, Nov 07, 2017 at 06:14:04PM +1100, Alexey Kardashevskiy wrote:
> >>> On 20/10/17 11:46, Alexey Kardashevskiy wrote:
> On
On Fri, Dec 29, 2017 at 9:48 AM, Philippe Mathieu-Daudé wrote:
> Since v2:
> - more detailed 'capabilities', all boards converted to use these properties
> - since all qtests pass, removed the previous 'capareg' property
> - added Stefan/Alistair R-b
> - corrected 'access' LED behavior (Alistair's
On Fri, Dec 29, 2017 at 9:49 AM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/sd/sdhci-internal.h | 2 +-
> hw/sd/sdhci.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/sd/sdhc
On Fri, Dec 29, 2017 at 9:49 AM, Philippe Mathieu-Daudé wrote:
> running qtests:
>
> $ make check-qtest-arm
> GTESTER check-qtest-arm
> SDHC rd_4b @0x44 not implemented
> SDHC wr_4b @0x40 <- 0x89abcdef not implemented
> SDHC wr_4b @0x44 <- 0x01234567 not implemented
>
> Signed-off-by:
On Fri, Dec 29, 2017 at 9:49 AM, Philippe Mathieu-Daudé wrote:
> It blinks to caution the user not to remove the card while the SD card is
> being accessed.
> So far it only emit a trace event.
s/emit/emits/g
>
> Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Alistair Francis
Alistair
> --
On Fri, Dec 29, 2017 at 9:48 AM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> include/hw/sd/sdhci.h | 2 --
> hw/sd/sdhci.c | 2 --
> 2 files changed, 4 deletions(-)
>
> diff --git a/include/hw/sd/sdhci.h b/inclu
On Fri, Dec 29, 2017 at 9:48 AM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Alistair Francis
Alistair
> ---
> include/hw/sd/sdhci.h | 21 +++--
> 1 file changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/include/hw/sd/sdhci.h b/inc
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
---
target/m68k/translate.c | 53 ++---
1 file changed, 46 insertions(+), 7 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index d007943d93..205c3b8f35 100644
--
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