Re: [Qemu-devel] [PATCH 3/3] linux-user: MIPS set cpu to r6 CPU if binary is R6

Le 17/01/2018 à 03:26, YunQiang Su a écrit : > On Sat, Jan 13, 2018 at 10:48 PM, Laurent Vivier wrote: >> From: YunQiang Su >> >> So here we need to detect the version of binaries and set >> cpu_model for it. >> >> [lv: original patch modified to move code

Re: [Qemu-devel] [RFC v1] block/NVMe: introduce a new vhost NVMe host device to QEMU

On 17/01/2018 01:53, Liu, Changpeng wrote: >> Second, virtio-based vhost-user remains QEMU's preferred method for >> high-performance I/O in guests. Discard support is missing and that is >> important for SSDs; that should be fixed in the virtio spec. Are there > Previously I have a patch adding

Re: [Qemu-devel] [PATCH v2 0/4] coroutine-lock: polymorphic CoQueue

Hi, This series failed docker-build@min-glib build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. Type: series Message-id: 20180116142316.30486-1-pbonz...@redhat.com Subject: [Qemu-devel] [PATCH v2 0/4]

[Qemu-devel] [PATCH v1 4/4] virtio-balloon: Don't skip free pages if the poison val is non-zero

If the guest is using a non-zero poisoning, we don't skip the transfer of guest free pages. Todo: As a next step optimization, we can try 1) skip the transfer of guest poisoned free pages; 2) send the poison value to destination; and 3) seek a way to poison the guest free pages before the guest

[Qemu-devel] [PATCH v1 0/4] virtio-balloon: support free page reporting

This is the deivce part implementation to add a new feature, VIRTIO_BALLOON_F_FREE_PAGE_VQ to the virtio-balloon device. The device receives the guest free page hint from the driver and clears the corresponding bits in the dirty bitmap, so that those free pages are not transferred to the

[Qemu-devel] [PATCH v1 1/4] virtio-balloon: VIRTIO_BALLOON_F_FREE_PAGE_VQ

The new feature enables the virtio-balloon device to receive the hint of guest free pages from the free page vq, and clears the corresponding bits of the free page from the dirty bitmap, so that those free pages are not transferred by the migration thread. Without this feature, to local live

[Qemu-devel] [PATCH v1 3/4] virtio-balloon: add a timer to limit the free page report wating time

This patch adds a timer to limit the time that the host waits for the free pages reported by the guest. Users can specify the time in ms via "free-page-wait-time" command line option. If a user doesn't specify a time, the host waits till the guest finishes reporting all the free pages. The policy

[Qemu-devel] [PATCH v1 2/4] migration: call balloon to clear bits of free pages from dirty bitmap

When migration starts, call the related balloon functions to clear the bits of guest free pages from the dirty bitmap. The dirty bitmap should be ready to use when sending pages to the destination, so stop the guest from reporting free pages before sending pages. Signed-off-by: Wei Wang

Re: [Qemu-devel] [PATCH 00/11] qdev: remove DeviceClass::init/exit()

Hi, This series failed docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. Type: series Message-id: 20180116131555.14242-1-f4...@amsat.org Subject: [Qemu-devel] [PATCH 00/11] qdev: remove

Re: [Qemu-devel] [PATCH v2 0/4] coroutine-lock: polymorphic CoQueue

On 01/17/2018 02:04 PM, no-re...@patchew.org wrote: BUILD min-glib Traceback (most recent call last): File "./tests/docker/docker.py", line 407, in sys.exit(main()) File "./tests/docker/docker.py", line 404, in main return args.cmdobj.run(args, argv) File

Re: [Qemu-devel] [PATCH v5 0/2] qemu-img: Document --force-share / -U

Ping? On Tue, Dec 26, 2017 at 10:52 AM, Fam Zheng wrote: > v5: Clean up the @table @var section first. [Kevin, Peter] > > Fam Zheng (2): > qemu-img.texi: Clean up parameter list > qemu-img: Document --force-share / -U > > qemu-img.texi | 75 >

Re: [Qemu-devel] [qemu-s390x] [PATCH v3 4/8] s390-ccw: interactive boot menu for eckd dasd (menu setup)

On 16.01.2018 20:37, Collin L. Walling wrote: > On 01/16/2018 01:23 PM, Thomas Huth wrote: >> On 15.01.2018 17:44, Collin L. Walling wrote: >>> Reads boot menu flag and timeout values from the iplb and >>> sets the respective fields for the menu. >>> >>> Signed-off-by: Collin L. Walling

Re: [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations

gcc-4.8.5-16.el7_4.1.ppc64le On Tue, Jan 16, 2018 at 11:50 PM, Richard Henderson wrote: > On 01/16/2018 03:59 AM, Peter Maydell wrote: >> /var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: >> internal compiler error: in emit_move_insn, at

Re: [Qemu-devel] [PATCH v3 1/4] cryptodev: add vhost-user as a new cryptodev backend

> -Original Message- > From: Qemu-devel [mailto:qemu-devel- > bounces+jianjay.zhou=huawei@nongnu.org] On Behalf Of Michael S. Tsirkin > Sent: Wednesday, January 17, 2018 12:41 AM > To: Zhoujian (jay) > Cc: pa...@linux.vnet.ibm.com; Huangweidong (C)

Re: [Qemu-devel] [RFC 3/3] vhost-user: add VFIO based accelerators support

On Tue, Jan 16, 2018 at 10:23:39AM -0700, Alex Williamson wrote: > On Fri, 22 Dec 2017 14:41:51 +0800 > Tiwei Bie wrote: > > > Signed-off-by: Tiwei Bie > > --- > > docs/interop/vhost-user.txt| 57 ++ > > hw/vfio/common.c | 2 +-

Re: [Qemu-devel] [PATCH v2 6/8] docker: add the Fedora 27 base image

On Tue, Jan 16, 2018 at 12:38 AM, Philippe Mathieu-Daudé wrote: > On 01/15/2018 01:27 PM, Daniel P. Berrange wrote: >> On Mon, Jan 15, 2018 at 11:34:57AM -0300, Philippe Mathieu-Daudé wrote: >>> straight copy on Fedora 25 base. >>> >>> Suggested-by: Paolo Bonzini

Re: [Qemu-devel] [PATCH v1] migration: use s->threshold_size inside migration_update_counters

On Wed, Jan 17, 2018 at 09:06:43AM +0800, Wei Wang wrote: > On 01/16/2018 08:19 PM, Peter Xu wrote: > > On Tue, Jan 16, 2018 at 06:51:32PM +0800, Wei Wang wrote: > > > The threshold size is changed to be recorded in s->threshold_size by > > > commit b15df1ae5063c7c181f8f068f9eba7661b3b5e1. > > >

Re: [Qemu-devel] [PATCH v2 0/4] Clean up the ppc configs

On Tue, Jan 16, 2018 at 01:15:54PM +0100, Thomas Huth wrote: > ppc64-softmmu is a superset of ppc-softmmu which in turn is a superset > of ppcemb-softmmu. But since the config files are currently independent > from each other, we missed to define some CONFIG switches in the super- > sets:

Re: [Qemu-devel] [PATCH 0/3] target/ppc: add support for hypervisor doorbells

On Tue, Jan 16, 2018 at 08:41:54AM +0100, Cédric Le Goater wrote: > Hi, > > The hypervisor doorbells are used by skiboot and Linux on POWER9 > processors to wake up secondaries. This adds processor control support > to the Book3S architecture. > > The full tree can be found here : > >

Re: [Qemu-devel] [PATCH] Add ability to provide ifname when using netdev bridge or tap helper

On 2018年01月17日 07:18, Shaun Reitan wrote: This patch replaces the patch I sent yesturday. This one fixes a bug in my original code as well as corrects a few styling issues. Hopfully this one comes out correct! Sorry for the inconvienece. When currently using -netdev bridge or -netdev tap

Re: [Qemu-devel] [PULL 00/25] pc, pci, virtio: features, fixes, cleanups

On 2018年01月16日 16:03, Dmitry Fleytman wrote: On 16 Jan 2018, at 8:28, Jason Wang wrote: On 2018年01月16日 10:48, Michael S. Tsirkin wrote: On Tue, Jan 09, 2018 at 12:10:10PM +1100, David Gibson wrote: On Mon, Jan 08, 2018 at 08:10:23PM +0200, Michael S. Tsirkin wrote:

Re: [Qemu-devel] [PATCH v4 13/13] docker: change Fedora images to run with python3

On 01/16/2018 01:02 AM, Daniel P. Berrange wrote: Fedora has switched to Python 3 by default, so it makes sense to use that for testing QEMU builds, so we get testing of Python 3 compatibility. Signed-off-by: Daniel P. Berrange ---

Re: [Qemu-devel] [PATCH 0/7] docker: update Ubuntu and Fedora images, deprecate old ones

On 01/12/2018 08:49 PM, Philippe Mathieu-Daudé wrote: Hi, This series is to be clearer about which upstream version we are using. All "FROM distrib:latest" entries have now been removed and replaced by explicit "FROM distrib:version" ones. To keep backward compatibility, a warning is

[Qemu-devel] [PULL 19/22] ppc/pnv: fix XSCOM core addressing on POWER9

From: Cédric Le Goater The XSCOM base address of the core chiplet was wrongly calculated. Use the OPAL macros to fix that and do a couple of renames. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv.c

Re: [Qemu-devel] [PATCH 3/3] linux-user: MIPS set cpu to r6 CPU if binary is R6

On Sat, Jan 13, 2018 at 10:48 PM, Laurent Vivier wrote: > From: YunQiang Su > > So here we need to detect the version of binaries and set > cpu_model for it. > > [lv: original patch modified to move code into get_cpu_model()] > Signed-off-by: Laurent Vivier

[Qemu-devel] [PULL 18/22] ppc/pnv: introduce pnv*_is_power9() helpers

From: Cédric Le Goater These are useful when instantiating device models which are shared between the POWER8 and the POWER9 processor families. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv_xscom.c | 8

[Qemu-devel] [PULL 08/22] hw/ppc/spapr_caps: Rework spapr_caps to use uint8 internal representation

From: Suraj Jitindar Singh Currently spapr_caps are tied to boolean values (on or off). This patch reworks the caps so that they can have any uint8 value. This allows more capabilities with various values to be represented in the same way internally. Capabilities are

[Qemu-devel] [PULL 21/22] target/ppc: add support for POWER9 HILE

From: Cédric Le Goater Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- target/ppc/cpu.h | 1 + target/ppc/excp_helper.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.h

[Qemu-devel] [PULL 16/22] ppc/pnv: use POWER9 DD2 processor

From: Cédric Le Goater commit 1ed9c8af501f ("target/ppc: Add POWER9 DD2.0 model information") deprecated the POWER9 model v1.0. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv.c | 2 +-

[Qemu-devel] [PULL 03/22] spapr: Treat Hardware Transactional Memory (HTM) as an optional capability

This adds an spapr capability bit for Hardware Transactional Memory. It is enabled by default for pseries-2.11 and earlier machine types. with POWER8 or later CPUs (as it must be, since earlier qemu versions would implicitly allow it). However it is disabled by default for the latest

[Qemu-devel] [PULL 22/22] target-ppc: Fix booke206 tlbwe TLB instruction

From: Luc MICHEL When overwritting a valid TLB entry with a new one, the previous page were not flushed in QEMU TLB, leading to incoherent mapping. This commit fixes this. Signed-off-by: Luc MICHEL Signed-off-by: David Gibson

[Qemu-devel] [PULL 13/22] spapr: Adjust default VSMT value for better migration compatibility

fa98fbfc "PC: KVM: Support machine option to set VSMT mode" introduced the "vsmt" parameter for the pseries machine type, which controls the spacing of the vcpu ids of thread 0 for each virtual core. This was done to bring some consistency and stability to how that was done, while still allowing

[Qemu-devel] [PULL 12/22] spapr: Allow some cases where we can't set VSMT mode in the kernel

At present if we require a vsmt mode that's not equal to the kernel's default, and the kernel doesn't let us change it (e.g. because it's an old kernel without support) then we always fail. But in fact we can cope with the kernel having a different vsmt as long as a) it's >= the actual number

[Qemu-devel] [PULL 05/22] target/ppc: Clean up probing of VMX, VSX and DFP availability on KVM

When constructing the "host" cpu class we modify whether the VMX and VSX vector extensions and DFP (Decimal Floating Point) are available based on whether KVM can support those instructions. This can depend on policy in the host kernel as well as on the actual host cpu capabilities. However, the

[Qemu-devel] [PULL 20/22] ppc/pnv: change initrd address

From: Cédric Le Goater When skiboot starts, it first clears the CPU structs for all possible CPUs on a system : for (i = 0; i <= cpu_max_pir; i++) memset(_stacks[i].cpu, 0, sizeof(struct cpu_thread)); On POWER9, cpu_max_pir is quite big, 0x7fff, and the

[Qemu-devel] [PULL 17/22] ppc/pnv: change core mask for POWER9

From: Cédric Le Goater When addressed by XSCOM, the first core has the 0x20 chiplet ID but the CPU PIR can start at 0x0. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv.c | 4 ++--

[Qemu-devel] [PULL 11/22] target/ppc: Clarify compat mode max_threads value

We recently had some discussions that were sidetracked for a while, because nearly everyone misapprehended the purpose of the 'max_threads' field in the compatiblity modes table. It's all about guest expectations, not host expectations or support (that's handled elsewhere). In an attempt to

[Qemu-devel] [PULL 04/22] spapr: Validate capabilities on migration

Now that the "pseries" machine type implements optional capabilities (well, one so far) there's the possibility of having different capabilities available at either end of a migration. Although arguably a user error, it would be nice to catch this situation and fail as gracefully as we can. This

[Qemu-devel] [PULL 02/22] spapr: Capabilities infrastructure

Because PAPR is a paravirtual environment access to certain CPU (or other) facilities can be blocked by the hypervisor. PAPR provides ways to advertise in the device tree whether or not those features are available to the guest. In some places we automatically determine whether to make a feature

[Qemu-devel] [PULL 10/22] ppc: Change Power9 compat table to support at most 8 threads/core

From: Jose Ricardo Ziviani Increases the max smt mode to 8 for Power9. That's because KVM supports smt emulation in this platform so QEMU should allow users to use it as well. Today if we try to pass -smp ...,threads=8, QEMU will silently truncate it to smt4 mode and

[Qemu-devel] [PULL 15/22] tests/boot-serial-test: fix powernv support

From: Cédric Le Goater Recent commit introduced the firmware image skiboot 5.9 which has a different first line ouput. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- tests/boot-serial-test.c | 2 +- 1 file changed, 1

[Qemu-devel] [PULL 00/22] ppc-for-2.12 queue 20180117

The following changes since commit 8e5dc9ba49743b46d955ec7dacb04e42ae7ada7c: Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180116' into staging (2018-01-16 17:36:39 +) are available in the Git repository at: git://github.com/dgibson/qemu.git tags/ppc-for-2.12-20180117

[Qemu-devel] [PULL 01/22] target/ppc: Yet another fix for KVM-HV HPTE accessors

From: Alexey Kardashevskiy As stated in the 1ad9f0a464fe commit log, the returned entries are not a whole PTEG. It was not a problem before 1ad9f0a464fe as it would read a single record assuming it contains a whole PTEG but now the code tries reading the entire PTEG and "if ((n -

[Qemu-devel] [PULL 07/22] spapr: Handle Decimal Floating Point (DFP) as an optional capability

Decimal Floating Point has been available on POWER7 and later (server) cpus. However, it can be disabled on the hypervisor, meaning that it's not available to guests. We currently handle this by conditionally advertising DFP support in the device tree depending on whether the guest CPU model

[Qemu-devel] [PULL 09/22] spapr: Remove unnecessary 'options' field from sPAPRCapabilityInfo

The options field here is intended to list the available values for the capability. It's not used yet, because the existing capabilities are boolean. We're going to add capabilities that aren't, but in that case the info on the possible values can be folded into the .description field.

[Qemu-devel] [PULL 06/22] spapr: Handle VMX/VSX presence as an spapr capability flag

We currently have some conditionals in the spapr device tree code to decide whether or not to advertise the availability of the VMX (aka Altivec) and VSX vector extensions to the guest, based on whether the guest cpu has those features. This can lead to confusion and subtle failures on migration,

Re: [Qemu-devel] [PATCH 4/7] docker: do not use Trusty APT source in Xenial

On 01/12/2018 08:49 PM, Philippe Mathieu-Daudé wrote: probably missed in 7fc581c29518 Signed-off-by: Philippe Mathieu-Daudé --- tests/docker/dockerfiles/ubuntu.docker | 2 -- 1 file changed, 2 deletions(-) diff --git a/tests/docker/dockerfiles/ubuntu.docker

Re: [Qemu-devel] [PATCH 3/7] docker: add the Ubuntu Trusty base image

On 01/12/2018 08:49 PM, Philippe Mathieu-Daudé wrote: based on QEMU v2.10 ubuntu.docker (ca853f0c76e3 and 2346b12fc52d) Signed-off-by: Philippe Mathieu-Daudé --- tests/docker/dockerfiles/ubuntu14.04.docker | 17 + 1 file changed, 17 insertions(+) create

Re: [Qemu-devel] [PATCH 2/7] docker: do not display deprecated images in 'make docker' help

On 01/12/2018 08:49 PM, Philippe Mathieu-Daudé wrote: the 'debian' base image is deprecated since 3e11974988d8 Signed-off-by: Philippe Mathieu-Daudé --- tests/docker/Makefile.include | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git

Re: [Qemu-devel] Qemu c++ build question

Hi and thanks for the answer, Yes, not quite what I expected but your suggestion might indeed be the solution I need. Even if the problem that I'm encountering doesn't seeem to be related to the one you had, I'd will just export a C interface from the C++ code and keep the two isolated,

Re: [Qemu-devel] Qemu c++ build question

> On 17 Jan 2018, at 03:14, Ancuta, Cristian wrote: > > I'm currently working on implementing an emulation target in QEMU and the > implementation is in C++. it might not be the answer you expect, but last time I tried to do a similar thing I encountered a problem

Re: [Qemu-devel] [PATCH] memory: update comments and fix some typos

> -Original Message- > From: Paolo Bonzini [mailto:pbonz...@redhat.com] > Sent: Tuesday, January 16, 2018 10:44 PM > To: Zhoujian (jay) ; qemu-devel@nongnu.org > Cc: Huangweidong (C) ; wangxin (U) > > Subject:

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 0/6] target/ppc: Rework spapr_caps

On Wed, Jan 17, 2018 at 10:46:45AM +1100, Alexey Kardashevskiy wrote: > On 17/01/18 10:30, David Gibson wrote: > > On Wed, Jan 17, 2018 at 10:26:28AM +1100, Alexey Kardashevskiy wrote: > >> On 17/01/18 09:34, David Gibson wrote: > >>> On Tue, Jan 16, 2018 at 03:46:20PM +0100, Andrea Bolognani

[Qemu-devel] Qemu c++ build question

I'm not sure this is the right way to ask this question - and I appollogize if it isn't - but here goes: I'm currently working on implementing an emulation target in QEMU and the implementation is in C++. I have the file qemu/target/mytarget/translate.cpp from which I #include and osdep.h

Re: [Qemu-devel] [PATCH v1] migration: use s->threshold_size inside migration_update_counters

On 01/16/2018 08:19 PM, Peter Xu wrote: On Tue, Jan 16, 2018 at 06:51:32PM +0800, Wei Wang wrote: The threshold size is changed to be recorded in s->threshold_size by commit b15df1ae5063c7c181f8f068f9eba7661b3b5e1. Signed-off-by: Wei Wang Could you help confirm the

Re: [Qemu-devel] [RFC v1] block/NVMe: introduce a new vhost NVMe host device to QEMU

> -Original Message- > From: Paolo Bonzini [mailto:pbonz...@redhat.com] > Sent: Wednesday, January 17, 2018 1:07 AM > To: Liu, Changpeng ; qemu-devel@nongnu.org > Cc: Harris, James R ; Busch, Keith > ;

[Qemu-devel] [PATCH v2] usb-storage: Fix share-rw option parsing

Because usb-storage creates an internal scsi device, we should propagate options. We already do so for bootindex etc, but failed to take care of share-rw. Fix it in an apparent way: add a new parameter to scsi_bus_legacy_add_drive and pass in s->conf.share_rw. Cc: qemu-sta...@nongnu.org

Re: [Qemu-devel] [PATCH v2 2/3] xlnx-zynqmp-rtc: Add basic time support

On Mon, Jan 15, 2018 at 5:35 AM, Peter Maydell wrote: > On 12 January 2018 at 22:37, Alistair Francis > wrote: >> Allow the guest to determine the time set from the QEMU command line. >> >> This includes adding a trace event to debug the new

Re: [Qemu-devel] [PATCH] LEON3 IRQMP: Fix IRQ software ack

On Mon, Jan 15, 2018 at 9:27 AM, Jean-Christophe Dubois wrote: > Le 2018-01-15 14:45, Jean-Christophe Dubois a écrit : >> >> Le 2018-01-15 12:09, Fabien Chouteau a écrit : >>> >>> On 12/01/2018 15:10, Jean-Christophe Dubois wrote: Le 2018-01-12 11:55, Fabien

Re: [Qemu-devel] [PATCH v2 1/3] xlnx-zynqmp-rtc: Initial commit

On Mon, Jan 15, 2018 at 5:25 AM, Peter Maydell wrote: > On 12 January 2018 at 22:36, Alistair Francis > wrote: >> Initial commit of the ZynqMP RTC device. >> >> Signed-off-by: Alistair Francis >> --- >> V2: >>

[Qemu-devel] [PATCH] Add ability to provide ifname when using netdev bridge or tap helper

This patch replaces the patch I sent yesturday. This one fixes a bug in my original code as well as corrects a few styling issues. Hopfully this one comes out correct! Sorry for the inconvienece. When currently using -netdev bridge or -netdev tap with a helper you are unable to set an ifname.

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 0/6] target/ppc: Rework spapr_caps

On 17/01/18 10:30, David Gibson wrote: > On Wed, Jan 17, 2018 at 10:26:28AM +1100, Alexey Kardashevskiy wrote: >> On 17/01/18 09:34, David Gibson wrote: >>> On Tue, Jan 16, 2018 at 03:46:20PM +0100, Andrea Bolognani wrote: On Wed, 2018-01-17 at 00:54 +1100, David Gibson wrote: >> Correct

[Qemu-devel] [PATCH v5 8/9] xlnx-zynqmp-pmu: Connect the IPI device to the PMU

Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- V4: - Move the IPI to the machine instead of the SoC hw/microblaze/xlnx-zynqmp-pmu.c | 31 +++ 1 file changed, 31 insertions(+) diff --git

[Qemu-devel] [PATCH v5 5/9] xlnx-pmu-iomod-intc: Add the PMU Interrupt controller

Add the PMU IO Module Interrupt controller device. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- default-configs/microblaze-softmmu.mak | 1 + hw/intc/Makefile.objs | 1 +

Re: [Qemu-devel] [PATCH v5 0/9] Add the ZynqMP PMU and IPI

On Tue, Jan 16, 2018 at 3:22 PM, Alistair Francis wrote: > > This series adds the ZynqMP Power Management Unit (PMU) machine with basic > functionality. > > The machine only has the > - CPU > - Memory > - Interrupt controller > - IPI device > > connected, but that

[Qemu-devel] [PATCH v5 7/9] xlnx-zynqmp-ipi: Initial version of the Xilinx IPI device

This is the initial version of the Inter Processor Interrupt device. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- hw/intc/Makefile.objs | 1 + hw/intc/xlnx-zynqmp-ipi.c | 377

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 0/6] target/ppc: Rework spapr_caps

On Wed, Jan 17, 2018 at 10:26:28AM +1100, Alexey Kardashevskiy wrote: > On 17/01/18 09:34, David Gibson wrote: > > On Tue, Jan 16, 2018 at 03:46:20PM +0100, Andrea Bolognani wrote: > >> On Wed, 2018-01-17 at 00:54 +1100, David Gibson wrote: > Correct me if I'm wrong, but it seems to me like

[Qemu-devel] [PATCH v5 6/9] xlnx-zynqmp-pmu: Connect the PMU interrupt controller

Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- hw/microblaze/xlnx-zynqmp-pmu.c | 24 1 file changed, 24 insertions(+) diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c

[Qemu-devel] [PATCH v5 3/9] xlnx-zynqmp-pmu: Add the CPU and memory

Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- V4: - Remove the ZCU102 name V2: - Fix the pmu-cpu name - Use err and errp for CPU realise instead of

[Qemu-devel] [PATCH v5 4/9] aarch64-softmmu.mak: Use an ARM specific config

In preperation for having an ARM and MicroBlaze ZynqMP machine let's split out the current ARM specific config options. Signed-off-by: Alistair Francis Acked-by: Peter Maydell Reviewed-by: Edgar E. Iglesias ---

[Qemu-devel] [PATCH v5 2/9] xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU

The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due

[Qemu-devel] [PATCH v5 1/9] microblaze: boot.c: Don't try to find NULL pointer

Previously if no device tree was passed to microblaze_load_kernel() then qemu_find_file() would try to find a NULL pointer. To avoid this put a check around qemu_find_file(). Signed-off-by: Alistair Francis Reported-by: Peter Maydell ---

[Qemu-devel] [PATCH v5 0/9] Add the ZynqMP PMU and IPI

This series adds the ZynqMP Power Management Unit (PMU) machine with basic functionality. The machine only has the - CPU - Memory - Interrupt controller - IPI device connected, but that is enough to run some of the ROM and firmware code on the machine The series also adds the IPI device

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 0/6] target/ppc: Rework spapr_caps

On 17/01/18 09:34, David Gibson wrote: > On Tue, Jan 16, 2018 at 03:46:20PM +0100, Andrea Bolognani wrote: >> On Wed, 2018-01-17 at 00:54 +1100, David Gibson wrote: Correct me if I'm wrong, but it seems to me like there's no way to figure out through QMP whether these new machine options

Re: [Qemu-devel] [PATCH v2 31/32] qcow2: Allow configuring the L2 slice size

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > Now that the code is ready to handle L2 slices we can finally add an > option to allow configuring their size. > > An L2 slice is the portion of an L2 table that is read by the qcow2 > cache. Until now the cache was always reading full L2 tables,

Re: [Qemu-devel] [PATCH v2 26/32] qcow2: Update qcow2_truncate() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > The qcow2_truncate() code is mostly independent from whether > we're using L2 slices or full L2 tables, but in full and > falloc preallocation modes new L2 tables are allocated using > qcow2_alloc_cluster_link_l2(). Therefore the code needs to be >

Re: [Qemu-devel] [PATCH v6 20/21] sdhci: implement UHS-I voltage switch

On Thu, Jan 11, 2018 at 12:56 PM, Philippe Mathieu-Daudé wrote: > [based on a patch from Alistair Francis > from qemu/xilinx tag xilinx-v2015.2] > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis

Re: [Qemu-devel] [PATCH v6 11/21] hw/arm/xilinx_zynq: implement SDHCI Spec v2

On Thu, Jan 11, 2018 at 12:56 PM, Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Alistair > --- > hw/arm/xilinx_zynq.c | 64 >

Re: [Qemu-devel] [PATCH v2 25/32] qcow2: Update expand_zero_clusters_in_l1() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > expand_zero_clusters_in_l1() expands zero clusters as a necessary step > to downgrade qcow2 images to a version that doesn't support metadata > zero clusters. This function takes an L1 table (which may or may not > be active) and iterates over all

Re: [Qemu-devel] [PATCH v2 24/32] qcow2: Update qcow2_update_snapshot_refcount() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > qcow2_update_snapshot_refcount() increases the refcount of all > clusters of a given snapshot. In order to do that it needs to load all > its L2 tables and iterate over their entries. Since we'll be loading > L2 slices instead of full tables we need

Re: [Qemu-devel] [PATCH v2 23/32] qcow2: Update zero_single_l2() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > zero_single_l2() limits the number of clusters to be zeroed to the > amount that fits inside an L2 table. Since we'll be loading L2 slices > instead of full tables we need to update that limit. > > Apart from that, this function doesn't need any

Re: [Qemu-devel] [PATCH v2 22/32] qcow2: Update discard_single_l2() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > discard_single_l2() limits the number of clusters to be discarded to > the amount that fits inside an L2 table. Since we'll be loading L2 > slices instead of full tables we need to update that limit. > > Apart from that, this function doesn't need

Re: [Qemu-devel] [PATCH v2 21/32] qcow2: Update handle_alloc() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > handle_alloc() loads an L2 table and limits the number of checked > clusters to the amount that fits inside that table. Since we'll be > loading L2 slices instead of full tables we need to update that limit. > > Apart from that, this function

Re: [Qemu-devel] [PATCH v2 20/32] qcow2: Update handle_copied() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > handle_copied() loads an L2 table and limits the number of checked > clusters to the amount that fits inside that table. Since we'll be > loading L2 slices instead of full tables we need to update that limit. > > Apart from that, this function

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 0/6] target/ppc: Rework spapr_caps

On Tue, Jan 16, 2018 at 03:46:20PM +0100, Andrea Bolognani wrote: > On Wed, 2018-01-17 at 00:54 +1100, David Gibson wrote: > > > Correct me if I'm wrong, but it seems to me like there's no way > > > to figure out through QMP whether these new machine options can be > > > used for a given QEMU

Re: [Qemu-devel] [PATCH v2 19/32] qcow2: Update qcow2_alloc_cluster_link_l2() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > There's a loop in this function that iterates over the L2 entries in a > table, so now we need to assert that it remains within the limits of > an L2 slice. > > Apart from that, this function doesn't need any additional changes, so > this patch

Re: [Qemu-devel] [PATCH x86-next v2] target-i386: add PCID flag to Westmere, Sandy Bridge and Ivy Bridge

On Tue, Jan 16, 2018 at 05:43:44PM +, Daniel P. Berrange wrote: > On Tue, Jan 16, 2018 at 03:08:15PM -0200, Eduardo Habkost wrote: > > [CCing Daniel] [...] > > I still don't understand why OpenStack doesn't let users add or > > modify elements on the domain XML. This isn't the first time I

Re: [Qemu-devel] [PULL v1 0/8] Xilinx queue

On Tue, Jan 16, 2018 at 6:54 AM, Peter Maydell wrote: > On 16 January 2018 at 14:49, Edgar E. Iglesias > wrote: >> This didn't show up on my clang testing, do you mind sharing configure line >> and clang version you use? >> >> @Alistair, it

Re: [Qemu-devel] [PATCH v2 18/32] qcow2: Update qcow2_get_cluster_offset() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > qcow2_get_cluster_offset() checks how many contiguous bytes are > available at a given offset. The returned number of bytes is limited > by the amount that can be addressed without having to load more than > one L2 table. > > Since we'll be loading

Re: [Qemu-devel] [PATCH v2 17/32] qcow2: Update get_cluster_table() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > This patch updates get_cluster_table() to return L2 slices instead of > full L2 tables. > > The code itself needs almost no changes, it only needs to call > offset_to_l2_slice_index() instead of offset_to_l2_index(). This patch > also renames all

Re: [Qemu-devel] [PATCH v2 16/32] qcow2: Update l2_allocate() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > This patch updates l2_allocate() to support the qcow2 cache returning > L2 slices instead of full L2 tables. > > The old code simply gets an L2 table from the cache and initializes it > with zeroes or with the contents of an existing table. With a

[Qemu-devel] [PATCH v3 0/4] linux-user: select CPU type according ELF header values

This idea has been suggested to me before by Philippe Mathieu-Daudé, and recently YunQiang Su has proposed a patch to manage the MIPS r6 case. Based on this, this series tries to clean-up the original patch, and introduces the use for m68k architecture and port the patch from YunQiang Su. v3:

[Qemu-devel] [PATCH v3 3/4] linux-user, m68k: select CPU according to ELF header values

M680x0 doesn't support the same set of instructions as ColdFire, so we can't use "any" CPU type to execute m68020 instructions. We select CPU type ("m68040" or "any" for ColdFire) according to the ELF header. If we can't, we use by default the value used until now: "any". Signed-off-by: Laurent

[Qemu-devel] [PATCH v3 4/4] linux-user: MIPS set cpu to r6 CPU if binary is R6

From: YunQiang Su So here we need to detect the version of binaries and set cpu_model for it. [lv: original patch modified to move code into cpu_get_model()] Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson ---

[Qemu-devel] [PATCH v3 1/4] linux-user: Move CPU type name selection to a function

Instead of a sequence of "#if ... #endif" move the selection to a function in linux-user/*/target_elf.h We can't add them in linux-user/*/target_cpu.h because we will need to include "elf.h" to use ELF flags with eflags, and including "elf.h" in "target_cpu.h" introduces some conflicts in

[Qemu-devel] [PATCH v3 2/4] linux-user: introduce functions to detect CPU type

From: YunQiang Su Add a function to return ELF e_flags and use it to select the CPU model. [lv: split the patch and some cleanup in get_elf_eflags()] Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- Notes:

Re: [Qemu-devel] [PATCH v2 15/32] qcow2: Update l2_load() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > Each entry in the qcow2 L2 cache stores a full L2 table (which uses a > complete cluster in the qcow2 image). A cluster is usually too large > to be used efficiently as the size for a cache entry, so we want to > decouple both values by allowing

Re: [Qemu-devel] [PATCH v2 14/32] qcow2: Add offset_to_l2_slice_index()

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > Similar to offset_to_l2_index(), this function takes a guest offset > and returns the index in the L2 slice that contains its L2 entry. > > An L2 slice has currently the same size as an L2 table (one cluster), > so both functions return the same

Re: [Qemu-devel] [PATCH v2 13/32] qcow2: Add l2_slice_size field to BDRVQcow2State

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > The BDRVQcow2State structure contains an l2_size field, which stores > the number of 64-bit entries in an L2 table. > > For efficiency reasons we want to be able to load slices instead of > full L2 tables, so we need to know how many entries an L2

Re: [Qemu-devel] [PATCH v2 12/32] qcow2: Add offset_to_l1_index()

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > Similar to offset_to_l2_index(), this function returns the index in > the L1 table for a given guest offset. This is only used in a couple > of places and it's not a particularly complex calculation, but it > makes the code a bit more readable. > >

  1   2   3   4   5   >