Re: [Qemu-devel] [PATCH 1/2] target/openrisc: convert to DisasContextBase

On Sun, Feb 18, 2018 at 12:10:46 +0900, Stafford Horne wrote: > On Sat, Feb 17, 2018 at 08:32:36PM -0500, Emilio G. Cota wrote: > > Signed-off-by: Emilio G. Cota > This looks ok to me, and thanks for testing. However, I am not so familiar > with > the DisasContextBase. Is this

[Qemu-devel] [Bug 1211910] Re: Logical to linear address translation is wrong for 32-bit guests on a 64-bit hypervisor

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1211910 Title: Logical to

[Qemu-devel] [Bug 1202289] Re: Windows 2008/7 Guest to Guest Very slow 10-20Mbit/s

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1202289 Title: Windows

[Qemu-devel] [Bug 1299858] Re: qemu all apps crash on OS X 10.6.8

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1299858 Title: qemu all

Re: [Qemu-devel] [PATCH 2/2] target/openrisc: convert to TranslatorOps

On Sat, Feb 17, 2018 at 08:32:37PM -0500, Emilio G. Cota wrote: > Notes: > > - Changed the num_insns test in tb_start to check for > dc->base.num_insns > 1, since when tb_start is first > called in a TB, base.num_insns is already set to 1. > > - Removed DISAS_NEXT from the switch on tb_stop;

Re: [Qemu-devel] [PATCH 1/2] target/openrisc: convert to DisasContextBase

On Sat, Feb 17, 2018 at 08:32:36PM -0500, Emilio G. Cota wrote: > Signed-off-by: Emilio G. Cota Hello, This looks ok to me, and thanks for testing. However, I am not so familiar with the DisasContextBase. Is this something new? It would be good to have a commit message to say

[Qemu-devel] [PATCH 2/2] target/openrisc: convert to TranslatorOps

Notes: - Changed the num_insns test in tb_start to check for dc->base.num_insns > 1, since when tb_start is first called in a TB, base.num_insns is already set to 1. - Removed DISAS_NEXT from the switch on tb_stop; use DISAS_TOO_MANY instead. - Added an assert_not_reached on tb_stop for

[Qemu-devel] [PATCH 0/2] target/openrisc: translator loop conversion

Tested on the image linked from the wiki: https://wiki.qemu.org/Testing/System_Images Boot after decompressing with: or1k-softmmu/qemu-system-or1k -cpu or1200 -M or1k-sim \ -kernel path/to/or1k-linux-4.10 \ -serial stdio -nographic -monitor none Thanks, Emilio

[Qemu-devel] [PATCH 1/2] target/openrisc: convert to DisasContextBase

Signed-off-by: Emilio G. Cota --- target/openrisc/translate.c | 87 ++--- 1 file changed, 43 insertions(+), 44 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 2747b24..0450144 100644 ---

[Qemu-devel] [PATCH] target/m68k: TCGv returned by gen_load() must be freed

Signed-off-by: Laurent Vivier --- target/m68k/translate.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 70c7583621..cb795ed25b 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@

Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 3/3] ppc: Add aCube Sam460ex board

On Fri, 16 Feb 2018, BALATON Zoltan wrote: On Fri, 16 Feb 2018, David Gibson wrote: On Thu, Feb 15, 2018 at 10:27:06PM +0100, BALATON Zoltan wrote: Add emulation of aCube Sam460ex board based on AMCC 460EX embedded SoC. This is not a complete implementation yet with a lot of components still

[Qemu-devel] [PATCH v3] ppc: Add aCube Sam460ex board

Add emulation of aCube Sam460ex board based on AMCC 460EX embedded SoC. This is not a complete implementation yet with a lot of components still missing but enough for the U-Boot firmware to start and to boot a Linux kernel or AROS. Signed-off-by: François Revol Signed-off-by:

Re: [Qemu-devel] [PATCH 0/1] slirp: Add domainname option to slirp's DHCP server

Hello, Benjamin Drung, on ven. 16 févr. 2018 13:55:03 +0100, wrote: > Or should the command line option be simpler, but how should it be specified > then? Maybe > > -net > staticroute=10.0.2.0/24via10.0.2.2,staticroute=192.168.0.0/16via10.0.2.2 I guess > -net

[Qemu-devel] [PATCH 12/19] target/hppa: Convert direct and indirect branches

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 125 --- target/hppa/insns.decode | 34 - 2 files changed, 63 insertions(+), 96 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 11/19] target/hppa: Convert shift, extract, deposit insns

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 217 ++- target/hppa/insns.decode | 15 2 files changed, 96 insertions(+), 136 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 17/19] target/hppa: Convert fp fused multiply-add insns

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 79 target/hppa/insns.decode | 12 2 files changed, 38 insertions(+), 53 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 18/19] target/hppa: Convert fp operate insns

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 757 --- target/hppa/insns.decode | 175 +++ 2 files changed, 498 insertions(+), 434 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 19/19] target/hppa: Merge translate_one into hppa_tr_translate_insn

Now that the implementation is entirely within the generated decode function, eliminate the wrapper. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 11 +++ 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 10/19] target/hppa: Convert conditional branches

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 188 --- target/hppa/insns.decode | 30 2 files changed, 110 insertions(+), 108 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 09/19] target/hppa: Convert fp multiply-add

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 69 target/hppa/insns.decode | 12 + 2 files changed, 52 insertions(+), 29 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 16/19] target/hppa: Convert halt/reset insns

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 49 +++- target/hppa/insns.decode | 5 + 2 files changed, 20 insertions(+), 34 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 15/19] target/hppa: Convert fp indexed memory insns

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 93 target/hppa/insns.decode | 21 +++ 2 files changed, 21 insertions(+), 93 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 14/19] target/hppa: Convert offset memory insns

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 193 ++- target/hppa/insns.decode | 49 2 files changed, 88 insertions(+), 154 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 08/19] target/hppa: Convert indexed memory insns

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 157 ++- target/hppa/insns.decode | 24 2 files changed, 56 insertions(+), 125 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 13/19] target/hppa: Convert arithmetic immediate insns

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 168 +-- target/hppa/insns.decode | 21 ++ 2 files changed, 96 insertions(+), 93 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 01/19] target/hppa: Use DisasContextBase.is_jmp

Instead of returning DisasJumpType, immediately store it. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 971 1 file changed, 487 insertions(+), 484 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 06/19] target/hppa: Convert memory management insns

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 159 +++ target/hppa/insns.decode | 38 +++ 2 files changed, 88 insertions(+), 109 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 05/19] target/hppa: Unify specializations of OR

With decodetree.py, the specializations would conflict so we must have a single entry point for all variants of OR. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 108 +++- 1 file changed, 60

[Qemu-devel] [PATCH 07/19] target/hppa: Convert arithmetic/logical insns

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 337 ++- target/hppa/insns.decode | 40 ++ 2 files changed, 197 insertions(+), 180 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 02/19] target/hppa: Begin using scripts/decodetree.py

Convert the BREAK instruction to start. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 14 +++--- target/hppa/Makefile.objs | 8 target/hppa/insns.decode | 24 3 files changed, 43 insertions(+), 3

[Qemu-devel] [PATCH 03/19] target/hppa: Convert move to/from system registers

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 57 +--- target/hppa/insns.decode | 15 + 2 files changed, 40 insertions(+), 32 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 04/19] target/hppa: Convert remainder of system insns

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 92 ++-- target/hppa/insns.decode | 12 +++ 2 files changed, 55 insertions(+), 49 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 00/19] target/hppa: Convert to decodetree.py

The existing hppa backend uses a lot of mask/compare tables to do decoding beyond the major opcode. Converting the port to the autogenerator makes things lots easier to read. r~ Richard Henderson (19): target/hppa: Use DisasContextBase.is_jmp target/hppa: Begin using scripts/decodetree.py

[Qemu-devel] [PATCH 2/2] hw/mips/boston: Enable pch_gbe ethernet controller

Enable CONFIG_PCH_GBE_PCI in mips64el-softmmu.mak (currently the only default config to enable Boston board support) and create the pch_gbe device when using the Boston board. This provides the board with an ethernet controller matching that found on real Boston boards as part of the Intel EG20T

[Qemu-devel] [PATCH v9 13/14] hw/arm/virt-acpi-build: Add smmuv3 node in IORT table

From: Prem Mallappa This patch builds the smmuv3 node in the ACPI IORT table. The RID space of the root complex, which spans 0x0-0x1 maps to streamid space 0x0-0x1 in smmuv3, which in turn maps to deviceid space 0x0-0x1 in the ITS group. The guest must

[Qemu-devel] [PATCH v9 12/14] hw/arm/virt: Add SMMUv3 to the virt board

From: Prem Mallappa Add code to instantiate an smmuv3 in virt machine. A new iommu integer member is introduced in VirtMachineState to store the type of the iommu in use. Signed-off-by: Prem Mallappa Signed-off-by: Eric Auger

[Qemu-devel] [PATCH v9 09/14] hw/arm/smmuv3: Implement translate callback

This patch implements the IOMMU Memory Region translate() callback. Most of the code relates to the translation configuration decoding and check (STE, CD). Signed-off-by: Eric Auger --- v8 -> v9: - use SMMU_EVENT_STRING macro - get rid of last erro_report's - decode asid

[Qemu-devel] [PATCH v9 11/14] target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route

In case the MSI is translated by an IOMMU we need to fixup the MSI route with the translated address. Signed-off-by: Eric Auger --- v5 -> v6: - use IOMMUMemoryRegionClass API It is still unclear to me if we need to register an IOMMUNotifier to handle any change in the

[Qemu-devel] [PATCH v9 06/14] hw/arm/smmuv3: Queue helpers

We introduce helpers to read/write into the command and event circular queues. smmuv3_write_eventq and smmuv3_cmq_consume will become static in subsequent patches. Invalidation commands are not yet dealt with. We do not cache data that need to be invalidated. This will change with vhost

[Qemu-devel] [PATCH v9 07/14] hw/arm/smmuv3: Implement MMIO write operations

Now we have relevant helpers for queue and irq management, let's implement MMIO write operations. Signed-off-by: Eric Auger --- v7 -> v8: - precise in the commit message invalidation commands are not yet treated. - use new queue helpers - do not decode unhandled

[Qemu-devel] [PATCH v9 04/14] hw/arm/smmuv3: Skeleton

From: Prem Mallappa This patch implements a skeleton for the smmuv3 device. Datatypes and register definitions are introduced. The MMIO region, the interrupts and the queue are initialized. Only the MMIO read operation is implemented here. Signed-off-by: Prem

[Qemu-devel] [PATCH v9 00/14] ARM SMMUv3 Emulation Support

This series implements the emulation code for ARM SMMUv3. SMMUv3 gets instantiated by adding ",iommu=smmuv3" to the virt machine option. VHOST integration will be handled in a separate series. VFIO integration is not targeted at the moment. Only stage 1 and AArch64 PTW are supported. Main

[Qemu-devel] [PATCH v9 14/14] hw/arm/virt: Handle iommu in 2.12 machine type

The new machine type exposes a new "iommu" virt machine option. The SMMUv3 IOMMU is instantiated using -machine virt,iommu=smmuv3. Signed-off-by: Eric Auger --- v7 -> v8: - Revert to machine option, now dubbed "iommu", preparing for virtio instantiation. v5 -> v6:

Re: [Qemu-devel] [Qemu-arm] [PATCH 2/3] hw/sii9022: Add support for Silicon Image SII9022

Hi Linus, On 02/17/2018 11:00 AM, Linus Walleij wrote: > This adds support for emulating the Silicon Image SII9022 DVI/HDMI > bridge. It's not very clever right now, it just acknowledges > the switch into DDC I2C mode and back. Combining this with the > existing DDC I2C emulation gives the right

[Qemu-devel] [PATCH 0/2] MIPS Boston / pch_gbe ethernet support

This short series introduces support for emulating the ethernet controller found in the Intel EG20T Platform Controller Hub, and then enables that device for the MIPS Boston board. This gives the Boston board a network device matching that found on real Boston boards, providing unmodified Boston

[Qemu-devel] [PATCH v9 05/14] hw/arm/smmuv3: Wired IRQ and GERROR helpers

We introduce some helpers to handle wired IRQs and especially GERROR interrupt. SMMU writes GERROR register on GERROR event and SW acks GERROR interrupts by setting GERRORn. The Wired interrupts are edge sensitive hence the pulse usage. Signed-off-by: Eric Auger --- v7

[Qemu-devel] [PATCH v2 63/67] target/arm: Implement SVE floating-point trig multiply-add coefficient

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 4 +++ target/arm/sve_helper.c| 70 ++ target/arm/translate-sve.c | 26 + target/arm/sve.decode | 3 ++ 4 files changed, 103

[Qemu-devel] [PATCH v9 02/14] hw/arm/smmu-common: IOMMU memory region and address space setup

We enumerate all the PCI devices attached to the SMMU and initialize an associated IOMMU memory region and address space. This happens on SMMU base instance init. Those info are stored in SMMUDevice objects. The devices are grouped according to the PCIBus they belong to. A hash table indexed by

[Qemu-devel] [PATCH v2 56/67] target/arm: Implement SVE scatter store vector immediate

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 79 +++--- target/arm/sve.decode | 11 +++ 2 files changed, 65 insertions(+), 25 deletions(-) diff --git a/target/arm/translate-sve.c

[Qemu-devel] [PATCH 1/2] hw/net: Add support for Intel pch_gbe ethernet

This patch introduces support for emulating the ethernet controller found in the Intel EG20T Platform Controller Hub, referred to as pch_gbe for consistency with both Linux & U-Boot. Documentation for the hardware can be found here:

[Qemu-devel] [PATCH v9 08/14] hw/arm/smmuv3: Event queue recording helper

Let's introduce a helper function aiming at recording an event in the event queue. Signed-off-by: Eric Auger --- v8 -> v9: - add SMMU_EVENT_STRING v7 -> v8: - use dma_addr_t instead of hwaddr in smmuv3_record_event() - introduce struct SMMUEventInfo - add

[Qemu-devel] [PATCH v2 66/67] target/arm: Implement SVE floating-point round to integral value

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 14 target/arm/sve_helper.c| 8 + target/arm/translate-sve.c | 80 ++ target/arm/sve.decode | 9 ++ 4 files changed, 111

[Qemu-devel] [PATCH v2 55/67] target/arm: Implement SVE gather loads

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 67 target/arm/sve_helper.c| 75 +++ target/arm/translate-sve.c | 97 ++

[Qemu-devel] [PATCH v9 10/14] hw/arm/smmuv3: Abort on vfio or vhost case

At the moment, the SMMUv3 does not support notification on TLB invalidation. So let's abort as soon as such notifier gets enabled. Signed-off-by: Eric Auger --- hw/arm/smmuv3.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/hw/arm/smmuv3.c

[Qemu-devel] [PATCH v2 65/67] target/arm: Implement SVE floating-point convert to integer

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 30 target/arm/sve_helper.c| 16 +++ target/arm/translate-sve.c | 70 ++ target/arm/sve.decode | 16 +++ 4

[Qemu-devel] [PATCH v2 50/67] target/arm: Implement SVE Floating Point Accumulating Reduction Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 7 ++ target/arm/sve_helper.c| 56 ++ target/arm/translate-sve.c | 42 ++ target/arm/sve.decode | 5 + 4

[Qemu-devel] [PATCH v9 03/14] hw/arm/smmu-common: VMSAv8-64 page table walk

This patch implements the page table walk for VMSAv8-64. Signed-off-by: Eric Auger --- v8 -> v9: - remove guest error log on PTE fetch fault - rename trace functions - fix smmu_page_walk_level_res_invalid_pte last arg - fix PTE_ADDRESS - turn functions into macros - make

[Qemu-devel] [PATCH v2 60/67] target/arm: Implement SVE FP Fast Reduction Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 35 ++ target/arm/sve_helper.c| 61 ++ target/arm/translate-sve.c | 55 +

[Qemu-devel] [PATCH v9 01/14] hw/arm/smmu-common: smmu base device and datatypes

The patch introduces the smmu base device and class for the ARM smmu. Devices for specific versions will be derived from this base device. We also introduce some important datatypes. Signed-off-by: Eric Auger Signed-off-by: Prem Mallappa ---

[Qemu-devel] [PATCH v2 49/67] target/arm: Implement SVE FP Multiply-Add Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 16 ++ target/arm/sve_helper.c| 53 ++ target/arm/translate-sve.c | 41 +++ target/arm/sve.decode | 17

[Qemu-devel] [PATCH v2 46/67] target/arm: Implement SVE load and broadcast quadword

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 51 ++ target/arm/sve.decode | 9 2 files changed, 60 insertions(+) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c

[Qemu-devel] [PATCH v2 51/67] target/arm: Implement SVE load and broadcast element

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 + target/arm/sve_helper.c| 43 target/arm/translate-sve.c | 55 +- target/arm/sve.decode | 5 + 4

[Qemu-devel] [PATCH v2 62/67] target/arm: Implement SVE FP Compare with Zero Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 42 ++ target/arm/sve_helper.c| 45 + target/arm/translate-sve.c | 41 +

Re: [Qemu-devel] [PATCH 3/3] arm/vexpress: Add proper display connector emulation

Hi Linus, On 02/17/2018 11:00 AM, Linus Walleij wrote: > This adds the SiI9022 and EDID I2C devices to the ARM Versatile > Express machine, and selects the two I2C devices necessary in the > arm-softmmy.mak configuration so everything will build smoothly. > > I am implementing proper handling of

[Qemu-devel] [PATCH v2 45/67] target/arm: Implement SVE Memory Contiguous Store Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 29 +++ target/arm/sve_helper.c| 211 + target/arm/translate-sve.c | 68 ++- target/arm/sve.decode | 38 4 files

[Qemu-devel] [PATCH v2 42/67] target/arm: Implement SVE Integer Wide Immediate - Unpredicated Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 25 + target/arm/sve_helper.c| 41 ++ target/arm/translate-sve.c | 135 + target/arm/sve.decode | 26 + 4 files

[Qemu-devel] [PATCH v2 67/67] target/arm: Implement SVE floating-point unary operations

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 14 ++ target/arm/sve_helper.c| 8 target/arm/translate-sve.c | 28 target/arm/sve.decode | 4 4 files changed, 54 insertions(+) diff

[Qemu-devel] [PATCH v2 61/67] target/arm: Implement SVE Floating Point Unary Operations - Unpredicated Group

Signed-off-by: Richard Henderson --- target/arm/helper.h| 8 target/arm/translate-sve.c | 43 +++ target/arm/vec_helper.c| 20 target/arm/sve.decode | 5 + 4 files changed,

[Qemu-devel] [PATCH v2 38/67] target/arm: Implement SVE Partition Break Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 18 target/arm/sve_helper.c| 247 + target/arm/translate-sve.c | 96 ++ target/arm/sve.decode | 19 4 files changed,

[Qemu-devel] [PATCH v2 40/67] target/arm: Implement SVE Integer Compare - Scalars Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 2 + target/arm/sve_helper.c| 31 target/arm/translate-sve.c | 92 ++ target/arm/sve.decode | 8 4 files changed, 133

[Qemu-devel] [PATCH v2 57/67] target/arm: Implement SVE floating-point compare vectors

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 49 +++ target/arm/sve_helper.c| 64 ++ target/arm/translate-sve.c | 41 +

[Qemu-devel] [PATCH v2 64/67] target/arm: Implement SVE floating-point convert precision

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 13 + target/arm/sve_helper.c| 27 +++ target/arm/translate-sve.c | 30 ++ target/arm/sve.decode | 8 4 files

[Qemu-devel] [PATCH v2 54/67] target/arm: Implement SVE prefetches

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 9 + target/arm/sve.decode | 23 +++ 2 files changed, 32 insertions(+) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index

[Qemu-devel] [PATCH v2 59/67] target/arm: Implement SVE Floating Point Multiply Indexed Group

Signed-off-by: Richard Henderson --- target/arm/helper.h| 14 ++ target/arm/translate-sve.c | 44 +++ target/arm/vec_helper.c| 64 ++ target/arm/sve.decode | 19

[Qemu-devel] [PATCH v2 37/67] target/arm: Implement SVE Integer Compare - Immediate Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 44 +++ target/arm/sve_helper.c| 88 ++ target/arm/translate-sve.c | 63 + target/arm/sve.decode

[Qemu-devel] [PATCH v2 31/67] target/arm: Implement SVE conditionally broadcast/extract element

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 2 + target/arm/sve_helper.c| 11 ++ target/arm/translate-sve.c | 299 + target/arm/sve.decode | 20 +++ 4 files changed, 332 insertions(+)

[Qemu-devel] [PATCH v2 52/67] target/arm: Implement SVE store vector/predicate register

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 101 + target/arm/sve.decode | 6 +++ 2 files changed, 107 insertions(+) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index

[Qemu-devel] [PATCH v2 30/67] target/arm: Implement SVE compress active elements

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 3 +++ target/arm/sve_helper.c| 34 ++ target/arm/translate-sve.c | 12 target/arm/sve.decode | 6 ++ 4 files changed, 55 insertions(+)

[Qemu-devel] [PATCH v2 58/67] target/arm: Implement SVE floating-point arithmetic with immediate

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 56 +++ target/arm/sve_helper.c| 68 ++ target/arm/translate-sve.c | 73 ++

[Qemu-devel] [PATCH v2 35/67] target/arm: Implement SVE Select Vectors Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 9 target/arm/sve_helper.c| 55 ++ target/arm/translate-sve.c | 2 ++ target/arm/sve.decode | 6 + 4 files changed, 72

[Qemu-devel] [PATCH v2 29/67] target/arm: Implement SVE Permute - Interleaving Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 15 ++ target/arm/sve_helper.c| 72 ++ target/arm/translate-sve.c | 69 target/arm/sve.decode

[Qemu-devel] [PATCH v2 34/67] target/arm: Implement SVE vector splice (predicated)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 2 ++ target/arm/sve_helper.c| 37 + target/arm/translate-sve.c | 10 ++ target/arm/sve.decode | 3 +++ 4 files changed, 52 insertions(+) diff

[Qemu-devel] [PATCH v2 53/67] target/arm: Implement SVE scatter stores

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 41 ++ target/arm/sve_helper.c| 62 target/arm/translate-sve.c | 71 ++

[Qemu-devel] [PATCH v2 44/67] target/arm: Implement SVE Memory Contiguous Load Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 35 +++ target/arm/sve_helper.c| 235 + target/arm/translate-sve.c | 130 + target/arm/sve.decode | 44 - 4

[Qemu-devel] [PATCH v2 32/67] target/arm: Implement SVE copy to vector (predicated)

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 13 + target/arm/sve.decode | 6 ++ 2 files changed, 19 insertions(+) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 207a22a0bc..fc2a295ab7 100644

[Qemu-devel] [PATCH v2 24/67] target/arm: Implement SVE Bitwise Immediate Group

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 50 ++ target/arm/sve.decode | 17 2 files changed, 67 insertions(+) diff --git a/target/arm/translate-sve.c

[Qemu-devel] [PATCH v2 48/67] target/arm: Implement SVE floating-point arithmetic (predicated)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 77 target/arm/sve_helper.c| 107 + target/arm/translate-sve.c | 47 target/arm/sve.decode

[Qemu-devel] [PATCH v2 41/67] target/arm: Implement FDUP/DUP

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 35 +++ target/arm/sve.decode | 8 2 files changed, 43 insertions(+) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index

[Qemu-devel] [PATCH v2 22/67] target/arm: Implement SVE floating-point trig select coefficient

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 4 target/arm/sve_helper.c| 43 +++ target/arm/translate-sve.c | 19 +++ target/arm/sve.decode | 4 4 files changed, 70

[Qemu-devel] [PATCH v2 25/67] target/arm: Implement SVE Integer Wide Immediate - Predicated Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 10 + target/arm/sve_helper.c| 108 + target/arm/translate-sve.c | 92 ++ target/arm/sve.decode | 17

[Qemu-devel] [PATCH v2 47/67] target/arm: Implement SVE integer convert to floating-point

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 30 +++ target/arm/sve_helper.c| 52 ++ target/arm/translate-sve.c | 92 ++ target/arm/sve.decode | 22

[Qemu-devel] [PATCH v2 23/67] target/arm: Implement SVE Element Count Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 11 ++ target/arm/sve_helper.c| 136 ++ target/arm/translate-sve.c | 274 - target/arm/sve.decode | 30 - 4 files

[Qemu-devel] [PATCH v2 28/67] target/arm: Implement SVE Permute - Predicates Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 6 + target/arm/sve_helper.c| 280 + target/arm/translate-sve.c | 110 ++ target/arm/sve.decode | 18 +++ 4 files changed, 414

[Qemu-devel] [PATCH v2 21/67] target/arm: Implement SVE floating-point exponential accelerator

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 4 +++ target/arm/sve_helper.c| 81 ++ target/arm/translate-sve.c | 22 + target/arm/sve.decode | 7 4 files changed, 114

[Qemu-devel] [PATCH v2 43/67] target/arm: Implement SVE Floating Point Arithmetic - Unpredicated Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 14 +++ target/arm/helper.h| 19 ++ target/arm/translate-sve.c | 41 target/arm/vec_helper.c| 94 ++

[Qemu-devel] [PATCH v2 17/67] target/arm: Implement SVE Index Generation Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 target/arm/sve_helper.c| 40 +++ target/arm/translate-sve.c | 67 ++ target/arm/sve.decode | 14 ++ 4

[Qemu-devel] [PATCH v2 19/67] target/arm: Implement SVE Bitwise Shift - Unpredicated Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 12 +++ target/arm/sve_helper.c| 30 + target/arm/translate-sve.c | 81 ++ target/arm/sve.decode | 26 +++ 4 files

[Qemu-devel] [PATCH v2 26/67] target/arm: Implement SVE Permute - Extract Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 2 ++ target/arm/sve_helper.c| 81 ++ target/arm/translate-sve.c | 29 + target/arm/sve.decode | 9 +- 4 files changed, 120

[Qemu-devel] [PATCH v2 39/67] target/arm: Implement SVE Predicate Count Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 2 + target/arm/sve_helper.c| 14 ++ target/arm/translate-sve.c | 116 + target/arm/sve.decode | 27 +++ 4 files changed, 159

[Qemu-devel] [PATCH v2 14/67] target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 60 + target/arm/sve_helper.c| 127 + target/arm/translate-sve.c | 111 +++

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