Balaton, can you review this please.
On Thu, Jun 21, 2018 at 09:47:51PM -0700, Guenter Roeck wrote:
> sam4660ex (or at least this emulation) does not support the "ibm,cpm" power
> management. As a result, Linux crashes when trying to access it. Remove
> its devicetree node. Also, if/when we boot
On 06/22/2018 03:01 AM, Joel Stanley wrote:
> On 22 June 2018 at 08:09, Cédric Le Goater wrote:
>> The timer controller can be driven by either an external 1MHz clock or
>> by the APB clock. Today, the model makes this assumption that the APB
>> frequency is 24MHz but this is incorrect on the
On 06/22/2018 02:57 AM, Joel Stanley wrote:
> On 22 June 2018 at 08:09, Cédric Le Goater wrote:
>> All Aspeed SoC clocks are driven by an input source clock which can
>> have different frequencies : 24MHz or 25MHz, and also, on the Aspeed
>> AST2400 SoC, 48MHz. The H-PLL (CPU) clock is defined
On 06/20/2018 05:05 AM, Yongbok Kim wrote:
> +static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count,
> +uint8_t gp, uint16_t u)
> +{
> +int counter = 0;
> +TCGv va = tcg_temp_new();
> +TCGv t0 = tcg_temp_new();
> +
> +while (counter != count)
Hi Yongbok,
On 06/20/2018 09:05 AM, Yongbok Kim wrote:
> This series of patches is implementing recently announced nanoMIPS on QEMU.
> nanoMIPS is a variable length ISA containing 16, 32 and 48 bit wide
> instructions. It is designed to be portable at assembly level with other MIPS
> and
sam4660ex (or at least this emulation) does not support the "ibm,cpm" power
management. As a result, Linux crashes when trying to access it. Remove
its devicetree node. Also, if/when we boot the Linux kernel directly,
u-boot will not fix up serial frequencies in the devicetree file, and
serial
Currently during KVM initialization on POWER, kvm_fixup_page_sizes()
rewrites a bunch of information in the cpu state to reflect the
capabilities of the host MMU and KVM. This overwrites the information
that's already there reflecting how the TCG implementation of the MMU will
operate.
This
On 06/20/2018 09:06 AM, Yongbok Kim wrote:
> From: Yongbok Kim
>
> Fix ERET/ERETNC can cause ADEL exception
>
> Signed-off-by: Yongbok Kim
> ---
> target/mips/op_helper.c | 11 ++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/target/mips/op_helper.c
From: BALATON Zoltan
As well as being able to generate its own i2c transactions, the ppc4xx
i2c controller has a DIRECTCNTL register which allows explicit control
of the i2c lines.
Using this register an OS can directly bitbang i2c operations. In
order to let emulated i2c devices respond to
From: Cédric Le Goater
It introduces a base PnvChip class from which the specific processor
chip classes, Pnv8Chip and Pnv9Chip, inherit. Each of them needs to
define an init and a realize routine which will create the controllers
of the target processor. For the moment, the base PnvChip class
From: John Arbuckle
Fix the helper_fpscr_clrbit() function so it correctly sets the FEX
and VX bits.
Determining the value for the Floating Point Status and Control
Register's (FPSCR) FEX bit is suppose to be done like this:
FEX = (VX & VE) | (OX & OE) | (UX & UE) | (ZX & ZE) | (XX & XE))
It
From: BALATON Zoltan
According to PPC440 User Manual PPC440 has multiple opcodes for icbt
instruction: one for compatibility with older cores and two 440
specific opcodes one of which is defined in BookE. QEMU only
implements two of these, add the missing one.
Signed-off-by: BALATON Zoltan
From: BALATON Zoltan
We don't emulate slave mode so related registers are not needed.
[lh]sadr are only retained to avoid too many warnings and simplify
debugging but sdata is not even correct because device has a 4 byte
FIFO instead so just remove this unimplemented register for now.
The intr
From: Cédric Le Goater
Today, when a device requests for IRQ number in a sPAPR machine, the
spapr_irq_alloc() routine first scans the ICSState status array to
find an empty slot and then performs the assignement of the selected
numbers. Split this sequence in two distinct routines :
The way we used to handle KVM allowable guest pagesizes for PAPR guests
required some convoluted checking of memory attached to the guest.
The allowable pagesizes advertised to the guest cpus depended on the memory
which was attached at boot, but then we needed to ensure that any memory
later
The way the POWER Hash Page Table (HPT) MMU is virtualized by KVM HV means
that every page that the guest puts in the pagetables must be truly
physically contiguous, not just GPA-contiguous. In effect this means that
an HPT guest can't use any pagesizes greater than the host page size used
to
From: Cédric Le Goater
On Power9, the thread interrupt presenter has a different type and is
linked to the chip owning the cores.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 21 +++--
hw/ppc/pnv_core.c| 18 +-
spapr capabilities have an apply hook to actually activate (or deactivate)
the feature in the system at reset time. However, a number of capabilities
affect the setup of cpus, and need to be applied to each of them -
including hotplugged cpus for extra complication. To make this simpler,
add an
From: Cédric Le Goater
This moves the details of the ISA bus creation under the LPC model but
more important, the new PnvChip operation will let us choose the chip
class to use when we introduce the different chip classes for Power9
and Power8. It hides away the processor chip controllers from
Previously, the effective values of the various spapr capability flags
were only determined at machine reset time. That was a lazy way of making
sure it was after cpu initialization so it could use the cpu object to
inform the defaults.
But we've now improved the compat checking code so that we
ppc_check_compat() is used in a number of places to check if a cpu object
supports a certain compatiblity mode, subject to various constraints.
It takes a PowerPCCPU *, however it really only depends on the cpu's class.
We have upcoming cases where it would be useful to make compatibility
checks
KVM HV has a restriction that for HPT mode guests, guest pages must be hpa
contiguous as well as gpa contiguous. We have to account for that in
various places. We determine whether we're subject to this restriction
from the SMMU information exposed by KVM.
Planned cleanups to the way we handle
From: Greg Kurz
QEMU implements the "Shared Processor LPAR" (SPLPAR) option, which allows
the hypervisor to time-slice a physical processor into multiple virtual
processor. The intent is to allow more guests to run, and to optimize
processor utilization.
The guest OS can cede idle VCPUs, so
From: Sebastian Bauer
According to the sm501 specs the hardware cursor colors are to be given in
the rgb565 format, but the code currently interprets them as bgr565.
Therefore, the colors of the hardware cursors are wrong in the QEMU
display, e.g., the standard mouse pointer of AmigaOS appears
KVM HV has some limitations (deriving from the hardware) that mean not all
host-cpu supported pagesizes may be usable in the guest. At present this
means that KVM guests and TCG guests may see different available page sizes
even if they notionally have the same vcpu model. This is confusing and
From: Greg Kurz
A per-CPU machine data pointer was recently added to PowerPCCPU. The
motivation is to to hide platform specific details from the core CPU
code. This per-CPU data can hold state which is relevant to the guest
though, eg, Virtual Processor Areas, and we should migrate this state.
From: Cédric Le Goater
spapr_irq_alloc_block and spapr_irq_alloc() are now deprecated.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 80 +-
include/hw/ppc/spapr.h | 4 ---
2 files
From: Cédric Le Goater
The device tree node of the ISA bus was being partially done in
different places. Move all the nodes creation under the same routine.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 51 +++
The paravirtualized PAPR platform sometimes needs to restrict the guest to
using only some of the page sizes actually supported by the host's MMU.
At the moment this is handled in KVM specific code, but for consistency we
want to apply the same limitations to all accelerators.
This makes a start
On 06/20/2018 09:06 AM, Yongbok Kim wrote:
> From: Yongbok Kim
>
> Offset can be larger than 16 bit from nanoMIPS,
> and immediate field can be larger than 16 bits as well.
>
> Signed-off-by: Yongbok Kim
Reviewed-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate.c | 8
> 1
On 06/20/2018 09:06 AM, Yongbok Kim wrote:
> From: Yongbok Kim
>
> BadVaddr shouldn't be updated in Debug Mode
Long-standing issue!
>
> Signed-off-by: Yongbok Kim
Reviewed-by: Philippe Mathieu-Daudé
> ---
> target/mips/helper.c| 4 +++-
> target/mips/op_helper.c | 20
On 06/20/2018 09:05 AM, Yongbok Kim wrote:
> Update gen_flt_ldst() in order to reuse the functions for nanoMIPS
>
> Signed-off-by: Yongbok Kim
Reviewed-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate.c | 15 +++
> 1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff
Okay thanks. I forgot to mention I am running the Gentoo version of
kernel 4.14 series. Here is the configure settings for gcc from my
desktop system used to reproduce the crash that originally occurred on
the hardened server, and even though the desktop system isn't using
hardened profile, this
Hi Zoltan,
On 06/21/2018 05:08 AM, BALATON Zoltan wrote:
> Emulate the i2c part of SM501 which is used to access the EDID info
> from a monitor.
>
> The vmstate structure is changed and its version is increased but
> SM501 is only used on SH and PPC sam460ex machines that don't support
>
On Wed, Jun 20, 2018 at 3:00 AM, Dr. David Alan Gilbert wrote:
> * Zhang Chen (zhangc...@gmail.com) wrote:
> > On Wed, May 16, 2018 at 2:56 AM, Dr. David Alan Gilbert <
> dgilb...@redhat.com
> > > wrote:
> >
> > > * Zhang Chen (zhangc...@gmail.com) wrote:
> > > > From: zhanghailiang
> > > >
> >
On 06/20/2018 05:05 AM, Yongbok Kim wrote:
> Add nanoMIPS pool16c instructions
>
> Signed-off-by: Yongbok Kim
> ---
> target/mips/translate.c | 22 ++
> 1 file changed, 22 insertions(+)
This is a good example of using a subroutine that should be used elsewhere.
Reviewed-by:
On 06/20/2018 05:05 AM, Yongbok Kim wrote:
> +static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
> +{
> +uint32_t op;
> +int rt = mmreg_nanomips(uMIPS_RD(ctx->opcode));
> +int rs = mmreg_nanomips(uMIPS_RS(ctx->opcode));
> +int rd =
On 06/20/2018 05:05 AM, Yongbok Kim wrote:
> Add nanoMIPS 16bit load and store instructions
>
> Signed-off-by: Yongbok Kim
> ---
> target/mips/translate.c | 110
>
> 1 file changed, 110 insertions(+)
>
> diff --git a/target/mips/translate.c
On 06/20/2018 05:05 AM, Yongbok Kim wrote:
> From: Yongbok Kim
>
> Add nanoMIPS OPCODE table
>
> Reference:
> nanoMIPS Base ISA Technical Reference Manual
>
> Signed-off-by: Yongbok Kim
> ---
> target/mips/mips-defs.h | 4 +
> target/mips/translate.c | 670
>
On Thu, Jun 21, 2018 at 11:20:35PM -0300, Philippe Mathieu-Daudé wrote:
> The '--output-sync' option is available since GNU make 4.0.
>
> 5.4.1 Output During Parallel Execution
>
> When running several recipes in parallel the output from each
> recipe appears as soon as it is generated,
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180622003140.164613-1-...@redhat.com
Subject: [Qemu-devel] [PATCH v4 0/2] kvm: limited x86 CPU power management
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
On Thu, Jun 21, 2018 at 06:21:55PM -0700, Siwei Liu wrote:
> On Thu, Jun 21, 2018 at 7:59 AM, Cornelia Huck wrote:
> > On Wed, 20 Jun 2018 22:48:58 +0300
> > "Michael S. Tsirkin" wrote:
> >
> >> On Wed, Jun 20, 2018 at 06:06:19PM +0200, Cornelia Huck wrote:
> >> > In any case, I'm not sure
On Thu, Jun 21, 2018 at 06:07:18PM -0700, Siwei Liu wrote:
> On Thu, Jun 21, 2018 at 11:14 AM, Michael S. Tsirkin wrote:
> > On Wed, Jun 13, 2018 at 01:40:59PM +0800, Jason Wang wrote:
> >>
> >>
> >> On 2018年06月13日 12:24, Samudrala, Sridhar wrote:
> >> > On 6/12/2018 7:38 PM, Jason Wang wrote:
>
On 2018-06-21 18:21:55 -0700, Siwei Liu wrote:
> On Thu, Jun 21, 2018 at 7:59 AM, Cornelia Huck wrote:
> > On Wed, 20 Jun 2018 22:48:58 +0300
> > "Michael S. Tsirkin" wrote:
> >
> >> On Wed, Jun 20, 2018 at 06:06:19PM +0200, Cornelia Huck wrote:
> >> > In any case, I'm not sure anymore why we'd
On Thu, 06/21 15:21, Nishanth Aravamudan wrote:
> When the AioContext changes, we need to associate a LinuxAioState with
> the new AioContext. Use the bdrv_attach_aio_context callback and call
> the new aio_setup_linux_aio(), which will allocate a new AioContext if
> needed, and return errors on
On Thu, Jun 21, 2018 at 09:17:11AM +0200, BALATON Zoltan wrote:
> On Wed, 20 Jun 2018, David Gibson wrote:
> > On Tue, Jun 19, 2018 at 10:52:15AM +0200, BALATON Zoltan wrote:
> > > As well as being able to generate its own i2c transactions, the ppc4xx
> > > i2c controller has a DIRECTCNTL register
On Thu, 06/21 15:21, Nishanth Aravamudan wrote:
> laio_init() can fail for a couple of reasons, which will lead to a NULL
> pointer dereference in laio_attach_aio_context().
>
> To solve this, add a aio_setup_linux_aio() function which is called
> early in raw_open_common. If this fails,
The '--output-sync' option is available since GNU make 4.0.
5.4.1 Output During Parallel Execution
When running several recipes in parallel the output from each
recipe appears as soon as it is generated, with the result that
messages from different recipes may be interspersed, sometimes
Builds only require:
- dtc
- keycodemapdb
- capstone
Signed-off-by: Philippe Mathieu-Daudé
---
Some tests might require ROMs. Can they clone submodules only when required?
---
.travis.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/.travis.yml b/.travis.yml
index
Hi Eric
I want to test your smmu emulation patchset with vfio-pci ethernet device.
Could you kindly give me the NIC type information.
In my test, there is vf probe error for menallox connect 4 NIC and TX Unit
hang error for Intel X540 NIC. That's the reason why I ask this question.
--
Cheers,
Cc'ing Gerd who maintains many hw/display/ files.
On 06/21/2018 09:51 PM, David Gibson wrote:
> On Thu, Jun 21, 2018 at 10:08:21AM +0200, BALATON Zoltan wrote:
>> These are fixes to sm501 emulation that were found while testing with
>> AmigaOS 4.1FE (AmigaOS 4 is known to work on real hardware
On 06/21/2018 05:08 AM, BALATON Zoltan wrote:
> From: Sebastian Bauer
>
> Changing the palette of a color index has as an immediate effect on
> all pixels with the corresponding index on real hardware. Performing a
> full update after a palette change is a simple way to emulate this
> effect.
>
Hi Zoltan,
On 06/21/2018 05:08 AM, BALATON Zoltan wrote:
> These are fixes to sm501 emulation that were found while testing with
> AmigaOS 4.1FE (AmigaOS 4 is known to work on real hardware but we have
> no way to verify it against hardware). While this is mainly to improve
Is it possible to
On 06/21/2018 06:12 PM, no-re...@patchew.org wrote:
> This series seems to have some coding style problems. See output below for
> more information:
>
> Type: series
> Message-id: 20180621184116.910-1-alex.ben...@linaro.org
> Subject: [Qemu-devel] [PATCH] blogposts: add post about the new
On Thu, Jun 21, 2018 at 7:59 AM, Cornelia Huck wrote:
> On Wed, 20 Jun 2018 22:48:58 +0300
> "Michael S. Tsirkin" wrote:
>
>> On Wed, Jun 20, 2018 at 06:06:19PM +0200, Cornelia Huck wrote:
>> > In any case, I'm not sure anymore why we'd want the extra uuid.
>>
>> It's mostly so we can have e.g.
On Thu, Jun 21, 2018 at 11:14 AM, Michael S. Tsirkin wrote:
> On Wed, Jun 13, 2018 at 01:40:59PM +0800, Jason Wang wrote:
>>
>>
>> On 2018年06月13日 12:24, Samudrala, Sridhar wrote:
>> > On 6/12/2018 7:38 PM, Jason Wang wrote:
>> > >
>> > >
>> > > On 2018年06月12日 19:54, Michael S. Tsirkin wrote:
>> >
On Thu, Jun 21, 2018 at 11:41 AM, Alex Bennée wrote:
> Signed-off-by: Alex Bennée
> ---
> _posts/2018-06-21-tcg-testing.md | 129 +++
> 1 file changed, 129 insertions(+)
> create mode 100644 _posts/2018-06-21-tcg-testing.md
>
> diff --git
On 22 June 2018 at 08:09, Cédric Le Goater wrote:
> The timer controller can be driven by either an external 1MHz clock or
> by the APB clock. Today, the model makes this assumption that the APB
> frequency is 24MHz but this is incorrect on the AST2400 SoC. palmetto
> machines use a 48MHz input
On 22 June 2018 at 08:09, Cédric Le Goater wrote:
> The System Control Unit should be initialized first as it drives all
> the configuration of the SoC and other device models.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
> ---
> hw/arm/aspeed_soc.c | 40
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180621184116.910-1-alex.ben...@linaro.org
Subject: [Qemu-devel] [PATCH] blogposts: add post about the new check-tcg
infrastructure
=== TEST SCRIPT BEGIN ===
#!/bin/bash
On 22 June 2018 at 08:09, Cédric Le Goater wrote:
> All Aspeed SoC clocks are driven by an input source clock which can
> have different frequencies : 24MHz or 25MHz, and also, on the Aspeed
> AST2400 SoC, 48MHz. The H-PLL (CPU) clock is defined from a
> calculation using parameters in the H-PLL
On Thu, Jun 21, 2018 at 10:08:21AM +0200, BALATON Zoltan wrote:
> These are fixes to sm501 emulation that were found while testing with
> AmigaOS 4.1FE (AmigaOS 4 is known to work on real hardware but we have
> no way to verify it against hardware). While this is mainly to improve
> sam460ex
Similar to the BootLinuxConsoleX86_64 test:
boot a Linux kernel on a Malta board and verify the serial is working.
This test can be run using:
$ avocado run -t endian:big tests/acceptance
Signed-off-by: Philippe Mathieu-Daudé
---
tests/acceptance/boot_linux_console.py | 38
The board already instantiate the proper devices, we don't want to
add extra devices but connect the chardev to one of the serial already
available.
Signed-off-by: Philippe Mathieu-Daudé
---
scripts/qemu.py| 6 --
tests/acceptance/boot_linux_console.py | 3 ++-
2
Introduce 'arch' and 'endian' namespaces.
For example, all little-endian tests can be run using:
$ avocado run -t endian:little tests/acceptance
Signed-off-by: Philippe Mathieu-Daudé
---
tests/acceptance/boot_linux_console.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
Signed-off-by: Philippe Mathieu-Daudé
---
https://travis-ci.org/philmd/qemu/jobs/395266626
...
LINKx86_64-softmmu/qemu-system-x86_64
JOB ID : a3a56af3c02d193e862ce660aae1d9c72926dcb6
JOB LOG:
/home/travis/avocado/job-results/job-2018-06-21T23.49-a3a56af/job.log
(1/7)
Signed-off-by: Philippe Mathieu-Daudé
---
tests/acceptance/boot_linux_console.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/acceptance/boot_linux_console.py
b/tests/acceptance/boot_linux_console.py
index 98324f7591..f6a34d75a5 100644
---
Tests can change this property to run tests in other
architectures than the host one.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/acceptance/avocado_qemu/__init__.py | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git
Hi,
Another neanderthal approach to add multi-arch acceptance tests using
Avocado.
Since Cleber Rosa work got merged [0], I can restart my previous attempt [1]
at using Avocado in QEMU.
Cleber Rosa rewrote my previous v1 [1], in good python, now this v2 pushes
a bit further:
- we can now run
This adds ability to expose some host CPU power management capabilities
to guests. For intel guests, this is sufficient for guest to enable low
power CPU states on idle. For AMD guests it isn't sufficient, deeper
C-states are entered using System-IO.
When enabled this puts CPU in a low power
With this flag, kvm allows guest to control host CPU power state. This
increases latency for other processes using same host CPU in an
unpredictable way, but if decreases idle entry/exit times for the
running VCPU, so to use it QEMU needs a hint about whether host CPU is
overcommitted, hence the
When guest CPU PM is enabled, and with -cpu host, expose the host CPU
MWAIT leaf in the CPUID so guest can make good PM decisions.
Note: the result is 100% CPU utilization reported by host as host
no longer knows that the CPU is halted.
Signed-off-by: Michael S. Tsirkin
---
target/i386/cpu.h |
On 06/21/18 12:10, Marc-André Lureau wrote:
> What do you think Laszlo?
Apologies, I'm currently lacking the bandwidth to even understand the
question. I'm tagging this message for later; it'll take a while before
I get to it.
Thanks
Laszlo
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180621171925.28925-1-kw...@redhat.com
Subject: [Qemu-devel] [PATCH] file-posix: Implement co versions of discard/flush
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
The System Control Unit should be initialized first as it drives all
the configuration of the SoC and other device models.
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed_soc.c | 40
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git
The timer controller can be driven by either an external 1MHz clock or
by the APB clock. Today, the model makes this assumption that the APB
frequency is 24MHz but this is incorrect on the AST2400 SoC. palmetto
machines use a 48MHz input clock source.
Use the SCU object to get the APB frequency
Hello,
The Aspeed SoC clocks are driven by an input source clock which can
have different frequencies : 24MHz or 25MHz, and also, on the Aspeed
AST2400 SoC, 48MHz. The H-PLL (CPU) clock is defined from a calculation
using parameters in the H-PLL Parameter register or from a predefined
set of
All Aspeed SoC clocks are driven by an input source clock which can
have different frequencies : 24MHz or 25MHz, and also, on the Aspeed
AST2400 SoC, 48MHz. The H-PLL (CPU) clock is defined from a
calculation using parameters in the H-PLL Parameter register or from a
predefined set of frequencies
laio_init() can fail for a couple of reasons, which will lead to a NULL
pointer dereference in laio_attach_aio_context().
To solve this, add a aio_setup_linux_aio() function which is called
early in raw_open_common. If this fails, propagate the error up. The
signature of aio_get_linux_aio() was
laio_init() can fail for a couple of reasons, which will lead to a NULL
pointer dereference in laio_attach_aio_context(), called from
aio_get_linux_aio().
Test case 1:
Set /proc/sys/fs/max-aio-nr to 0. Start a guest with an aio=native
disk.
Result: laio_init() returns NULL due to not
When the AioContext changes, we need to associate a LinuxAioState with
the new AioContext. Use the bdrv_attach_aio_context callback and call
the new aio_setup_linux_aio(), which will allocate a new AioContext if
needed, and return errors on failures. If it fails for any reason,
fallback to
On 06/21/2018 11:59 AM, Vladimir Sementsov-Ogievskiy wrote:
> 20.06.2018 23:58, John Snow wrote:
>> Vladimir, can you jog our memories and let us know which series still
>> need to hit QEMU for 3.0 for safe persistence/migration et al?
>>
>> (Not including any of my own qemu-img patches which
On 06/21/2018 07:01 AM, Paolo Bonzini wrote:
On 08/06/2018 22:07, Daniel Henrique Barboza wrote:
The previous patches implemented a way to deliver an emulated
Block Limits (BL) response for the guest in case the underlying
hardware does not support this page.
However, the approach used is
Hi Justin,
We are trying to use QEMU on Windows Hyper-V environment with whpx enabled
for better performance. We were unable to build QEMU with WHPX support. We
used Ubuntu 18.04 server VM with two libraries (WinHv*.lib) from the latest
Windows 10 SDK to build QEMU and added '--enable-whpx'
On 06/21/2018 08:49 AM, Eric Blake wrote:
> The NBD spec says that behavior is unspecified if the client
> requests 0 length for block status; but since the structured
> reply is documenting as returning a non-zero length, it's
> easier to just diagnose this with an EINVAL error than to
>
Hi,
On 06/21/2018 05:19 PM, Murilo Opsfelder Araujo wrote:
On Thu, Jun 21, 2018 at 07:21:47AM -0300, Daniel Henrique Barboza wrote:
changes in v2 from Marc-Andre Lureau review:
- use error_free() accordingly
- use g_spawn_sync() instead of fork() in run_process_child()
- previous version link:
Hi,
On Thu, Feb 15, 2018 at 10:27:06PM +0100, BALATON Zoltan wrote:
> Remaining patches for Sam460ex emulation. The original cover letter
> with more details is here:
>
> http://lists.nongnu.org/archive/html/qemu-ppc/2017-08/msg00112.html
>
> We'll need to also add binaries for firmware
On 06/21/2018 06:25 AM, Vladimir Sementsov-Ogievskiy wrote:
>>
>
> agree. and this is one more reason to not load bitmaps in inactive mode
> at all. and drop them (after storing) on inactivating.
> I'll make a patch.
Sure. I guess persistent bitmaps that exist when BDRV_O_INACTIVE is set
need
On 06/21/2018 07:08 PM, Paolo Bonzini wrote:
> On 21/06/2018 19:01, Christian Borntraeger wrote:
>> kexec/kdump as well as the bootloader use a subcode of diagnose 308
>> that is supposed to reset the subsystem but not comprise a full
>> "reboot". With the latest refactoring this is now broken
On Thu, Jun 21, 2018 at 07:21:47AM -0300, Daniel Henrique Barboza wrote:
> changes in v2 from Marc-Andre Lureau review:
> - use error_free() accordingly
> - use g_spawn_sync() instead of fork() in run_process_child()
> - previous version link:
>
On 06/21/2018 07:55 AM, Marc-André Lureau wrote:
From: Stefan Berger
The TPM Physical Presence interface consists of an ACPI part, a shared
memory part, and code in the firmware. Users can send messages to the
firmware by writing a code into the shared memory through invoking the
ACPI code.
On 06/20/2018 09:25 AM, Paolo Bonzini wrote:
> +pio_fis_i = is_atapi ? ad->done_atapi_packet : !is_write;
Per DPIOO1, does this go to false for the first DRQ block, or did I
misunderstand? Currently my understanding:
- device->host
DPIOI1
Interrupt bit shall be set.
-
Hmm... Is this a stack size protection fault due to the hardening?
We tried to fix the ATAPI recursion depth issue recently, but caused a
regression that stops us from booting with SeaBIOS (maybe UEFI too?) and
patches are pending to fix this, so sit tight and I'll have a git commit
for you to
Signed-off-by: Alex Bennée
---
_posts/2018-06-21-tcg-testing.md | 129 +++
1 file changed, 129 insertions(+)
create mode 100644 _posts/2018-06-21-tcg-testing.md
diff --git a/_posts/2018-06-21-tcg-testing.md b/_posts/2018-06-21-tcg-testing.md
new file mode 100644
On Tue, Jun 19, 2018 at 05:31:59PM -0400, Babu Moger wrote:
> Remove generic non-intel check while validating hyperthreading support.
> Certain AMD CPUs can support hyperthreading now.
>
> CPU family with TOPOEXT feature can support hyperthreading now.
>
> Signed-off-by: Babu Moger
> Tested-by:
On Tue, Jun 19, 2018 at 05:31:58PM -0400, Babu Moger wrote:
> Enable TOPOEXT feature on EPYC CPU. This is required to support
> hyperthreading on VM guests. Also extend xlevel to 0x801E.
>
> Disable topoext on PC_COMPAT_2_12 and keep xlevel 0x800a.
>
> Signed-off-by: Babu Moger
> ---
>
On Tue, Jun 19, 2018 at 05:31:57PM -0400, Babu Moger wrote:
> This is part of topoext support. To keep the compatibility, it is better
> we support all the combination of nr_cores and nr_threads currently
> supported. By allowing more nr_cores and nr_threads, we might end up with
> more nodes than
12.06.2018 20:26, Vladimir Sementsov-Ogievskiy wrote:
First: this variable was introduced to handle reopens. We need it on
following qcow2_do_open, to don't try loading bitmaps again. So, we are
fixing qcow2_invalidate_cache().
However, if we fix only qcow2_invalidate_cache, iotest 169 fails on
On Thu, Jun 21, 2018 at 04:59:13PM +0200, Cornelia Huck wrote:
> On Wed, 20 Jun 2018 22:48:58 +0300
> "Michael S. Tsirkin" wrote:
>
> > On Wed, Jun 20, 2018 at 06:06:19PM +0200, Cornelia Huck wrote:
> > > In any case, I'm not sure anymore why we'd want the extra uuid.
> >
> > It's mostly so
On Wed, Jun 13, 2018 at 01:40:59PM +0800, Jason Wang wrote:
>
>
> On 2018年06月13日 12:24, Samudrala, Sridhar wrote:
> > On 6/12/2018 7:38 PM, Jason Wang wrote:
> > >
> > >
> > > On 2018年06月12日 19:54, Michael S. Tsirkin wrote:
> > > > On Wed, Jun 06, 2018 at 10:29:03AM +0800, Jason Wang wrote:
>
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