Complete xtensa-semi chardev console implementation: allow reading input
characters from file descriptor 0 and call sys_select_one simcall on it.
Signed-off-by: Max Filippov
---
target/xtensa/xtensa-semi.c | 55 ++---
1 file changed, 52 insertions(+), 3 de
On Sat, Sep 8, 2018 at 6:04 PM Tony Garnock-Jones
wrote:
>
> Bring linux-user write(2) handling into line with linux for the case
> of a 0-byte write with a NULL buffer. Based on a patch originally
> written by Zhuowei Zhang.
>
> Addresses https://bugs.launchpad.net/qemu/+bug/1716292.
>
> From Zhu
Hi,
After noticing Fredrik patch [1] clashes with an ongoing work, I shared my
concerns after the current limitations of CPUMIPSState::insn_flags, having
1 bit left to store more 'Chip specific instructions'.
The first patch drop this restriction,
the second simply add definitions for 2 Toshiba c
Currently this holder is limited to at most 32 flags on
a 32-bit architecture, which lets an unique bit available
for another 'chip specific instructions' flag.
Relax this limit using a 64-bit integer.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h | 2 +-
target/mips/interna
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/mips-defs.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index c8e99791ad..9875bdac82 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -56,6 +56,8 @@
#define
Bring linux-user write(2) handling into line with linux for the case
of a 0-byte write with a NULL buffer. Based on a patch originally
written by Zhuowei Zhang.
Addresses https://bugs.launchpad.net/qemu/+bug/1716292.
>From Zhuowei Zhang's patch
>(https://lists.gnu.org/archive/html/qemu-devel/201
A few fixes since yesterday's v1:
https://lists.gnu.org/archive/html/qemu-devel/2018-09/msg00884.html
- Convert copy_qemu_to_soft80 to qemu_to_soft80, just like the other
conversion functions
- Set fp-test as the program name as reported by itself
- Fix Makefile to include .d files so that dep
By leveraging berkeley's softfloat and testfloat.
fp-test.c is derived from testfloat's testsoftfloat.c. To ease
the tracking of upstream changes to the latter file, fp-test.c
keeps the original camel-case variable naming, and includes
most new code via wrap.inc.c.
Most changes to the original co
These are BSD-licensed so we can add them as submodules.
Signed-off-by: Emilio G. Cota
---
.gitmodules | 6 ++
tests/fp/berkeley-softfloat-3 | 1 +
tests/fp/berkeley-testfloat-3 | 1 +
3 files changed, 8 insertions(+)
create mode 16 tests/fp/berkeley-softfloat-3
creat
On Fri, Sep 07, 2018 at 18:07:29 -0400, Emilio G. Cota wrote:
> You can pull this tree from:
> https://github.com/cota/qemu/tree/fp-test
I just sent a v2; please review that one instead.
Thanks,
Emilio
Le 08/09/2018 à 18:20, Stefan Weil a écrit :
Am 08.09.2018 um 18:14 schrieb Hervé Poussineau:
[...]
diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
index f123b15e3e..f865822e32 100644
--- a/tests/boot-serial-test.c
+++ b/tests/boot-serial-test.c
@@ -75,12 +75,12 @@ typedef struc
Am 08.09.2018 um 18:14 schrieb Hervé Poussineau:
[...]
> diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
> index f123b15e3e..f865822e32 100644
> --- a/tests/boot-serial-test.c
> +++ b/tests/boot-serial-test.c
> @@ -75,12 +75,12 @@ typedef struct testdef {
> static testdef_t tests[
OpenBIOS gained 40p support in 5b20e4cacecb62fb2bdc6867c11d44cddd77c4ff
Use it, instead of relying on an unmaintained and very limited firmware.
Signed-off-by: Hervé Poussineau
---
Changes v2->v3:
- rebased on dgibson/ppc-for-3.1
Changes v1->v2:
- rebased on master
- fixed tests
hw/ppc/prep.c
Le 08/09/2018 à 11:08, Mark Cave-Ayland a écrit :
According to the PReP specification section 6.1.6 "System Interrupt
Assignments", all PCI interrupts are routed via IRQ 15.
In the case of the 40p machine this isn't quite true in that it has a routing
quirk: the LSI SCSI device is always routed
On 8 September 2018 at 15:15, Yan-Jie Wang wrote:
> In macOS, lseek with SEEK_DATA behaves differently.
> It seeks to the next data region even though offset is in the middle of
> a data region. In addition, there may be many data regions without any
> hole among them, like this: |---Data---|---Da
In macOS, lseek with SEEK_DATA behaves differently.
It seeks to the next data region even though offset is in the middle of
a data region. In addition, there may be many data regions without any
hole among them, like this: |---Data---|---Data---|
Because of this, qemu-img convert with raw images a
Hi Aleksandar,
> Please:
>
> - rebase your changes to the latest QEMU code
Sure. V2 applied to 3.0.0 and this v3 applies to HEAD (commit 19b599f7664b).
> - organize the changes in the form of patch series
What kind of granularity do you have in mind? The patch is quite small with
79 insertions
Before, we did not clear callback like handle_output when delete
the virtqueue which may result be segmentfault.
The scene is as follows:
1. Start a vm with multiqueue vhost-net,
2. then we write VIRTIO_PCI_GUEST_FEATURES in PCI configuration to
triger multiqueue disable in this vm which will delet
Hi Fredrik,
> Aleksandar, Aurelien, Maciej -- are you happy with this initial v2 patch?
I have skimmed over and I have a couple of comments. I'll try to
finalise them ASAP, however I'm currently at the GNU Tools Cauldron and
much of my time is taken by the event.
Maciej
On 9/7/18 9:56 AM, Mark Cave-Ayland wrote:
> As part of an upcoming 40p patchset I have a requirement to change the PCI
> configuration of the LSI SCSI. However since commits a64aa5785d "hw:
> Deprecate -drive
> if=scsi with non-onboard HBAs" and b891538e81 "hw/ppc/prep: Fix implicit
> creation o
On 9/8/18 6:08 AM, Mark Cave-Ayland wrote:
> This really lays the groundwork for the upcoming patches: it renames the
> irqs PREPPCIState struct member to pci_irqs (as soon there will be a
> distinction) and then changes the raven IRQ opaque to use PREPPCIState
> instead of just irqs array.
>
> Si
On 9/8/18 6:08 AM, Mark Cave-Ayland wrote:
> According to the PReP specification section 6.1.6 "System Interrupt
> Assignments", all PCI interrupts are routed via IRQ 15.
>
> Instead of mapping each PCI IRQ separately, we introduce an OR gate within the
> raven PCI host bridge and then wire the si
On 9/8/18 6:08 AM, Mark Cave-Ayland wrote:
> Whilst the PReP specification describes how all PCI IRQs are routed via IRQ
> 15 on the interrupt controller, the real 40p machine has routing quirk in
> that the LSI SCSI device is routed to IRQ 13.
>
> This is implemented using a little hack: the exis
》From: Fredrik Noring
》Sent: Friday, September 7, 2018 9:16 PM
》To: Richard Henderson; Aurelien Jarno; Aleksandar Markovic; Maciej W. Rozycki
》Cc: Jürgen Urban; qemu-devel@nongnu.org
》Subject: Re: [PATCH v2] target/mips: Initial support for MIPS R5900
Please:
- rebase your changes to the latest
According to the PReP specification section 6.1.6 "System Interrupt
Assignments", all PCI interrupts are routed via IRQ 15.
Instead of mapping each PCI IRQ separately, we introduce an OR gate within the
raven PCI host bridge and then wire the single output of the OR gate to the
interrupt controlle
Whilst the PReP specification describes how all PCI IRQs are routed via IRQ
15 on the interrupt controller, the real 40p machine has routing quirk in
that the LSI SCSI device is routed to IRQ 13.
This is implemented using a little hack: the existing IRQ routing code uses
(irq_num + (pci_dev->devfn
This really lays the groundwork for the upcoming patches: it renames the
irqs PREPPCIState struct member to pci_irqs (as soon there will be a
distinction) and then changes the raven IRQ opaque to use PREPPCIState
instead of just irqs array.
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/prep.c
According to the PReP specification section 6.1.6 "System Interrupt
Assignments", all PCI interrupts are routed via IRQ 15.
In the case of the 40p machine this isn't quite true in that it has a routing
quirk: the LSI SCSI device is always routed to IRQ 13. At least Linux and
NetBSD compare the mod
On 27/08/18 18:12, BALATON Zoltan wrote:
> On Mon, 27 Aug 2018, Mark Cave-Ayland wrote:
>> According to the PReP specification section 6.1.6 "System Interrupt
>> Assignments", all PCI interrupts are routed via IRQ 15.
>>
>> With this patch applied it is now possible to boot the sandalfoot
>> zImag
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