Signed-off-by: Li Qiang
---
hw/misc/edu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/misc/edu.c b/hw/misc/edu.c
index 0687ffd343..cdcf550dd7 100644
--- a/hw/misc/edu.c
+++ b/hw/misc/edu.c
@@ -342,7 +342,7 @@ static void *edu_fact_thread(void *opaque)
static
Signed-off-by: Eduardo Habkost
---
I'd like to do this in QEMU 3.1. I think it's time to drop
support for old systems that have only Python 2.
We still have a few scripts that are not required for building
QEMU that still work only with Python 2 (iotests being the most
relevant set). Requiring
This patch adds functionality to perform flush from guest
to host over VIRTIO. We are registering a callback based
on 'nd_region' type. virtio_pmem driver requires this special
flush function. For rest of the region types we are registering
existing flush function. Report error returned by host
This patch adds virtio-pmem driver for KVM guest.
Guest reads the persistent memory range information from
Qemu over VIRTIO and registers it on nvdimm_bus. It also
creates a nd_region object with the persistent memory
range information so that existing 'nvdimm/pmem' driver
can reserve this into
This patch series has implementation for "fake DAX".
"fake DAX" is fake persistent memory(nvdimm) in guest
which allows to bypass the guest page cache. This also
implements a VIRTIO based asynchronous flush mechanism.
Sharing guest kernel driver in this patchset with the
changes
On Wed, Sep 19, 2018 at 11:11:22AM +0800, Tao Xu wrote:
> New CPU models mostly inherit features from ancestor Skylake-Server,
> while addin new features: AVX512_VNNI, Intel PT.
> SSBD support for speculative execution
> side channel mitigations.
Comparing to Skylake-Server, the following
On Fri, Oct 12, 2018 at 11:30:39PM +0200, Philippe Mathieu-Daudé wrote:
> Hi Cleber,
>
> On 12/10/2018 18:53, Cleber Rosa wrote:
> > A number of QEMU tests are written in Python, and may benefit
> > from an untainted Python venv.
> >
> > By using make rules, tests that depend on specific Python
The current virtio-*-pci device types actually represent 3
different types of devices:
* virtio 1.0 non-transitional devices
* virtio 1.0 transitional devices
* virtio 0.9 ("legacy device" in virtio 1.0 terminology)
That would be just an annoyance if it didn't break our device/bus
compatibility
Signed-off-by: Philippe Mathieu-Daudé
---
tests/vm/basevm.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/vm/basevm.py b/tests/vm/basevm.py
index b2e0de2022..9f4794898a 100755
--- a/tests/vm/basevm.py
+++ b/tests/vm/basevm.py
@@ -74,7 +74,7 @@ class BaseVM(object):
The 'arch' property gives a hint on which architecture the guest image runs.
This can be use to select the correct QEMU binary path.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/vm/basevm.py | 4 +++-
tests/vm/centos | 1 +
tests/vm/freebsd | 1 +
tests/vm/netbsd | 1 +
Signed-off-by: Philippe Mathieu-Daudé
---
tests/vm/basevm.py | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/tests/vm/basevm.py b/tests/vm/basevm.py
index 9415e7c33a..81a1cb05dd 100755
--- a/tests/vm/basevm.py
+++ b/tests/vm/basevm.py
@@ -177,11 +177,14 @@ class
Signed-off-by: Philippe Mathieu-Daudé
---
tests/vm/basevm.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/vm/basevm.py b/tests/vm/basevm.py
index 2bd32dc6ce..9415e7c33a 100755
--- a/tests/vm/basevm.py
+++ b/tests/vm/basevm.py
@@ -70,7 +70,7 @@ class BaseVM(object):
Signed-off-by: Philippe Mathieu-Daudé
---
tests/vm/basevm.py | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tests/vm/basevm.py b/tests/vm/basevm.py
index 9f4794898a..5caf77d6b8 100755
--- a/tests/vm/basevm.py
+++ b/tests/vm/basevm.py
@@ -200,10 +200,10 @@ class
Signed-off-by: Philippe Mathieu-Daudé
---
scripts/qemu.py| 4
tests/vm/basevm.py | 4 ++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/scripts/qemu.py b/scripts/qemu.py
index f099ce7278..9fc0be4828 100644
--- a/scripts/qemu.py
+++ b/scripts/qemu.py
@@ -26,6 +26,10 @@
Signed-off-by: Philippe Mathieu-Daudé
---
scripts/qemu.py | 2 ++
1 file changed, 2 insertions(+)
diff --git a/scripts/qemu.py b/scripts/qemu.py
index 9fc0be4828..bcd24aad82 100644
--- a/scripts/qemu.py
+++ b/scripts/qemu.py
@@ -27,6 +27,8 @@ LOG = logging.getLogger(__name__)
def
Signed-off-by: Philippe Mathieu-Daudé
---
v3: Use default args.jobs
v2: Add get_default_jobs (Fam suggestion)
---
tests/vm/basevm.py | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/tests/vm/basevm.py b/tests/vm/basevm.py
index 834bc90cc1..2bd32dc6ce 100755
---
Hi Fam,
Few patches I added while testing the VM tests without KVM access.
I doubt many people want to suffer using TCG for VM testing, but
it was handy to debug/support aarch64 VM tests.
Also this could be a useful TCG stress test...?
Since v2:
Avoiding the file copy greatly speeds the process up.
Comparison with network file already cached, stopping after build_image():
Before:
$ time make vm-build-freebsd
real1m38.153s
user1m16.871s
sys 0m19.325s
After:
$ time make vm-build-freebsd
real0m13.512s
user
- Setup MemoryListener in QEMU to get all updates to sysmem, and
forward all RAM updates to remote device process
- Remote device process updates its "system_memory" container using
shared file descriptors provided by SYNC_SYSMEM message
Signed-off-by: Jagannathan Raman
---
hw/qemu-proxy.c
- Define proxy-link object which forms the communication link between
QEMU & emulation program.
- Add functions to configure members of proxy-link object instance.
- Add functions to send and receive messages over the communication
channel.
- Add GMainLoop to handle events received on the
- sync_sysmem_msg_t message format is defined. It is used to send
file descriptors of the RAM regions to remote device
- RAM on the remote device is configured with a set of file descriptors.
Old RAM regions are deleted and new regions, each with an fd, is
added to the RAM.
Signed-off-by:
Hi
The multi-process QEMU project proposal written by John Johnson
is copied below.
This patchset implements part of the proposal.
The goal is to run emulated devices as standalone processes. To begin
with, we've chosen to run lsi53c895a as a standalone process /remote
device, based on the
From: Elena Ufimtseva
Define PCI Device proxy object as a parent of TYPE_PCI_DEVICE.
PCI Proxy Object will register PCI BARs, MemoryRegionOps to handle
access to the BARs and forward those to the remote device.
PCI Proxy object intercepts config space reads and writes. In case
of pci config
Initialize remote process main loop and add the message
handling logic. Handle SYNC_SYSMEM message by updating
its "system_memory" container using shared file descriptors
received from QEMU.
Signed-off-by: Jagannathan Raman
---
hw/scsi/qemu-scsi-dev.c | 71
- PCI host bridge is setup for the remote device process. It is
implemented using remote-pcihost object. It is an extension of the PCI
host bridge setup by QEMU.
- remote-pcihost configures a PCI bus which could be used by the remote
PCI device to latch on to.
Signed-off-by: Jagannathan
- remote-machine object sets up various subsystems of the remote device
process.
- PCI host bridge is instantiated
- RAM, IO & PCI memory regions are initialized
Signed-off-by: Jagannathan Raman
---
exec.c| 3 +-
hw/scsi/qemu-scsi-dev.c | 9 +
- Makefile changes necessary to support the building of the remote device
process is added
- functions that are necessary to compile the code, but are not needed at
run-time are stubbed out
- main() function of remote SCSI device process is implemented
Signed-off-by: Jagannathan Raman
---
Hi Cleber,
On 12/10/2018 18:53, Cleber Rosa wrote:
> This enables the execution of the acceptance tests on Travis.
>
> Because the Travis environment is based on Ubuntu Trusty, it requires
> the python3-pip and python3.4-venv packages.
>
> Signed-off-by: Cleber Rosa
> ---
> .travis.yml | 5
On 12/10/2018 18:53, Cleber Rosa wrote:
> TL;DR
> =
>
> Allow acceptance tests to be run with `make check-acceptance`.
>
> Details
> ===
>
> This introduces a Python virtual environment that will be setup within
> the QEMU build directory, that will contain the exact environment that
>
On 12/10/2018 18:53, Cleber Rosa wrote:
> The acceptance (aka functional, aka Avocado-based) tests are
> Python files located in "tests/acceptance" that need to be run
> with the Avocado libs and test runner.
>
> Let's provide a convenient way for QEMU developers to run them,
> by making use of
Hi Cleber,
On 12/10/2018 18:53, Cleber Rosa wrote:
> A number of QEMU tests are written in Python, and may benefit
> from an untainted Python venv.
>
> By using make rules, tests that depend on specific Python libs
> can set that rule as a requirement, along with rules that require
> the
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> +%pred 24:4
> +%succ 20:4
...
> +@noargs
...
> +@fence . ... . ... %pred %succ
...
> +fence 0 000 0 000 @fence
> +fence_i 0
On 08/10/2018 18:35, Cortland Tölva wrote:
> Provide ioctl definitions for the generic thunk mechanism to
> convert most usbfs calls. Calculate arg size at runtime.
>
> Signed-off-by: Cortland Tölva
> ---
> Changes from v1:
> move some type definitions to patch 3/3
> Changes from v2:
>
RFC v3: https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg01753.html
Changes since RFC v3:
- This is now a proper patch series, since it should not (knowingly)
break anything.
- Rebase on top of rth's tcg-next (ffd8994b90f5), which includes
patch 1 from RFC v3.
- Make the feature
As the following experiments show, this a net perf gain,
particularly for memory-heavy workloads. Experiments
are run on an Intel i7-6700K CPU @ 4.00GHz.
1. System boot + shudown, debian aarch64:
- Before (tb-lock-v3):
Performance counter stats for 'taskset -c 0 ../img/aarch64/die.sh' (10
Currently we evict an entry to the victim TLB when it doesn't match
the current address. But it could be that there's no match because
the current entry is empty (i.e. all -1's, for instance via tlb_flush).
Do not evict the entry to the vtlb in that case.
This change will help us keep track of
Disable for all TCG backends for now.
Signed-off-by: Emilio G. Cota
---
include/exec/cpu-defs.h | 43 +++-
include/exec/cpu_ldst.h | 21 ++
tcg/aarch64/tcg-target.h | 1 +
tcg/arm/tcg-target.h | 1 +
tcg/i386/tcg-target.h| 1 +
tcg/mips/tcg-target.h| 1 +
On 09/10/2018 09:45, Kan Li wrote:
> Summary:
> This is to fix bug https://bugs.launchpad.net/qemu/+bug/1796754.
> It is valid for ifc_buf to be NULL according to
> http://man7.org/linux/man-pages/man7/netdevice.7.html.
>
> Signed-off-by: Kan Li
> ---
> linux-user/syscall.c | 56
On 09/10/2018 09:45, Kan Li wrote:
> Summary:
> This is to fix bug https://bugs.launchpad.net/qemu/+bug/1796754.
> It is valid for ifc_buf to be NULL according to
> http://man7.org/linux/man-pages/man7/netdevice.7.html.
>
> Signed-off-by: Kan Li
> ---
> linux-user/syscall.c | 56
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> +static bool trans_andi(DisasContext *ctx, arg_andi *a, uint32_t insn)
> +{
> +gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm);
> +return true;
> +}
> +static bool trans_slli(DisasContext *ctx, arg_slli *a, uint32_t insn)
> +{
> +
> Subject: [PATCH v5 21/28] target/mips: Add opcodes for nanoMIPS EVA
> instructions
>
> From: Dimitrije Nikolic
>
> Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE,
LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE.
>
> Signed-off-by: Dimitrije Nikolic
> Signed-off-by:
> Subject: [PATCH v5 22/28] target/mips: Add CP0 Config2 to DisasContext
>
> From: Stefan Markovic
>
> Add field corresponding to CP0 Config2 to DisasContext. This is
needed for availability control via Config2 bits.
>
> Signed-off-by: Stefan Markovic
> Signed-off-by: Aleksandar Markovic
> ---
Hi Mao,
On 12/10/2018 14:30, Philippe Mathieu-Daudé wrote:
> Cc'ing Eduardo and Thomas.
>
> On 12/10/2018 13:51, maozy wrote:
>> Hi, Philippe
>>
>> On 10/12/18 5:53 PM, Philippe Mathieu-Daudé wrote:
>>> Hi Mao,
>>>
>>> On 12/10/2018 10:30, Mao Zhongyi wrote:
According to qdev-properties.h,
> Subject: [PATCH v5 25/28] hw/mips: Add Data Scratch Pad RAM
>
>From: Yongbok Kim
>
> The optional Data Scratch Pad RAM (DSPRAM) block provides a
general scratch pad RAM used for temporary storage of data. The
DSPRAM provides a connection to on-chip memory or memory-mapped
registers, which are
> Subject: [PATCH v5 08/28] target/mips: Add CPO PWBase register
>
> From: Yongbok Kim
>
>Add PWBase register (CP0 Register 5, Select 5).
This and several other patches in this series contain letter "O" instead of
digit "0" in their title. This should be corrected.
Aleksandar
On 09/10/2018 18:18, Peter Maydell wrote:
> Our __get_user_e() and __put_user_e() macros cause newer versions
> of clang to generate false-positive -Waddress-of-packed-member
> warnings if they are passed the address of a member of a packed
> struct (see
On 09/10/2018 20:40, Peter Maydell wrote:
> Remove a comment suggesting that we need to call tb_flush()
> after writing the SPARC signal frame trampoline insns.
> This isn't necessary in QEMU, because (even if the guest
> architecture requires explicit icache maintenance) we
> ensure that memory
> Subject: [PATCH v5 04/28] linux-user: Add MIPS-specific prctl() options
>
> From: Stefan Markovic
>
>Add MIPS-specific prctl() options TARGET_PR_SET_FP_MODE and
TARGET_PR_SET_FP_MODE. These values are essentially copied from
linux kernel header include/uapi/linux/prctl.h.
>
>This is done in a
> Subject: [PATCH v5 05/28] linux-user: Add infrastructure for handling
> MIPS-specific prctl()
>
> From: Stefan Markovic
>
>Add infrastructure for handling MIPS-specific prctl(). This is,
for now, just an empty placeholder. The real handling will be
implemented in subsequent patches.
>
>
On 12/10/2018 18:26, Alex Williamson wrote:
> Difficult to make use of if not installed
>
> Fixes: cd1bfd5ef336 ("seabios: update bios and vgabios binaries")
> Signed-off-by: Alex Williamson
Reviewed-by: Philippe Mathieu-Daudé
> ---
>
> Makefile |1 +
> 1 file changed, 1 insertion(+)
>
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> +}
> +static bool trans_lh(DisasContext *ctx, arg_lh *a, uint32_t insn)
Watch your spacing. Otherwise,
Reviewed-by: Richard Henderson
r~
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> +static bool trans_jal(DisasContext *ctx, arg_jal *a, uint32_t insn)
> +{
> +CPURISCVState *env = current_cpu->env_ptr;
> +gen_jal(env, ctx, a->rd, a->imm);
I think you should go ahead and put env into ctx, which is probably where it
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> +#define EX_SH(amount) \
> +static int64_t ex_shift_##amount(int imm) \
> +{ \
> +return imm << amount; \
> +}
The int64_t return doesn't help, because it'll be stored
On Fri, Oct 12, 2018 at 02:24:27PM +1100, David Gibson wrote:
> When the balloon is inflated, we discard memory place in it using madvise()
> with MADV_DONTNEED. And when we deflate it we use MADV_WILLNEED, which
> sounds like it makes sense but is actually unnecessary.
>
> The misleadingly
On 10/12/18 12:41 PM, Richard Henderson wrote:
On 10/11/18 8:24 PM, David Gibson wrote:
When the balloon is inflated, we discard memory place in it using madvise()
with MADV_DONTNEED. And when we deflate it we use MADV_WILLNEED, which
sounds like it makes sense but is actually unnecessary.
On 10/12/18 6:55 AM, Kevin Wolf wrote:
If read-only=off, but auto-read-only=on is given, open the volume
read-write if we have the permissions, but instead of erroring out for
read-only volumes, just degrade to read-only.
Signed-off-by: Kevin Wolf
---
block/iscsi.c | 8 +---
1 file
return false in trans_* instructions is no longer used as a fallback to
the old decoder. We can therefore now use 'return false' to indicate an illegal
instruction.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
.../riscv/insn_trans/trans_privileged.inc.c | 6 ++
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvm.inc.c | 55 ++---
target/riscv/translate.c| 266 +++-
2 files changed, 151 insertions(+), 170 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c
manual decoding in gen_arith() is not necessary with decodetree.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 3 ++-
target/riscv/insn_trans/trans_rvi.inc.c | 21 ++--
target/riscv/translate.c| 33
decodetree handles all instructions now so the fallback is not necessary
anymore.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/translate.c | 23 ---
1 file changed, 23 deletions(-)
diff --git a/target/riscv/translate.c
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as gen_store() did.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 31 --
target/riscv/translate.c| 34 -
with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/translate.c | 32
1 file changed, 32 deletions(-)
diff --git
On Wed, Oct 10, 2018 at 7:27 PM Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> Add support for selecting the Memory Region that the GEM
> will do DMA to.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/net/cadence_gem.c | 59
On 10/11/18 8:24 PM, David Gibson wrote:
> When the balloon is inflated, we discard memory place in it using madvise()
> with MADV_DONTNEED. And when we deflate it we use MADV_WILLNEED, which
> sounds like it makes sense but is actually unnecessary.
>
> The misleadingly named MADV_DONTNEED just
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/Makefile.objs | 9 ++-
target/riscv/insn16.decode | 55 +++
target/riscv/insn_trans/trans_rvc.inc.c | 89 +
target/riscv/translate.c| 88
gen_arith_imm() does a lot of decoding manually, which was hard to read in
case of the shift instructions and is not necessary anymore with decodetree.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 3 +-
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 13 +++
target/riscv/insn_trans/trans_rva.inc.c | 99 +
target/riscv/translate.c| 140
3 files changed, 112 insertions(+), 140
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as gen_load() did.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 44 +
target/riscv/translate.c| 20 ---
2 files
This also removes all functions that now became obsolete.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn16.decode | 34 +-
target/riscv/insn_trans/trans_rvc.inc.c | 107 +
target/riscv/translate.c| 151
On 10/12/18 6:55 AM, Kevin Wolf wrote:
If read-only=off, but auto-read-only=on is given, open the file
read-write if we have the permissions, but instead of erroring out for
read-only files, just degrade to read-only.
Signed-off-by: Kevin Wolf
---
block/gluster.c | 9 +
1 file
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 35 +++
target/riscv/insn_trans/trans_rvf.inc.c | 326
target/riscv/translate.c| 1 +
3 files changed, 362 insertions(+)
create mode 100644
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 28 +++
target/riscv/insn_trans/trans_rvd.inc.c | 313
target/riscv/translate.c| 1 +
3 files changed, 342 insertions(+)
create mode 100644
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvf.inc.c | 70 +
2 files changed, 76 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 79 +
target/riscv/translate.c| 59 ++
2 files changed, 86 insertions(+), 52 deletions(-)
diff --git
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 8 +
target/riscv/insn_trans/trans_rvd.inc.c | 94 +
target/riscv/translate.c| 484 +---
3 files changed, 103 insertions(+), 483 deletions(-)
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 17 +
target/riscv/insn_trans/trans_rvm.inc.c | 87 +
target/riscv/translate.c| 10 +--
3 files changed, 105 insertions(+), 9 deletions(-)
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
falls back to the old decoder.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/Makefile.objs | 10 +++
target/riscv/insn32.decode | 30 +
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode| 13 ++
.../riscv/insn_trans/trans_privileged.inc.c | 111 ++
target/riscv/translate.c | 49 +---
3 files changed, 125 insertions(+), 48
The latter utilizes argument-sets of decodetree such that no manual
decoding is necessary as in gen_branch().
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 56 +
target/riscv/translate.c| 47
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 19 +
target/riscv/insn_trans/trans_rvi.inc.c | 52 +
target/riscv/translate.c| 19 +
3 files changed, 72 insertions(+), 18
we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 36
target/riscv/insn_trans/trans_rvi.inc.c | 221
trans_jalr() is the only caller, so move the code into
trans_jalr().
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 27 +-
target/riscv/translate.c| 38 -
2 files changed, 26
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 8
target/riscv/insn_trans/trans_rvi.inc.c | 20
target/riscv/translate.c| 14 --
3 files changed, 28 insertions(+), 14
Hi,
this patchset converts the RISC-V decoder to decodetree in three major steps:
1) Convert 32-bit instructions to decodetree [Patch 1-14]:
Many of the gen_* functions are called by the decode functions for 16-bit
and 32-bit functions. If we move translation code from the gen_*
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvi.inc.c | 79 +
target/riscv/translate.c| 43 +-
3 files changed, 88 insertions(+), 42
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 17 +++
target/riscv/insn_trans/trans_rva.inc.c | 175
target/riscv/translate.c| 1 +
3 files changed, 193 insertions(+)
create mode 100644
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 15 ++
target/riscv/insn_trans/trans_rvi.inc.c | 71 +
target/riscv/translate.c| 7 ---
3 files changed, 86 insertions(+), 7 deletions(-)
diff
On 10/12/18 6:55 AM, Kevin Wolf wrote:
If read-only=off, but auto-read-only=on is given, just degrade to
read-only.
Signed-off-by: Kevin Wolf
---
block/curl.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Eric Blake
--
Eric Blake, Principal Software Engineer
On Fri, Oct 12, 2018 at 02:24:26PM +1100, David Gibson wrote:
> The virtio-balloon devices was never really thought out for cases
> other than 4kiB pagesize on both guest and host. It works in some
> cases, but in others can be ineffectual or even cause guest memory
> corruption.
>
> This series
On 10/12/18 6:55 AM, Kevin Wolf wrote:
If read-only=off, but auto-read-only=on is given, open the file
read-write if we have the permissions, but instead of erroring out for
read-only files, just degrade to read-only.
Signed-off-by: Kevin Wolf
---
block/file-posix.c | 13 +
1
The acceptance (aka functional, aka Avocado-based) tests are
Python files located in "tests/acceptance" that need to be run
with the Avocado libs and test runner.
Let's provide a convenient way for QEMU developers to run them,
by making use of the tests-venv with the required setup.
Also, while
TL;DR
=
Allow acceptance tests to be run with `make check-acceptance`.
Details
===
This introduces a Python virtual environment that will be setup within
the QEMU build directory, that will contain the exact environment that
tests may require.
There's one current caveat: it requires
A number of QEMU tests are written in Python, and may benefit
from an untainted Python venv.
By using make rules, tests that depend on specific Python libs
can set that rule as a requirement, along with rules that require
the presence or installation of specific libraries.
The
This enables the execution of the acceptance tests on Travis.
Because the Travis environment is based on Ubuntu Trusty, it requires
the python3-pip and python3.4-venv packages.
Signed-off-by: Cleber Rosa
---
.travis.yml | 5 +
1 file changed, 5 insertions(+)
diff --git a/.travis.yml
From: Stefan Markovic
Do following replacements:
ASE_DSPR2 -> ASE_DSP_R2
ASE_DSPR3 -> ASE_DSP_R3
check_dspr2() -> check_dsp_r2()
check_dspr3() -> check_dsp_r3()
Reviewed-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Signed-off-by: Aleksandar Markovic
---
target/mips/internal.h
On 10/12/18 6:55 AM, Kevin Wolf wrote:
Some block drivers have traditionally changed their node to read-only
mode without asking the user. This behaviour has been marked deprecated
since 2.11, expecting users to provide an explicit read-only=on option.
Now that we have auto-read-only=on, enable
From: Yongbok Kim
Update the ITU to utilise SAARI/SAAR registers and add new ITU
Control Register (ICR0).
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
---
hw/mips/cps.c | 8 ++
hw/misc/mips_itu.c | 72 +-
From: Yongbok Kim
The optional Data Scratch Pad RAM (DSPRAM) block provides a
general scratch pad RAM used for temporary storage of data. The
DSPRAM provides a connection to on-chip memory or memory-mapped
registers, which are accessed in parallel with the L1 data
cache to minimize access
From: Dimitrije Nikolic
Implement emulation of nanoMIPS EVA instructions. They are all
part of P.LS.E0 instruction pool, or one of its subpools.
Signed-off-by: Dimitrije Nikolic
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 128
From: Yongbok Kim
Add MSA ASE to MIPS64R2-generic CPU.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
---
target/mips/translate_init.inc.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate_init.inc.c
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