Fam Zheng writes:
> Use error_report for situations that affect user operation (i.e. we're
> actually returning error), and warn_report/warn_report_err when some
> less critical error happened but the user operation can still carry on.
>
> Suggested-by: Markus Armbruster
> Signed-off-by: Fam
+-- On Tue, 23 Oct 2018, Philippe Mathieu-Daudé wrote --+
| > From: Prasad J Pandit
| >
| > Update v1: use ARRAY_SIZE macro
| >-> https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg04826.html
| >
| > -qemu_set_irq(s->handler[bit], (level >> bit) & 1);
| > +if (bit <
Hi Emilio G. Cota (cota),
thank you,
after I free the "ptr",there is no crash occur :)
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Title:
null pointer dereference in tcg_emit_op
Hi Emilio G. Cota (cota),
for point 1, I don't know what you mean about leaking the ptr TCG temp
for point 2. what I want to do is call callback function when execute every
guest instructions
so I think it's not should inset code in .translate_insn. what do you think
about it?
--
You
This can avoid setting OCHIState.num_ports to a negative num.
Signed-off-by: Li Qiang
---
hw/usb/hcd-ohci.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
index 66656a1..c34cf5b 100644
--- a/hw/usb/hcd-ohci.c
+++
On 10/23/18 12:50 AM, Emilio G. Cota wrote:
> On Sun, Oct 21, 2018 at 14:34:25 +0100, Richard Henderson wrote:
>> On 10/19/18 2:06 AM, Emilio G. Cota wrote:
>>> @@ -540,16 +540,16 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
>>> */
>>> atomic_mb_set(>icount_decr.u16.high,
1. You're leaking the "ptr" TCG temp. Fix it, and also test your code with the
--enable-debug-tcg configure flag.
2. Don't insert your helper in .insn_start; you'll have better luck in
.translate_insn.
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On 18/10/18 17:31, Cleber Rosa wrote:
The acceptance (aka functional, aka Avocado-based) tests are
Python files located in "tests/acceptance" that need to be run
with the Avocado libs and test runner.
Let's provide a convenient way for QEMU developers to run them,
by making use of the
On Thu, Oct 18, 2018 at 8:43 PM Mark Cave-Ayland
wrote:
>
> From: Laurent Vivier
>
> This is needed by Quadra 800, this card can run on little-endian
> or big-endian bus.
>
> Signed-off-by: Laurent Vivier
> Tested-by: Hervé Poussineau
Reviewed-by: Philippe Mathieu-Daudé
> ---
>
On 19/10/18 15:38, Daniel P. Berrangé wrote:
Add a QAuthZListFile object type that implements the QAuthZ interface. This
built-in implementation is a proxy around the QAtuhZList object type,
initializing it from an external file, and optionally, automatically
reloading it whenever it changes.
On Sun, Oct 21, 2018 at 14:34:25 +0100, Richard Henderson wrote:
> On 10/19/18 2:06 AM, Emilio G. Cota wrote:
> > @@ -540,16 +540,16 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
> > */
> > atomic_mb_set(>icount_decr.u16.high, 0);
> >
> > -if
On 19/10/18 15:38, Daniel P. Berrangé wrote:
In many cases a single VM will just need to whilelist a single identity
as the allowed user of network services. This is especially the case for
TLS live migration (optionally with NBD storage) where we just need to
whitelist the x509 certificate
On 22/10/18 4:17, yuchenlin via Qemu-devel wrote:
Ping?
On 2018-10-12 17:07, yuchen...@synology.com wrote:
From: yuchenlin
There are 3 virtqueues (ctrl, event and cmd) for virtio scsi device,
but seabios will only set the physical address for the 3rd one (cmd).
Then in
On Sun, Oct 21, 2018 at 14:30:20 +0100, Richard Henderson wrote:
> On 10/19/18 2:06 AM, Emilio G. Cota wrote:
> > @@ -60,7 +60,7 @@ static bool mips_cpu_has_work(CPUState *cs)
> > /* Prior to MIPS Release 6 it is implementation dependent if
> > non-enabled
> > interrupts wake-up the
On Mon, Oct 22, 2018 at 1:59 PM Aleksandar Markovic
wrote:
>
> From: Aleksandar Markovic
>
> This small series adds two corrections for issues reported recently.
>
> Aleksandar Markovic (2):
> target/mips: Fix the title of translate.c
> target/mips: Fix decoding of ALIGN and DALIGN
On Mon, Oct 22, 2018 at 3:34 PM Aleksandar Markovic
wrote:
> > From: Fredrik Noring
> > Subject: [PATCH v8 00/38] target/mips: Limited support for the R5900
> >
> I experienced some build errors (see the end of this mail), so I had to
> exclude some patches, but all others are fine, and had my
On 22/10/18 9:40, Mao Zhongyi wrote:
According to qdev-properties.h, properties of pointer type should
be avoided, it seems a link type property is a good substitution.
Cc: Jan Kiszka
Cc: Peter Maydell
Cc: Gerd Hoffmann
Signed-off-by: Mao Zhongyi
Reviewed-by: Philippe Mathieu-Daudé
On 22/10/18 10:00, yuchenlin--- via Qemu-devel wrote:
From: yuchenlin
Signed-off-by: yuchenlin
Reviewed-by: Philippe Mathieu-Daudé
---
hw/display/vga_int.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/display/vga_int.h b/hw/display/vga_int.h
index 6e4fa48a79..55c418eab5
On Sun, Oct 21, 2018 at 14:17:01 +0100, Richard Henderson wrote:
> On 10/19/18 2:05 AM, Emilio G. Cota wrote:
> > -cpu->interrupt_request &= ~0x01;
> > +cpu_reset_interrupt(cpu, ~0x01);
>
> cpu_reset_interrupt(cpu, 1);
Ouch. Fixed.
> Although this is during vmload, and I'm not sure what
Hi Prasad,
On 22/10/18 20:10, P J P wrote:
From: Prasad J Pandit
While performing gpio write via strongarm_gpio_handler_update
routine, the 'bit' index could access beyond s->handler[28] array.
Add check to avoid OOB access.
Reported-by: Moguofang
Signed-off-by: Prasad J Pandit
---
On 22/10/18 20:40, Maciej W. Rozycki wrote:
On Mon, 22 Oct 2018, Maciej W. Rozycki wrote:
Hi Maciej,
What an odd copy & paste thinko! I can't believe I addressed myself in
the opening of my e-mail. :)
Haha when I saw your mail I thought "weird, there is another Maciej
involved in this
On Sun, Oct 21, 2018 at 14:38:38 +0100, Richard Henderson wrote:
> On 10/21/18 1:53 PM, Richard Henderson wrote:
> > On 10/19/18 2:05 AM, Emilio G. Cota wrote:
> >> To avoid a name clash with the soon-to-be-defined cpu_halted() helper.
> >>
> >> Cc: Laurent Vivier
> >> Signed-off-by: Emilio G.
Under heavy IO (e.g. fio) the queue is not checked frequently enough for
pending commands. As a result some pending commands are timed out by the
linux sym53c8xx driver, which sends SCSI Abort messages for the timed out
commands. The SCSI Abort messages result in linux errors, which show up
in
On Mon, Oct 22, 2018 at 08:36:30PM +0200, Samuel Ortiz wrote:
> This patch set implements support for the ACPI hardware-reduced
> specification.
>
> The changes are coming from the NEMU [1] project where we're defining
> a new x86 machine type: i386/virt. This is an EFI only, ACPI
>
On Sun, Oct 21, 2018 at 13:56:59 +0100, Richard Henderson wrote:
> On 10/19/18 2:05 AM, Emilio G. Cota wrote:
> > @@ -1088,11 +1088,13 @@ static target_ulong h_cede(PowerPCCPU *cpu,
> > sPAPRMachineState *spapr,
> >
> > env->msr |= (1ULL << MSR_EE);
> > hreg_compute_hflags(env);
> > +
What version did this last work on? What version have you tested that
failed? Have you tried the latest QEMU HEAD build? What was the full
command line of your invocation?
** Changed in: qemu
Status: New => Incomplete
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Is this a regression on previous behaviour or has never worked? What is
the command line you used to launch QEMU? What version have you tested
on?
** Changed in: qemu
Status: New => Incomplete
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On Sat, 10/13 02:40, Philippe Mathieu-Daudé wrote:
> Hi Fam,
>
> Few patches I added while testing the VM tests without KVM access.
> I doubt many people want to suffer using TCG for VM testing, but
> it was handy to debug/support aarch64 VM tests.
>
> Also this could be a useful TCG stress
Does this bug occur with a normal build of QEMU or only with your
changes to it?
** Changed in: qemu
Status: In Progress => Invalid
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https://bugs.launchpad.net/bugs/1799200
Hi Aleksandar,
> Pull request with 32 patches from this series is already sent, and I would
> like to avoid sending v2 of that request. Let's wait for some time until
> the pull request is hopefully accepted. There will be most likely another
> one at the beginning of the next week.
>
> We are
Thanks for helping Roman, so I take it my options at this point are wait
for VMEXIT to be implemented or try to find a linux distro that doesn't
require SSE?
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From: Sebastien Boeuf
In order to support PCI hotplug through a hardware-reduced GED, we need
to modify the GED device definition in the DSDT table, so that a PCI hotplug
related interrupt will trigger a new PCI scan.
We also need to modify the DSDT PCI bus definition in order to make sure
a PCI
From: Jing Liu
We only need to expose it through FADT.
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Signed-off-by: Jing Liu
---
hw/acpi/reduced.c | 7 ++-
include/hw/acpi/reduced.h | 2 ++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/acpi/reduced.c
On Mon, 22 Oct 2018, Maciej W. Rozycki wrote:
> Hi Maciej,
What an odd copy & paste thinko! I can't believe I addressed myself in
the opening of my e-mail. :)
Maciej
The ACPI Generic Event Device (GED) is a hardware-reduced specific
device that handles all platform events, including the hotplug ones.
This patch generate the AML code that defines GEDs.
Platforms need to specify their own GedEvent array to describe what kind
of events they want to support
From: Yang Zhong
If the platform is a NUMA enabled, we add the SRAT table to the ACPI
build. It is up to the calling platform to define its own SRAT build
method or use the aml-build.c one.
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Signed-off-by: Yang Zhong
---
hw/acpi/reduced.c | 10
From: Jing Liu
Hardware-reduced ACPI uses SLEEP_CONTROL_REG to enter S5 sleep state.
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Signed-off-by: Jing Liu
---
hw/acpi/aml-build.c | 2 +-
hw/acpi/reduced.c | 15 +++
include/hw/acpi/acpi-defs.h | 1 +
From: Sebastien Boeuf
If the platform is NVDIMM enabled, we add the NFIT table to the ACPI
build.
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Signed-off-by: Sebastien Boeuf
---
hw/acpi/reduced.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/acpi/reduced.c
From: Sebastien Boeuf
Instead of using the machine type specific method find_i440fx() to
retrieve the PCI bus, this commit aims to rely on the fact that the
PCI bus is known by the structure AcpiPciHpState.
When the structure is initialized through acpi_pcihp_init() call,
it saves the PCI bus,
From: Yang Zhong
We add the memory hotplug AML code to the hardware-reduced DSDT.
The memory hotplug event is handled through the GED device.
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Signed-off-by: Yang Zhong
---
hw/acpi/reduced.c | 17 ++---
1 file changed, 14 insertions(+),
We build a minimal set of ACPI hardware-reduced tables: XSDT,
FADT, MADT and a DSDT pointed by a RSDP.
The DSDT only contains one PCI host bridge for now.
This API will be consumed by new x86 machine type but also potentially
by the ARM virt one.
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
In order to decouple ACPI APIs from specific machine types, we are
adding granular firmware build methods to the generic MachineClass
structure. This way, a new machine type can re-use the high level ACPI
APIs and define some custom table build methods, without having to
duplicate most of the
From: Yang Zhong
The ACPI MCFG getter is not x86 specific and could be called from
anywhere within generic ACPI API, so let's export it.
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Paolo Bonzini
Cc: Richard Henderson
Cc: Eduardo Habkost
Cc: Marcel Apfelbaum
Signed-off-by: Yang Zhong
From: Yang Zhong
For PCIe based platform, we need to add an MCFG table to the
hardware-reduced DSDT.
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Signed-off-by: Yang Zhong
Signed-off-by: Samuel Ortiz
---
hw/acpi/reduced.c | 7 +++
1 file changed, 7 insertions(+)
diff --git
All PC machine type derivatives will use the same ACPI table build
methods. But with that change in place, any new x86 machine type will be
able to re-use the acpi-build API and customize part of it by defining
its own ACPI table build methods.
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc:
From: Sebastien Boeuf
The ACPI hotplug support for PCI devices APIs are not x86 or even
machine type specific. In order for future machine types to be able to
re-use that code, we export it through the architecture agnostic
hw/acpi folder.
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Paolo
From: Yang Zhong
When using the generated memory hotplug AML, the iasl
compiler would give the following error:
dsdt.dsl 266: Return (MOST (_UID, Arg0, Arg1, Arg2))
Error 6080 - Called method returns no value ^
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Signed-off-by: Yang Zhong
---
CPU and memory ACPI hotplug are not necessarily handled through SCI
events. For example, with Hardware-reduced ACPI, the GED device will
manage ACPI hotplug entirely.
As a consequence, we make the CPU and memory specific events AML
generation optional. The code will only be added when the method
From: Yang Zhong
The AML build routines for the PCI host bridge and the corresponding
DSDT addition are neither x86 nor PC machine type specific.
We can move them to the architecture agnostic hw/acpi folder, and by
carrying all the needed information through a new AcpiPciBus structure,
we can
From: Yang Zhong
The SRAT ACPI table is not x86 specific and will be needed for the
Hardware-reduced ACPI implementation. So we should export it through the
architecture independent hw/acpi folder.
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Paolo Bonzini
Cc: Richard Henderson
Cc:
This property is currently defined under i386/pc while it only describes
a region size that's eventually fetched from the AML ACPI code.
We can make it more generic and shareable across machine types by moving
it to memory-device.h instead.
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Marcel
From: Yang Zhong
Most of the AML build routines under acpi-build are not even
architecture specific. They can be moved to the more generic hw/acpi
folder where they could be shared across machine types and
architectures.
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Paolo Bonzini
Cc:
From: Yang Zhong
Make it more flexible by having it parsing a PCI host paths array
instead of open coding those paths deep down into the code logic itself.
This will be needed for PCI machine types that are neither emulatiing the
ich9 nor the i440fx chipsets.
Cc: "Michael S. Tsirkin"
Cc: Igor
From: Yang Zhong
The _OSC AML table is almost identical between the i386 Q35 and arm virt
machine types. We can make it slightly more generic and share it across
all PCIe architectures.
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Shannon Zhao
Cc: Peter Maydell
Cc: Marcel Apfelbaum
Cc:
The hardware-reduced API will need to build RSDP as well, so we should
export this routine.
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Paolo Bonzini
Cc: Richard Henderson
Cc: Eduardo Habkost
Cc: Marcel Apfelbaum
Signed-off-by: Samuel Ortiz
---
hw/acpi/aml-build.c | 65
ACPI tables are platform and machine type and even architecture
agnostic, and as such we want to provide an internal ACPI API that
only depends on platform agnostic information.
For the x86 architecture, in order to build ACPI tables independently
from the PC or Q35 machine types, we are moving a
This is going to be needed by the Hardware-reduced ACPI routines.
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Marcel Apfelbaum
Cc: Paolo Bonzini
Cc: Richard Henderson
Cc: Eduardo Habkost
Signed-off-by: Samuel Ortiz
---
hw/acpi/aml-build.c | 8
hw/i386/acpi-build.c
We make the ARM virt ACPI code use the now shared build_rsdp() API from
aml-build.c. By doing so we fix a bug where the ARM implementation was
missing adding both the legacy and extended checksums, which was
building an invalid RSDP table.
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Shannon
This patch set implements support for the ACPI hardware-reduced
specification.
The changes are coming from the NEMU [1] project where we're defining
a new x86 machine type: i386/virt. This is an EFI only, ACPI
hardware-reduced platform and as such we had to implement support
for the latter.
As a
Hi Maciej,
> > I added ASE_MMI flag along with INSN_R5900, I think this fits better in
> > the overall MIPS for QEMU design.
>
> Maciej -- can we add "MMI" under "ASEs implemented" in the kernel too,
> even if it is a vendor-specific architecture extension that normally
> isn't counted as an
On 22/10/18 20:16, Richard Henderson wrote:
In several places we use assert(FEATURE), and assume that if FEATURE
is disabled, all following code is removed as unreachable. Which allows
us to compile-out functions that are only present with FEATURE, and
have a link-time failure if the functions
On 10/22/18 7:16 PM, Richard Henderson wrote:
> + * not marked a noreturn, so the compiler cannot delete code following an
Bah. Peter, if you apply this directly, can you please fix the grammar around
"marked a return" (either s/a/as/ or s/a// sound equally plausible for me).
r~
In several places we use assert(FEATURE), and assume that if FEATURE
is disabled, all following code is removed as unreachable. Which allows
us to compile-out functions that are only present with FEATURE, and
have a link-time failure if the functions remain used.
MinGW does not mark its internal
+-- On Mon, 22 Oct 2018, liqsub1 wrote --+
| +if (bit < sizeof(s->handler) / sizeof(s->handler[0])) {
|
| Maybe you can use ARRAY_SIZE here.
Yes, sent patch v1.
Thank you.
--
Prasad J Pandit / Red Hat Product Security Team
47AF CE69 3A90 54AA 9045 1053 DD13 3D32 FE5B 041F
From: Prasad J Pandit
While performing gpio write via strongarm_gpio_handler_update
routine, the 'bit' index could access beyond s->handler[28] array.
Add check to avoid OOB access.
Reported-by: Moguofang
Signed-off-by: Prasad J Pandit
---
hw/arm/strongarm.c | 4 +++-
1 file changed, 3
> From: Fredrik Noring
>
> Subject: Re: [PATCH v8 00/38] target/mips: Limited support for the R5900
>
> Many thanks, Aleksandar,
>
> > I added ASE_MMI flag along with INSN_R5900, I think this fits better in
> > the overall MIPS for QEMU design.
>
> Maciej -- can we add "MMI" under "ASEs
On 10/21/18 4:21 PM, Peter Maydell wrote:
> On 21 October 2018 at 16:01, Peter Maydell wrote:
>> Any idea what's going on here? tcg/tcg.h has a comment saying
>> * The cmpxchg functions are only defined if HAVE_CMPXCHG128
>> so presumably the issue is that the helper-a64 code is
>> trying to
From: "Edgar E. Iglesias"
Announce 64bit addressing support.
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 16a8455128..d95cc27f58
From: "Edgar E. Iglesias"
This patch series adds initial support for Xilinx's Versal SoC.
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar
Processing Engines, Adaptable Hardware Engines, and
From: "Edgar E. Iglesias"
Add a model of Xilinx Versal SoC.
Signed-off-by: Edgar E. Iglesias
---
default-configs/aarch64-softmmu.mak | 1 +
hw/arm/Makefile.objs| 1 +
hw/arm/xlnx-versal.c| 323
include/hw/arm/xlnx-versal.h
From: "Edgar E. Iglesias"
Add a virtual Xilinx Versal board.
This board is based on the Xilinx Versal SoC. The exact
details of what peripherals are attached to this board
will remain in control of QEMU. QEMU will generate an
FDT on the fly for Linux and other software to auto-discover
From: "Edgar E. Iglesias"
Announce the availability of the various priority queues.
This fixes an issue where guest kernels would miss to
configure secondary queues due to inproper feature bits.
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 8 +++-
1 file changed, 7
Many thanks, Aleksandar,
> I added ASE_MMI flag along with INSN_R5900, I think this fits better in
> the overall MIPS for QEMU design.
Maciej -- can we add "MMI" under "ASEs implemented" in the kernel too,
even if it is a vendor-specific architecture extension that normally
isn't counted as an
Adds a new CPU flag to enable the Enlightened VMCS KVM feature.
QEMU enables KVM_CAP_HYPERV_ENLIGHTENED_VMCS and gets back the
version to be advertised in lower 16 bits of CPUID.0x400A:EAX.
Suggested-by: Ladi Prosek
Signed-off-by: Vitaly Kuznetsov
---
Changes since v1:
- Throw away
Update to kvm/next commit 1e58e5e59148 ("KVM: VMX: enable nested
virtualization by default").
kvm_put_vcpu_events() needs to be fixed as 'pad' was renamed to
'pending' in 'struct kvm_vcpu_events'
Signed-off-by: Vitaly Kuznetsov
---
linux-headers/asm-powerpc/kvm.h | 1 +
Changes since v1 [Roman Kagan]:
- Throw away HV_CPUID_MIN_NESTED.
- Create zeroed 0x4006-0x4009 CPUID leaves.
Hyper-V Enlightened VMCS feature was merged to KVM, enable it in Qemu.
The feature gives us a significant performance boost for Hyper-V on KVM
deployments.
The first patch of
This structure and command have missed qemu version 3.0, so fix it to since
version 3.1.
Signed-off-by: Zhang Chen
---
qapi/migration.json | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/qapi/migration.json b/qapi/migration.json
index 0928f4b727..38d4c41d88 100644
---
I have tried to run the OS and I can confirm that some instructions that
require VMEXIT are not implemented. In your case that's 0F7F or MOVQ
(mem from mmxreg) from MMX. In my case that's 0F11 or MOVUPS(xmmreg1 to
mem) from SSE.
I'd recommend you to run -cpu host,-mmx,-sse for a while, but the
Roman Kagan writes:
> On Fri, Oct 19, 2018 at 01:14:32PM +0200, Vitaly Kuznetsov wrote:
>> --- a/target/i386/kvm.c
>> +++ b/target/i386/kvm.c
>> @@ -798,6 +798,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
>> uint32_t unused;
>> struct kvm_cpuid_entry2 *c;
>> uint32_t signature[3];
>>
On 20/10/2018 01:46, Emilio G. Cota wrote:
>> So it is possible that it was my implementation, and not the approach,
>> what was at fault :-)
> I've just observed a similar hang after adding the "BQL
> pushdown" patches on top of this series. So it's likely that the
> hangs come from those
This shouldn't be "Expired", since the bug is likely still there.
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https://bugs.launchpad.net/bugs/1364501
Title:
Gdb hangs when trying to single-step after an invalid instruction
Igor Mammedov writes:
> On Fri, 19 Oct 2018 17:23:21 -0300
> Eduardo Habkost wrote:
>
>> On Fri, Oct 19, 2018 at 09:53:45PM +0200, Igor Mammedov wrote:
>> > On Fri, 19 Oct 2018 15:44:08 -0300
>> > Eduardo Habkost wrote:
>> >
>> > > On Fri, Oct 19, 2018 at 03:12:31PM +0100, Peter Maydell
On 10/20/18 8:31 PM, Kevin Wolf wrote:
Signed-off-by: Kevin Wolf
---
tests/qemu-iotests/232 | 147 +
tests/qemu-iotests/232.out | 59 +++
tests/qemu-iotests/group | 1 +
3 files changed, 207 insertions(+)
create mode 100755
On Wed, 12 Sep 2018 16:55:25 +0400
Marc-André Lureau wrote:
> The function is only used by a test, move it there.
>
> Signed-off-by: Marc-André Lureau
> ---
> include/hw/qdev-properties.h | 1 -
> hw/core/qdev-properties.c | 9 -
> tests/test-qdev-global-props.c | 18
On Wed, 12 Sep 2018 16:55:24 +0400
Marc-André Lureau wrote:
> global_props is only used for Xen xen_compat_props. It's a static
minor nit:
should be AccelClass::global_props
> array of GlobalProperty, like machine globals in SET_MACHINE_COMPAT().
> Let's register the globals the same way,
On Mon, Oct 22, 2018 at 5:27 AM Peter Xu wrote:
>
> On Mon, Oct 22, 2018 at 12:22:02AM -0400, Jintack Lim wrote:
> > Hi,
> >
> > I wonder if vIOMMU is working for Windows VM?
> >
> > I tried it with v2.11.0, but it didn't seem to work. I assume that seaBIOS
> > sets IOMMU on by default as is the
On Fri, 21 Sep 2018 10:17:58 +0200
Eric Auger wrote:
> To prepare for testing yet another extension, let's
> refactor the code. We introduce vfio_iommu_get_type()
> helper which selects the richest API (v2 first). Then
> vfio_init_container() does the SET_CONTAINER and
> SET_IOMMU ioctl calls.
On Fri, Oct 19, 2018 at 01:14:32PM +0200, Vitaly Kuznetsov wrote:
> --- a/target/i386/kvm.c
> +++ b/target/i386/kvm.c
> @@ -798,6 +798,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
> uint32_t unused;
> struct kvm_cpuid_entry2 *c;
> uint32_t signature[3];
> +uint16_t evmcs_version;
>
On Wed, 12 Sep 2018 16:55:23 +0400
Marc-André Lureau wrote:
> Improve a bit code readability.
>
> Signed-off-by: Marc-André Lureau
> ---
> include/qom/object_interfaces.h | 4
> qom/object.c| 4 ++--
> qom/object_interfaces.c | 9 +++--
> 3 files changed,
Use error_report for situations that affect user operation (i.e. we're
actually returning error), and warn_report/warn_report_err when some
less critical error happened but the user operation can still carry on.
Suggested-by: Markus Armbruster
Signed-off-by: Fam Zheng
---
block/file-posix.c |
There are two imports that need to be modified when running the iotests
under Python 3: One is StringIO, which no longer exists; instead, the
StringIO class comes from the io module, so import it from there (and
use the BytesIO class for Python 2). The other is the ConfigParser,
which has just
iotest 169 uses the 'new' module to add methods to a class. This module
no longer exists in Python 3. Instead, we can use a lambda. Best of
all, this works in 2.7 just as well.
Signed-off-by: Max Reitz
Reviewed-by: Eduardo Habkost
Reviewed-by: Cleber Rosa
---
tests/qemu-iotests/169 | 3 +--
Python 3.4 introduced the inheritable attribute for FDs. At the same
time, it changed the default so that all FDs are not inheritable by
default, that only inheritable FDs are inherited to subprocesses, and
only if close_fds is explicitly set to False.
Adhere to this by setting close_fds to
When dumping an object into the log, there are differences between
Python 2 and 3. First, unicode strings are prefixed by 'u' in Python 2
(they are no longer in 3, because unicode strings are the default
there). Second, the order of keys in dicts may differ. Third,
especially long numbers are
In Python 3, several functions now return iterators instead of lists.
This includes range(), items(), map(), and filter(). This means that if
we really want a list, we have to wrap those instances with list(). But
then again, the two instances where this is the case for map() and
filter(), there
After issuing a command, flush the pipe. This does not change anything
in Python 2, but it makes a difference in Python 3.
Signed-off-by: Max Reitz
Reviewed-by: Eduardo Habkost
Reviewed-by: Cleber Rosa
---
tests/qemu-iotests/iotests.py | 1 +
1 file changed, 1 insertion(+)
diff --git
In Python 3, / is always a floating-point division. We usually do not
want this, and as Python 2.7 understands // as well, change all integer
divisions to use that.
Signed-off-by: Max Reitz
Reviewed-by: Eduardo Habkost
Reviewed-by: Cleber Rosa
---
tests/qemu-iotests/030| 2 +-
When closing a connection, make the nbd-fault-injector flush the socket.
Without this, the output is a bit unreliable with Python 3.
Signed-off-by: Max Reitz
Reviewed-by: Eduardo Habkost
Reviewed-by: Cleber Rosa
Reviewed-by: Eric Blake
---
tests/qemu-iotests/083.out | 9
Since byte strings are no longer the default in Python 3, we have to
explicitly use them where we need to, which is mostly when working with
structures. It also means that we need to open a file in binary mode
when we want to use structures.
On the other hand, we have to accomodate for the fact
This series prepares the iotests to work with both Python 2 and 3. In
some places, it adds version-specific code and decides what to do based
on the version (for instance, whether to import the StringIO or the
BytesIO class from 'io' for use with the test runner), but most of the
time, it just
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