I corrected these 2 memory regions based on specifications from the chip
manufacturer. The existing ranges seem to overlap and and cause odd
behavior and/or crashes when trying to set up multiple UARTs,
I also played with changing MAX_SERIAL_PORTS to 8 to match the hardware,
but I did not include t
We've fixed it before like 38bb54f323 ("replication: Make
--disable-replication compile again", 2017-04-28) but it's failing
again. So fix it again.
There could be even cleaner way to fix this but current way is the
simplest. Let's start from simple.
CC: zhanghailiang
CC: Juan Quintela
CC: "D
On Tue 13 Nov 2018 06:06:54 PM CET, Eric Blake wrote:
>> Refcount table entries have a field to store the offset of the
>> refcount block. The rest of the bits of the entry are currently
>> reserved.
>>
>> The offset is always taken from the entry using REFT_OFFSET_MASK to
>> ensure that we only
On Wed, Nov 14, 2018 at 02:41:15PM +0800, Peter Xu wrote:
> On Wed, Nov 14, 2018 at 02:04:44PM +0800, Yu Zhang wrote:
> > The 64-bit key used by vtd_lookup_iotlb() to search the cached
> > mappings is formed by combining the GFN, source id and the page
> > level. To cover 57-bit IOVA, the shift of
On Wed, Nov 14, 2018 at 02:04:44PM +0800, Yu Zhang wrote:
> The 64-bit key used by vtd_lookup_iotlb() to search the cached
> mappings is formed by combining the GFN, source id and the page
> level. To cover 57-bit IOVA, the shift of source id and of page
> level need to be enlarged by 9 - the strid
On Wed, Nov 14, 2018 at 02:04:43PM +0800, Yu Zhang wrote:
> A 5-level paging capable VM may choose to use 57-bit IOVA address width.
> E.g. guest applications may prefer to use its VA as IOVA when performing
> VFIO map/unmap operations, to avoid the burden of managing the IOVA space.
>
> This patc
On Wed, Nov 14, 2018 at 02:04:42PM +0800, Yu Zhang wrote:
> Currently, vIOMMU is using the value of IOVA address width, instead of
> the host address width(HAW) to calculate the number of reserved bits in
> data structures such as root entries, context entries, and entries of
> DMA paging structure
Currently, vIOMMU is using the value of IOVA address width, instead of
the host address width(HAW) to calculate the number of reserved bits in
data structures such as root entries, context entries, and entries of
DMA paging structures etc.
However values of IOVA address width and of the HAW may no
A 5-level paging capable VM may choose to use 57-bit IOVA address width.
E.g. guest applications may prefer to use its VA as IOVA when performing
VFIO map/unmap operations, to avoid the burden of managing the IOVA space.
This patch extends the current vIOMMU logic to cover the extended address
wid
The 64-bit key used by vtd_lookup_iotlb() to search the cached
mappings is formed by combining the GFN, source id and the page
level. To cover 57-bit IOVA, the shift of source id and of page
level need to be enlarged by 9 - the stride of one paging structure
level.
Signed-off-by: Yu Zhang
---
Cc:
Intel's upcoming processors will extend maximum linear address width to
57 bits, and introduce 5-level paging for CPU. Meanwhile, the platform
will also extend the maximum guest address width for IOMMU to 57 bits,
thus introducing the 5-level paging for 2nd level translation(See chapter
3 in Intel
On 2018/11/10 上午3:56, Marc-André Lureau wrote:
-net socket has a fd argument, and may be passed pre-opened sockets.
TCP sockets use framing.
UDP sockets have datagram boundaries.
When given a unix dgram socket, it will be able to read from it, but
will attempt to send on the dgram_dst, which
Hi,
I have briefly tested this patch. Unfortunately, it apparently caused
deteriorated performance on a previously working Windows 10 guest with DMA Buf.
The patched qemu not only clogged up graphics drawing, but also obstructed the
guest OS. The boot time and latency for guest operations (e.g.
On Wed, Nov 14, 2018 at 12:52 PM Palmer Dabbelt wrote:
> The following changes since commit
> cb968d275c145467c8b385a3618a207ec111eab1:
>
> Update version for v3.1.0-rc1 release (2018-11-13 18:16:14 +)
>
> are available in the Git repository at:
>
> git://github.com/riscv/riscv-qemu.git t
On 2018/11/13 下午11:41, Dima Stepanov wrote:
Hi Jason,
I know that this patch has been already merged to stable, but i have a
question:
On Fri, Oct 19, 2018 at 11:22:23AM +0800, Jason Wang wrote:
There should not be a reason for passing a packet size greater than
INT_MAX. It's usually a hint
Nits. Please improve your commit message to make them more impersonal...
On Wed, Nov 14, 2018 at 12:52 PM Palmer Dabbelt wrote:
> Our current fence implementation ignores fences for the user-only
> configurations. This is incorrect but unlikely to manifest: it requires
> multi-threaded user-onl
Paolo Bonzini 于2018年11月14日周三 上午2:27写道：
> On 13/11/2018 11:17, Kevin Wolf wrote:
> > Am 13.11.2018 um 02:45 hat Li Qiang geschrieben:
> >> Ping what't the status of this patch.
> >>
> >> I see Kevin's new pr doesn't contain this patch.
> >
> > Oh, I thought you said that you wanted to fix this
On Mon, Nov 12, 2018 at 22:44:46 +0100, Richard Henderson wrote:
> Based on an idea forwarded by Emilio, which suggests a 5-6%
> speed gain is possible. I have not spent too much time
> measuring this, as the code size gains are significant.
Nice!
> I believe that I posted an x86_64-only patch s
The logs for the VM that gets undefined are no longer available.
Thanks,
Dan
On 11/12/2018 01:26 PM, Dr. David Alan Gilbert wrote:
> Also, can you please include the libvirt logs for the VM, they're
> typically in /var/log/libvirt/VMNAME.log
>
--
You received this bug notification because
On 11/13/18 10:11 AM, Thomas Huth wrote:
> Once a test has finished, the pcibus structure should be freed, to
> avoid leaking memory and to make sure that the structure is properly
> re-initialized when the next test starts.
>
> Signed-off-by: Thomas Huth
> ---
> tests/ide-test.c | 4
>
> On Nov 11, 2018, at 4:35 PM, qemu-devel-requ...@nongnu.org wrote:
>
> It seems that Cocoa checks are stricter on Mojave and some callbacks that
> worked from non-GUI thread on High Sierra are no longer working.
>
> The fixes included here are:
>
> * Deferring qemu_main() to another thread s
This was done with virsh on the cli - not through virt-manager. Virt
manager was only used to see the visual residence of the vm. The exact
command is below:
virsh migrate 79fdd9dd-068b-41cc-b97b-d0f9d8e9df84 --desturi
qemu+ssh://kvmadmin@192.168.0.84/system
after migrating, shutting down the
Gerd Hoffmann, le mar. 13 nov. 2018 08:03:20 +0100, a ecrit:
> Useful when debugging pxeboot, to see what the guest tries to do.
Applied to my tree, thanks!
Samuel
On 11/12/18 2:08 PM, Thomas Huth wrote:
> From: Eric Blake
>
> Managing parallel connections to two different monitors via
> the implicit global_qtest makes it hard to copy-and-paste code
> to tests that are not aware of the implicit state; the
> management of global_qtest is even harder to fo
On 11/12/18 2:06 AM, Marc Olson via Qemu-devel wrote:
> Add a new rule type for blkdebug that instead of returning an error, can
> inject latency to an IO.
>
> Signed-off-by: Marc Olson
> ---
> block/blkdebug.c | 79
> +++---
> docs/devel/blk
From: Bastian Koppelmann
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 18d7b6d1471d..5
From: Alistair Francis
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4a137a503c8a..2b38f890702c 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -240,6 +240,7 @@
From: Bastian Koppelmann
sfence.vm has been replaced in priv v1.10 spec by sfence.vma.
Reported-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 18 +-
1 file changed, 13 inser
Our current fence implementation ignores fences for the user-only
configurations. This is incorrect but unlikely to manifest: it requires
multi-threaded user-only code that takes advantage of the weakness in
the host's memory model and can be inlined by TCG.
This patch simply treats fences the sa
The following changes since commit cb968d275c145467c8b385a3618a207ec111eab1:
Update version for v3.1.0-rc1 release (2018-11-13 18:16:14 +)
are available in the Git repository at:
git://github.com/riscv/riscv-qemu.git tags/riscv-for-master-3.1-rc2
for you to fetch changes up to 3502dc824
On 11/13/18 6:34 PM, Marc Olson wrote:
> On 11/13/18 3:22 PM, John Snow wrote:
>>
>> On 11/12/18 2:06 AM, Marc Olson via Qemu-devel wrote:
>>> Break out the more common parts of the BlkdebugRule struct, and make
>>> rule_check() more explicit about operating only on error injection types
>>> so
On 11/13/18 3:22 PM, John Snow wrote:
On 11/12/18 2:06 AM, Marc Olson via Qemu-devel wrote:
Break out the more common parts of the BlkdebugRule struct, and make
rule_check() more explicit about operating only on error injection types
so that additional rule types can be added in the future.
Si
On Tue, Nov 13, 2018 at 04:58:40PM +, Peter Maydell wrote:
> On 13 November 2018 at 16:52, Samuel Ortiz wrote:
> > From: Philippe Mathieu-Daudé
> >
> > Signed-off-by: Philippe Mathieu-Daudé
> > Reviewed-by: Robert Bradford
> > Reviewed-by: Samuel Ortiz
> > ---
> > target/arm/helper.c | 7
Hi Philippe,
On Tue, Nov 13, 2018 at 07:02:57PM +0100, Philippe Mathieu-Daudé wrote:
> On 13/11/18 18:01, Peter Maydell wrote:
> > On 13 November 2018 at 16:52, Samuel Ortiz wrote:
> > > From: Philippe Mathieu-Daudé
> > >
> > > Signed-off-by: Philippe Mathieu-Daudé
> > > Reviewed-by: Robert Br
On 11/13/18 6:12 AM, xiezhide wrote:
This patch includes two parts:
1. factor out throttle code to reuse code
2. use ThrottleLimits structure
Any time your patch mentions two independent things, you have to ask if
that can be two independent patches. It's fine if they are to
intertwined to s
On 11/12/18 2:06 AM, Marc Olson via Qemu-devel wrote:
> Break out the more common parts of the BlkdebugRule struct, and make
> rule_check() more explicit about operating only on error injection types
> so that additional rule types can be added in the future.
>
> Signed-off-by: Marc Olson
> --
Hi,
This series failed docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: cover.1542110461.git.xiezh...@huawei.com
Subject: [Qemu-devel] [PATCH v2 0/3] fsdev-throt
On 11/12/18 2:06 AM, Marc Olson via Qemu-devel wrote:
> If 'once' is specified, the rule should execute just once, regardless if
> it is supposed to return an error or not. Take the example where you
> want the first IO to an LBA to succeed, but subsequent IOs to fail. You
> could either use sta
As the added iotests shows, we have a (corner case) data corruption
that is user triggerable, therefore, this is still appropriate for
inclusion in 3.1.
v6 was here:
https://lists.gnu.org/archive/html/qemu-devel/2018-06/msg08497.html
since then:
- don't reduce constraints on reftable [Kevin]
- re
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
second release candidate for the QEMU 3.1 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu-project.org/qemu-3.1.0-rc1.tar.xz
http://down
Our code was already checking that we did not attempt to
allocate more clusters than what would fit in an INT64 (the
physical maximimum if we can access a full off_t's worth of
data). But this does not catch smaller limits enforced by
various spots in the qcow2 image description: L1 and normal
clu
If you have a capable file system (tmpfs is good, ext4 not so much;
run ./check with TEST_DIR pointing to a good location so as not
to skip the test), it's actually possible to create a qcow2 file
that expands to a sparse 512T image with just over 38M of content.
The test is not the world's fastest
Although off_t permits up to 63 bits (8EB) of file offsets, in
practice, we're going to hit other limits first. Document some
of those limits in the qcow2 spec, and how choice of cluster size
can influence some of the limits.
While we cannot map any virtual cluster to any address higher than
64 P
Hi,
This series failed docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: cover.1542110461.git.xiezh...@huawei.com
Subject: [Qemu-devel] [PATCH v2 0/3] fsdev-thrott
On Tue, Nov 13, 2018 at 8:29 PM Philippe Mathieu-Daudé
wrote:
> On Tue, Nov 13, 2018 at 8:08 PM Aleksandar Markovic
> wrote:
> >
> > From: Aleksandar Markovic
> >
> > Disable R5900 support. There are some outstanding issues related
> > to ABI support and emulation accuracy, that were not underst
On 6/29/18 10:47 AM, Kevin Wolf wrote:
Am 29.06.2018 um 17:16 hat Eric Blake geschrieben:
On 06/29/2018 04:03 AM, Kevin Wolf wrote:
Am 28.06.2018 um 21:07 hat Eric Blake geschrieben:
When reading a compressed image, we were allocating s->cluster_data
to 32*cluster_size + 512 (possibly over 64
On 11/13/18 8:16 AM, Kevin Wolf wrote:
> Am 12.11.2018 um 20:58 hat John Snow geschrieben:
>>
>>
>> On 11/11/18 4:40 AM, Mark Cave-Ayland wrote:
>>> Commit c8a35f1cf0f "fdc: use IsaDma interface instead of global DMA_*
>>> functions" accidentally introduced a segfault in fdctrl_stop_transfer() f
Hi,
This series failed docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 20181112214224.31560-1-cont...@steffen-goertz.de
Subject: [Qemu-devel] [PATCH v5 00/14] a
On Thu, Nov 8, 2018 at 4:07 AM Bastian Koppelmann
wrote:
>
> Signed-off-by: Bastian Koppelmann
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/translate.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate
On Thu, Nov 8, 2018 at 4:07 AM Bastian Koppelmann
wrote:
>
> sfence.vm has been replaced in priv v1.10 spec by sfence.vma.
>
> Reported-by: Richard Henderson
> Signed-off-by: Bastian Koppelmann
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/translate.c | 18 +-
>
On Thu, Nov 8, 2018 at 5:41 AM Peter Maydell wrote:
>
> In practice for most of the more-or-less orphan Arm board models,
> I will review patches and put them in via the target-arm tree.
> So list myself as an "Odd Fixes" status maintainer for them.
>
> This commit downgrades these boards to "Odd
On 13/11/18 19:46, Peter Maydell wrote:
Add support for running the Coverity Scan tools inside a Docker
container rather than directly on the host system.
Signed-off-by: Peter Maydell
---
scripts/coverity-scan/coverity-scan.docker | 120 +
scripts/coverity-scan/run-coveri
On Tue, Nov 13, 2018 at 8:36 PM Richard Henderson
wrote:
>
> Fixes a TCG crash due to attempting the atomic operation without
> having set up the address first. This does not attempt to fix
> all of the other missing checks for LOCK.
>
> Fixes: a7cee522f35
> Fixes: https://bugs.launchpad.net/qemu
On 11/13/18 1:21 PM, Peter Maydell wrote:
set -e...
+check_upload_permissions() {
...and shell functions do NOT intuitively do what you would think. It's
almost always better to use explicit error checking than to rely on set -e
as a crutch, because then you don't get surprises.
I think
Hi,
This series failed docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 20181112214224.31560-1-cont...@steffen-goertz.de
Subject: [Qemu-devel] [PATCH v5 00/14] ar
Fixes a TCG crash due to attempting the atomic operation without
having set up the address first. This does not attempt to fix
all of the other missing checks for LOCK.
Fixes: a7cee522f35
Fixes: https://bugs.launchpad.net/qemu/+bug/1803160
Signed-off-by: Richard Henderson
---
target/i386/transl
Hi Aleksandar,
On Tue, Nov 13, 2018 at 8:08 PM Aleksandar Markovic
wrote:
>
> From: Aleksandar Markovic
>
> Disable R5900 support. There are some outstanding issues related
> to ABI support and emulation accuracy, that were not understood
> well during review process. Disable to avoid backward c
On 13 November 2018 at 19:06, Eric Blake wrote:
> On 11/13/18 12:46 PM, Peter Maydell wrote:
>>
>> Add a new script to automate the process of running the Coverity
>> Scan build tools and uploading the resulting tarball to the
>> website.
>>
>> This is intended eventually to be driven from Travis,
From: Aleksandar Markovic
Disable R5900 support. There are some outstanding issues related
to ABI support and emulation accuracy, that were not understood
well during review process. Disable to avoid backward compatibility
issues.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate_in
On 11/13/18 12:46 PM, Peter Maydell wrote:
Add a new script to automate the process of running the Coverity
Scan build tools and uploading the resulting tarball to the
website.
This is intended eventually to be driven from Travis,
but it can be run locally, if you are a maintainer of the
QEMU pr
Add support for running the Coverity Scan tools inside a Docker
container rather than directly on the host system.
Signed-off-by: Peter Maydell
---
scripts/coverity-scan/coverity-scan.docker | 120 +
scripts/coverity-scan/run-coverity-scan| 58 ++
2 files changed
This patchset is an attempt to automate the process of
running a Coverity Scan build and uploading it to the website.
(I had a go at this last year; the scripts here are based
on my older attempt, with some changes.)
Patch 1 is a script which will do a build-and-upload. It
requires that you have a
Add a new script to automate the process of running the Coverity
Scan build tools and uploading the resulting tarball to the
website.
This is intended eventually to be driven from Travis,
but it can be run locally, if you are a maintainer of the
QEMU project on the Coverity Scan website and have t
On 02/11/2018 16:40, Keith Busch wrote:
> Hey, so why is this memory region access even considered valid if the
> request is out of range from what NVMe had registered for its
> MemoryRegion? Wouldn't it be better to not call the mr->ops->read/write
> if it's out of bounds? Otherwise every MemoryRe
On 13/11/2018 11:17, Kevin Wolf wrote:
> Am 13.11.2018 um 02:45 hat Li Qiang geschrieben:
>> Ping what't the status of this patch.
>>
>> I see Kevin's new pr doesn't contain this patch.
>
> Oh, I thought you said that you wanted to fix this at a higher level so
> that the problem is caught bef
On Tue, Nov 06, 2018 at 20:20:22 +0800, guangrong.x...@gmail.com wrote:
> From: Xiao Guangrong
>
> This modules implements the lockless and efficient threaded workqueue.
(snip)
> +++ b/util/threaded-workqueue.c
> +struct Threads {
> +/*
> + * in order to avoid contention, the @requests is
Facepalm. I managed to not push the v3 changes anywhere,
so the v4 changes were done on top of v2. Ho hum.
r~
Richard Henderson (4):
target/arm: Install ARMISARegisters from kvm host
target/arm: Fill in ARMISARegisters for kvm64
target/arm: Introduce read_sys_reg32 for kvm32
target/arm
The ID registers are replacing (some of) the feature bits.
We need (some of) these values to determine the set of data
to be handled during migration.
Signed-off-by: Richard Henderson
---
target/arm/kvm_arm.h | 1 +
target/arm/kvm.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/targe
On 13/11/18 18:01, Peter Maydell wrote:
On 13 November 2018 at 16:52, Samuel Ortiz wrote:
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Robert Bradford
Reviewed-by: Samuel Ortiz
---
target/arm/helper.c | 3 ---
1 file changed, 3 deletions(-)
diff --git
Signed-off-by: Richard Henderson
---
target/arm/kvm64.c | 90 --
1 file changed, 88 insertions(+), 2 deletions(-)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 46fbe6d8ff..0a502091e7 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
Assert that the value to be written is the correct size.
No change in functionality here, just mirroring the same
function from kvm64.
Signed-off-by: Richard Henderson
---
target/arm/kvm32.c | 41 -
1 file changed, 16 insertions(+), 25 deletions(-)
diff -
Signed-off-by: Richard Henderson
---
target/arm/kvm32.c | 40 +++-
1 file changed, 35 insertions(+), 5 deletions(-)
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index bc0badf53d..bd51eb43c8 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -4
On 13 November 2018 at 18:02, Philippe Mathieu-Daudé wrote:
> On 13/11/18 18:01, Peter Maydell wrote:
>>
>> On 13 November 2018 at 16:52, Samuel Ortiz wrote:
>>> --- a/target/arm/helper.c
>>> +++ b/target/arm/helper.c
>>> @@ -12,13 +12,10 @@
>>> #include "internals.h"
>>> #include "exec/gdbs
On Tue, Nov 13, 2018 at 7:08 PM Peter Maydell wrote:
> On 13 November 2018 at 18:02, Philippe Mathieu-Daudé
> wrote:
> > On 13/11/18 18:01, Peter Maydell wrote:
> >> On 13 November 2018 at 16:52, Samuel Ortiz wrote:
>
> >>> --- a/target/arm/helper.c
> >>> +++ b/target/arm/helper.c
> >>> @@ -12,
Fix:
TESTlinux-test on i386
.../tests/tcg/multiarch/linux-test.c:201: readdir
readdir() calls getdents64() to have the list of the entries in a
directory, and getdents64() can return 64bit d_off values (with ext4,
for instance) that will not fit in the 32bit d_off field of the
readdir() d
On Thu, Nov 08, 2018 at 02:23:43AM +0400, Marc-André Lureau wrote:
> Hi
>
> On Fri, Oct 19, 2018 at 5:45 PM Daniel P. Berrangé wrote
> > ---
> > Makefile| 7 +-
> > Makefile.objs | 4 +
> > qapi/authz.json | 58
> > qapi/qapi-schema.json | 1 +
On 11/13/18 10:45 AM, Alberto Garcia wrote:
Refcount table entries have a field to store the offset of the
refcount block. The rest of the bits of the entry are currently
reserved.
The offset is always taken from the entry using REFT_OFFSET_MASK to
ensure that we only use the bits that belong to
Public bug reported:
QEMU version:
-
qemu-3.1.0-rc0 compiled from sources (earlier versions also affected)
Summary:
TCG crashes in i386 and x86_64 when it tries to execute some specific
illegal instructions. When running full OS emulation, both the guest
system and QEMU cra
On 11/13/18 2:39 PM, Daniel Henrique Barboza wrote:
On 11/13/18 2:32 PM, Eric Blake wrote:
On 11/13/18 10:09 AM, Daniel Henrique Barboza wrote:
Commit 067927d62e ("qga: systemd hibernate/suspend/hybrid-sleep
support") failed to update qapi-schema.json after adding systemd
hibernate/suspend
This patchset allows for building and running ARM targets with TCG
disabled. It splits the target/arm/helper.c file into logical TCG and
non TCG dependent files so that one can build and run QEMU binaries with
or without TCG enabled.
The rationale behind this work comes from the NEMU project where
On Thu, Nov 08, 2018 at 02:23:48AM +0400, Marc-André Lureau wrote:
> On Fri, Oct 19, 2018 at 5:49 PM Daniel P. Berrangé
> wrote:
> >
> > In many cases a single VM will just need to whilelist a single identity
> > as the allowed user of network services. This is especially the case for
> > TLS liv
They are no longer needed.
Signed-off-by: Samuel Ortiz
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Robert Bradford
---
target/arm/helper.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 689879c23a..dcb6
Group objects with the same build dependencies together.
Signed-off-by: Samuel Ortiz
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Robert Bradford
---
target/arm/Makefile.objs | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --gi
Signed-off-by: Samuel Ortiz
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Robert Bradford
---
target/arm/helper.c| 84 --
target/arm/op_helper.c | 84 ++
2 files changed, 84
It's only used in op_helper.c, it does not need to be exported and
moreover it should only be build when TCG is enabled.
Signed-off-by: Samuel Ortiz
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Robert Bradford
---
target/arm/internals.h | 5 -
target
do_interrupt, do_unaligned_access, do_transaction_failed and debug_excp
are only relevant in the TCG context, so we should not define them
when TCG is disabled.
Signed-off-by: Samuel Ortiz
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Robert Bradford
---
t
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Robert Bradford
Reviewed-by: Samuel Ortiz
---
target/arm/helper.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3d4e9c5c8a..27d9285e1e 100644
--- a/target/ar
Commit 067927d62e ("qga: systemd hibernate/suspend/hybrid-sleep
support") failed to update qapi-schema.json after adding systemd
hibernate/suspend/hybrid-sleep capabilities to guest-suspend-* QGA
commands.
Signed-off-by: Daniel Henrique Barboza
---
qga/qapi-schema.json | 25 ++---
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Robert Bradford
Reviewed-by: Samuel Ortiz
---
target/arm/helper.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 0da1424f72..3d4e9c5c8a 100644
--- a/targ
Since softfloat is only relevant with TCG, we move all ARM VFP helpers
into their own file (vfp_helper.c), in order to support TCG disablement
on ARM.
Signed-off-by: Samuel Ortiz
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewe
On 13 November 2018 at 16:52, Samuel Ortiz wrote:
> From: Philippe Mathieu-Daudé
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Robert Bradford
> Reviewed-by: Samuel Ortiz
> ---
> target/arm/helper.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/target/arm/helper.c
Here again, those APIs are not TCG dependent and can move to the always
built helper.c.
Signed-off-by: Samuel Ortiz
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Robert Bradford
---
target/arm/internals.h | 6 ++
target/arm/helper.c| 204
We can now safely turn all TCG dependent build off when CONFIG_TCG is
off. This allows building ARM binaries with --disable-tcg.
Signed-off-by: Samuel Ortiz
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Robert Bradford
---
target/arm/Makefile.objs | 14 +++
On 11/13/18 10:55 AM, Daniel Henrique Barboza wrote:
Commit 067927d62e ("qga: systemd hibernate/suspend/hybrid-sleep
support") failed to update qapi-schema.json after adding systemd
hibernate/suspend/hybrid-sleep capabilities to guest-suspend-* QGA
commands.
Signed-off-by: Daniel Henrique Barboz
They're not TCG specific and should be living the generic helper file
instead.
Signed-off-by: Samuel Ortiz
Reviewed-by: Robert Bradford
---
target/arm/internals.h | 12 +++
target/arm/translate.h | 7 --
target/arm/helper.c| 214 +
target/a
On Wed, Nov 07, 2018 at 10:26:29PM +0400, Marc-André Lureau wrote:
> On Fri, Oct 19, 2018 at 5:42 PM Daniel P. Berrangé
> wrote:
> >
> > The internal inotify APIs allow alot of conditional statements to be
>
> a lot
>
> > cleared out, and provide a simpler callback for handling events.
> >
> >
On 13 November 2018 at 16:52, Samuel Ortiz wrote:
> From: Philippe Mathieu-Daudé
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Robert Bradford
> Reviewed-by: Samuel Ortiz
> ---
> target/arm/helper.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/target/arm/helper.c b/ta
On 13/11/18 17:58, Peter Maydell wrote:
On 13 November 2018 at 16:52, Samuel Ortiz wrote:
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Robert Bradford
Reviewed-by: Samuel Ortiz
---
target/arm/helper.c | 7 +++
1 file changed, 7 insertions(+)
diff
Most of them are TCG dependent so we want to be able to not build them
in order to support TCG disablement with ARM.
Signed-off-by: Samuel Ortiz
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Robert Bradford
---
target/arm/excp_helper.c | 550 +++
target/arm
Refcount table entries have a field to store the offset of the
refcount block. The rest of the bits of the entry are currently
reserved.
The offset is always taken from the entry using REFT_OFFSET_MASK to
ensure that we only use the bits that belong to that field.
While that mask is used every ti
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