Patchew URL:
https://patchew.org/QEMU/20190214190603.25030-1-peter.mayd...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.mayd...@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm
On Thu, 14 Feb 2019 at 17:47, Aleksandar Markovic
wrote:
>
> From: Aleksandar Markovic
>
> The following changes since commit 7e407466b1efbd65225cc72fe09c0c5ec79df75b:
>
> Merge remote-tracking branch 'remotes/thibault/tags/samuel-thibault' into
> staging (2019-02-14 15:22:29 +)
>
> are
On 14.02.2019 19:44, Paolo Bonzini wrote:
> On 02/02/19 15:45, Kamil Rytarowski wrote:
>>
>> Clang/LLVM on NetBSD with enabled optimization cannot link
>> correct qemu program because of a missing symbol of
>> kvm_arch_get_supported_cpuid() in kvm-stubs.o used by executables.
>
> Can you please
On Wed, 13 Feb 2019 at 08:38, Thomas Huth wrote:
>
> Add Kconfig dependencies for the highbank machine (and the midway
> machine).
> This patch is slightly based on earlier work by Ákos Kovács (i.e.
> his "hw/arm/Kconfig: Add ARM Kconfig" patch).
>
> Signed-off-by: Thomas Huth
> ---
>
On Thu, Feb 14, 2019 at 06:35:47PM +0100, Paolo Bonzini wrote:
> See also "[PATCH for-3.2 00/10] vhost: preparation for qgraph
> conversion of vhost-user-test". Some of the other vhost-user-test
> patches have gone in already, and this is what is left.
>
> These patches are a prerequisite for
From: Richard Henderson
For same-sign saturation, we have tcg vector operations. We can
compute the QC bit by comparing the saturated value against the
unsaturated value.
Signed-off-by: Richard Henderson
Message-id: 20190209033847.9014-12-richard.hender...@linaro.org
Reviewed-by: Peter
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20190209033847.9014-3-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/translate-a64.c | 35 ++-
1 file changed, 14 insertions(+), 21
From: Richard Henderson
Change the representation of this field such that it is easy
to set from vector code.
Signed-off-by: Richard Henderson
Message-id: 20190209033847.9014-11-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/cpu.h
+-- On Wed, 13 Feb 2019, David Gibson wrote --+
| > +
| > +object_class_property_add_str(oc, "host-serial",
| > +machine_get_host_serial, machine_set_host_serial,
| > +_abort);
| > +object_class_property_set_description(oc, "host-serial",
| > +"Set host's system-id
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20190209033847.9014-4-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/translate.c | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff
From: Sandra Loosemore
Per the GDB remote protocol documentation
https://sourceware.org/gdb/current/onlinedocs/gdb/Packets.html#index-vKill-packet
the debug stub is expected to send a reply to the 'vKill' packet. At
least some versions of GDB crash if the gdb stub simply exits without
sending
From: Alex Bennée
Userspace programs should (in theory) query the ELF HWCAP before
probing these registers. Now we have implemented them all make it
public.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-id: 20190205190224.2198-6-alex.ben...@linaro.org
Signed-off-by: Peter
From: Alex Bennée
There are a whole bunch more registers in the CPUID space which are
currently not used but are exposed as RAZ. To avoid too much
duplication we expand ARMCPRegUserSpaceInfo to understand glob
patterns so we only need one entry to tweak whole ranges of registers.
Signed-off-by:
On Thu, Feb 14, 2019 at 07:02:16PM +0100, Stefano Garzarella wrote:
> Some multiboot images could be in the ELF format. In the current
> implementation QEMU fails because we try to load these images
> as a PVH image.
>
> In order to fix this issue, we should try multiboot first (we
> already
The code for handling the NVIC SHPR1 register intends to permit
byte and halfword accesses (as the architecture requires). However
the 'case' line for it only lists the base address of the
register, so attempts to access bytes other than the first one
end up in the "bad write" default logic. This
From: Richard Henderson
Given that we mask bits properly on set, there is no reason
to mask them again on get. We failed to clear the exception
status bits, 0x9f, which means that the wrong value would be
returned on get. Except in the (probably normal) case in which
the set clears all of the
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20190209033847.9014-8-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Alex Bennée
A number of CPUID registers are exposed to userspace by modern Linux
kernels thanks to the "ARM64 CPU Feature Registers" ABI. For QEMU's
user-mode emulation we don't need to emulate the kernels trap but just
return the value the trap would have done. To avoid too much #ifdef
From: Richard Henderson
Fortunately, the functions affected are so far only called from SVE,
so there is no tail to be cleared. But as we convert more of AdvSIMD
to gvec, this will matter.
Signed-off-by: Richard Henderson
Message-id: 20190209033847.9014-13-richard.hender...@linaro.org
From: Alex Bennée
Although technically not visible to userspace the kernel does make
them visible via a trap and emulate ABI. We provide a new permission
mask (PL0U_R) which maps to PL0_R for CONFIG_USER builds and adjust
the minimum permission check accordingly.
Signed-off-by: Alex Bennée
From: Richard Henderson
The 32-bit PMIN/PMAX has been decomposed to scalars,
and so can be trivially expanded inline.
Signed-off-by: Richard Henderson
Message-id: 20190209033847.9014-5-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
From: Richard Henderson
Minimize the code within a macro by splitting out a helper function.
Use deposit32 instead of manual bit manipulation.
Signed-off-by: Richard Henderson
Message-id: 20190209033847.9014-9-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter
From: Richard Henderson
These are now unused.
Signed-off-by: Richard Henderson
Message-id: 20190209033847.9014-6-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/helper.h | 12
target/arm/neon_helper.c | 12
2
From: Richard Henderson
Rather than a complex set of cases testing for writeback,
adjust DP after performing the operation.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20190206052857.5077-2-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
From: Richard Henderson
The components of this register is stored in several
different locations.
Signed-off-by: Richard Henderson
Message-id: 20190209033847.9014-7-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 4 ++--
1 file
From: Richard Henderson
Since we're now handling a == b generically, we no longer need
to do it by hand within target/arm/.
Reviewed-by: David Gibson
Signed-off-by: Richard Henderson
Message-id: 20190209033847.9014-2-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
From: Richard Henderson
For opcodes 0-5, move some if conditions into the structure
of a switch statement. For opcodes 6 & 7, decode everything
at once with a second switch.
Signed-off-by: Richard Henderson
Message-id: 20190206052857.5077-3-richard.hender...@linaro.org
Reviewed-by: Peter
From: Catherine Ho
The lo,hi order is different from the comments. And in commit
1ec182c33379 ("target/arm: Convert to HAVE_CMPXCHG128"), it changes
the original code logic. So just restore the old code logic before this
commit:
do_paired_cmpxchg64_be():
cmpv =
In commit 91c1e9fcbd7548db368 where we added dual-CPU support to
the ARMSSE, we set up the wiring of the expansion IRQs via nested
loops: the outer loop on 'i' loops for each CPU, and the inner loop
on 'j' loops for each interrupt. Fix a typo which meant we were
wiring every expansion IRQ line to
Peter Crosthwaite hasn't had the bandwidth to do code review or
other QEMU work for some time now -- remove his email address
from MAINTAINERS file entries so we don't bombard him with
patch emails.
Signed-off-by: Peter Maydell
Message-id: 20190207181422.4907-1-peter.mayd...@linaro.org
---
tags/pull-target-arm-20190214
for you to fetch changes up to 497bc12b1b374ecd62903bf062229bd93f8924af:
gdbstub: Send a reply to the vKill packet. (2019-02-14 18:45:49 +)
target-arm queue:
* gdbstub: Send a reply
HACR_EL2 is a register with IMPDEF behaviour, which allows
implementation specific trapping to EL2. Implement it as RAZ/WI,
since QEMU's implementation has no extra traps. This also
matches what h/w implementations like Cortex-A53 and A57 do.
Signed-off-by: Peter Maydell
Reviewed-by: Richard
At the moment the Arm implementations of kvm_arch_{get,put}_registers()
don't support having QEMU change the values of system registers
(aka coprocessor registers for AArch32). This is because although
kvm_arch_get_registers() calls write_list_to_cpustate() to
update the CPU state struct fields
On Thu, Feb 14, 2019 at 06:35:47PM +0100, Paolo Bonzini wrote:
> See also "[PATCH for-3.2 00/10] vhost: preparation for qgraph
> conversion of vhost-user-test". Some of the other vhost-user-test
> patches have gone in already, and this is what is left.
>
> These patches are a prerequisite for
From: Aaron Lindsay OS
This bug was introduced in:
commit 5ecdd3e47cadae83a62dc92b472f1fe163b56f59
target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
Signed-off-by: Aaron Lindsay
Reported-by: Laurent Desnogues
Reviewed-by: Laurent Desnogues
Message-id:
From: Alex Bennée
As this is a single register we could expose it with a simple ifdef
but we use the existing modify_arm_cp_regs mechanism for consistency.
Signed-off-by: Alex Bennée
Message-id: 20190205190224.2198-4-alex.ben...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter
On Thu, 14 Feb 2019 at 18:46, Paolo Bonzini wrote:
>
> On 14/02/19 16:24, Peter Maydell wrote:
> > It does check, but I forgot to make the makefiles pay attention
> > to the check.
> >
> > That's very irritating that Fedora is using a weird filename for
> > the tool -- what is their justification
> From: Peter Maydell
> Sent: Thursday, February 14, 2019 7:40 PM
> To: Aleksandar Markovic
> Cc: QEMU Developers; Aleksandar Markovic
> Subject: Re: [PULL v2 07/12] target/mips: Update ITU to utilize SAARI and
> SAAR CP0 registers
>
> On Fri, 18 Jan 2019 at 16:59, Aleksandar Markovic
> wrote:
Hi; Coverity detected an issue in contrib/elf2dmp/main.c (CID 1398641).
In this loop:
for (; KernBase >= 0xf780; KernBase -= PAGE_SIZE) {
nt_start_addr = va_space_resolve(, KernBase);
if (!nt_start_addr) {
continue;
}
if (*(uint16_t
From: "Dr. David Alan Gilbert"
If the migration fails before the channel is open (e.g. a bad
address) we end up in the cleanup with rdma->channel==NULL.
Spotted by Coverity: CID 1398634
Fixes: fbbaacab2758cb3f32a0
Signed-off-by: Dr. David Alan Gilbert
---
migration/rdma.c | 4 +++-
1 file
On Wed, 30 Jan 2019 at 07:41, Gerd Hoffmann wrote:
>
> From: Bandan Das
>
> For every MTP_WRITE_BUF_SZ copied, this patch writes it to file before
> getting the next block of data. The file is kept opened for the
> duration of the operation but the sanity checks on the write operation
> are
On 14/02/19 16:24, Peter Maydell wrote:
> It does check, but I forgot to make the makefiles pay attention
> to the check.
>
> That's very irritating that Fedora is using a weird filename for
> the tool -- what is their justification for doing that?
> I suppose we'll have to make configure cope
On 02/02/19 15:45, Kamil Rytarowski wrote:
>
> Clang/LLVM on NetBSD with enabled optimization cannot link
> correct qemu program because of a missing symbol of
> kvm_arch_get_supported_cpuid() in kvm-stubs.o used by executables.
Can you please include the full error message? Usually these
Ping?
On 02.02.2019 15:45, Kamil Rytarowski wrote:
> This improves the commit:
> "target-i386: Fix build by providing stub kvm_arch_get_supported_cpuid()"
> r. 2140cfa51d59177815f5b82e94ac48fb24909aba
>
> Clang/LLVM on NetBSD with enabled optimization cannot link
> correct qemu program because
On Fri, 18 Jan 2019 at 16:59, Aleksandar Markovic
wrote:
>
> From: Yongbok Kim
>
> Update ITU to utilize SAARI and SAAR CP0 registers.
Hi; Coverity complains (CID 1398648) about this bit of code:
> -static void itc_reconfigure(MIPSITUState *tag)
> +void itc_reconfigure(MIPSITUState *tag)
> {
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Tue, 22 Jan 2019 at 19:08, Dr. David Alan Gilbert (git)
> wrote:
> >
> > From: "Dr. David Alan Gilbert"
> >
> > Unregister the fd handler before we destroy the channel,
> > otherwise we've got a race where we might land in the
> > fd handler
On Thu, 14 Feb 2019 at 10:58, Laurent Vivier wrote:
>
> The following changes since commit 0b5e750bea635b167eb03d86c3d9a09bbd43bc06:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request'
> into staging (2019-02-12 10:53:37 +)
>
> are available in the Git repository
On Thu, 14 Feb 2019 at 14:07, Igor Mammedov wrote:
> Also some boards (ab)use memory_region_allocate_system_memory(), calling it
> several
> times to allocate various fixed sized chunks of RAM and ROMs, which is
> problematic
> to map to a single initial RAM Machine::memdev backend and is
Hi; we've just done another Coverity run, and it's pulled up some
issues in the recently changed Xen code. Rather than track them
back to exactly which patches in the recent refactorings resulted
in them, I figured I'd just list them here. Could you take a
look at them, please ?
(1) CID 1398635:
On 2/14/19 10:48 AM, Peter Maydell wrote:
On Tue, 12 Feb 2019 at 21:52, Sandra Loosemore wrote:
Per the GDB remote protocol documentation
https://sourceware.org/gdb/current/onlinedocs/gdb/Packets.html#index-vKill-packet
the debug stub is expected to send a reply to the 'vKill' packet. At
From: Aleksandar Markovic
Add tests for MSA bit counting instructions. This includes following
instructions:
* NLOC.B - number of leading ones (bytes)
* NLOC.H - number of leading ones (halfwords)
* NLOC.W - number of leading ones (words)
* NLOC.D - number of leading ones (doublewords)
Hi Peter,
On 2/14/19 6:35 PM, Peter Maydell wrote:
> On Tue, 5 Feb 2019 at 17:33, Eric Auger wrote:
>> This series aims to bump the 255GB RAM limit in machvirt and to
>> support device memory in general, and especially PCDIMM/NVDIMM.
>
>> Functionally, the series is split into 3 parts:
>> 1)
From: Leon Alrae
Completely rewrite conditional stores handling. Use cmpxchg.
This eliminates need for separate implementations of SC instruction
emulation for user and system emulation.
Signed-off-by: Leon Alrae
Signed-off-by: Miodrag Dinic
Signed-off-by: Aleksandar Markovic
Acked-by: Alex
Some multiboot images could be in the ELF format. In the current
implementation QEMU fails because we try to load these images
as a PVH image.
In order to fix this issue, we should try multiboot first (we
already check the multiboot magic header before to load it).
If it is not a multiboot image,
From: Miodrag Dinic
While testing mttcg VP0 could get stuck in a loop waiting for other
VPs to come up (which never actually happens). To fix this, kick VPs
while they are being powered up by Cluster Power Controller in an
async task which is triggered once the host thread is being spawned.
On 14/02/19 15:07, Igor Mammedov wrote:
> Also some boards (ab)use memory_region_allocate_system_memory(), calling it
> several
> times to allocate various fixed sized chunks of RAM and ROMs, which is
> problematic
> to map to a single initial RAM Machine::memdev backend and is currently
>
On 14/02/19 13:27, Xiang Zheng wrote:
> There is a small window between the twice blk_is_available in
> scsi_disk_emulate_command which would cause crash due to the later
> assertion if the remote cdrom is detached in this window.
>
> So this patch replaces assertions with return to avoid qemu
On Tue, 12 Feb 2019 at 21:52, Sandra Loosemore wrote:
>
> Per the GDB remote protocol documentation
>
> https://sourceware.org/gdb/current/onlinedocs/gdb/Packets.html#index-vKill-packet
>
> the debug stub is expected to send a reply to the 'vKill' packet. At
> least some versions of GDB crash if
From: Aleksandar Markovic
Add a header that contains test utilities. For now, it contains
only a function for checking and printing test results for bit
counting and similar MSA instructions.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
---
Patchew URL:
https://patchew.org/QEMU/20190214102816.3393-1-peter.mayd...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214102816.3393-1-peter.mayd...@linaro.org
Subject: [Qemu-devel] [PATCH v2 0/7] ui/cocoa: Use
From: Aleksandar Markovic
Add tests for MSA interleave instructions. This includes following
instructions:
* ILVEV.B - interleave even (bytes)
* ILVEV.H - interleave even (halfwords)
* ILVEV.W - interleave even (words)
* ILVEV.D - interleave even (doublewords)
* ILVOD.B - interleave
From: Leon Alrae
Do only virtual addresses comaprisons in LL/SC sequence emulations.
Until this patch, physical addresses had been compared in SC part of
LL/SC sequence, even though such comparisons could be avoided. Getting
rid of them allows throwing away SC helpers and having common SC
On Tue, 22 Jan 2019 at 19:08, Dr. David Alan Gilbert (git)
wrote:
>
> From: "Dr. David Alan Gilbert"
>
> Unregister the fd handler before we destroy the channel,
> otherwise we've got a race where we might land in the
> fd handler just as we're closing the device.
>
> (The race is quite data
From: Aleksandar Markovic
Make sure BQL is held for all interrupt requests.
For MTTCG-enabled configurations, handling soft and hard interrupts
between vCPUs must be properly locked. By acquiring BQL, make sure
all paths triggering an IRQ are synchronized.
Signed-off-by: Miodrag Dinic
From: Aleksandar Markovic
Add tests for MSA logic instructions. This includes following
instructions:
* AND.V - logical AND
* NOR.V - logical NOR
* OR.V - logical OR
* XOR.V - logical XOR
Each test consists of 80 test cases, so altogether there are 320
test cases.
Reviewed-by:
On Mon, 28 Jan 2019 at 18:11, Peter Maydell wrote:
>
> From: Aaron Lindsay OS
>
> A bug was introduced during a respin of:
>
> commit 57a4a11b2b281bb548b419ca81bfafb214e4c77a
> target/arm: Add array for supported PMU events, generate
> PMCEID[01]_EL0
> @@ -1113,13 +1115,16 @@
Patchew URL:
https://patchew.org/QEMU/20190214102816.3393-1-peter.mayd...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v2 0/7] ui/cocoa: Use OSX's main loop
Message-id:
From: Aleksandar Markovic
Add wrappers for MSA interleave instructions.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/include/wrappers_msa.h | 39 +++
1 file changed, 39 insertions(+)
diff --git
hw/net/vhost_net.c needs functions that are declared in net/vhost-user.c: the
vhost-user code is always compiled into QEMU, only the constructor
net_init_vhost_user is unreachable. Also, net/vhost-user.c needs functions
declared in hw/virtio/vhost-stub.c even if no virtio device exists.
Break
From: Aleksandar Markovic
Add wrappers for MSA logic instructions.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
---
tests/tcg/mips/include/wrappers_msa.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/tests/tcg/mips/include/wrappers_msa.h
This shows a preexisting bug: if a KVM target did not have virtio-net enabled,
it would fail with undefined symbols when vhost was enabled. This must now
be fixed, lest targets that have no virtio-net fail to compile.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Paolo Bonzini
From: Aleksandar Markovic
The following changes since commit 7e407466b1efbd65225cc72fe09c0c5ec79df75b:
Merge remote-tracking branch 'remotes/thibault/tags/samuel-thibault' into
staging (2019-02-14 15:22:29 +)
are available in the git repository at:
https://github.com/AMarkovic/qemu
From: Aleksandar Markovic
Add a header that contains wrappers around MSA instructions assembler
invocations. For now, only bit counting instructions (NLOC, NLZC, and
PCNT; each in four data format flavors) are supported.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
---
From: Aleksandar Markovic
The file tests/tcg/mips/include/test_inputs.h is planned to
contain various test inputs. For now, it contains 64 128-bit
pattern inputs (alternating groups od ones and zeroes) and
16 128-bit random inputs.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar
Detect all invalid configurations (e.g. mingw32 with vhost-user,
non-Linux with vhost-kernel). As a collateral benefit, all vhost-kernel
backends can be now disabled if one wants to reduce the attack surface.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Paolo Bonzini
Reviewed-by: Thomas
From: Aleksandar Markovic
Remove a file that was added long time ago by mistake. The commit
that introduced this file was commit d70080c4 (from 2012).
Reviewed-by: Aleksandar Rikalo
Acked-by: Alex Bennée
Reviewed-by: Eric Blake
Signed-off-by: Aleksandar Markovic
---
From: Aleksandar Markovic
Introduce MTTCG-enabled QEMU builds for mips32, mipsn32, and mips64.
Signed-off-by: Miodrag Dinic
Signed-off-by: Aleksandar Markovic
Acked-by: Alex Bennée
Reviewed-by: Alex Bennée
---
configure | 3 +++
target/mips/cpu.h | 2 ++
2 files changed, 5
From: Goran Ferenc
Hold BQL whenever mips_vpe_wake() is invoked.
Without this patch, MIPS MT with MTTCG enabled triggers an abort in
tcg_handle_interrupt() due to an unlocked access to cpu_interrupt().
This patch makes sure that the BQL is held in this case.
Signed-off-by: Goran Ferenc
vhost-user already has a way to communicate the endianness of the guest
via the vring endianness messages. The vring endianness always matches
the vnet header endianness so there is no need to do anything else in
the backend.
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
Hello,
On Thu, 14 Feb 2019, Aleksandar Markovic wrote:
The machine comes with 256M memory module by default but it's
upgradable so it could have different memory size. There was a TODO
comment to replace static SPD EEPROM data with dynamically generated
one to support this. Now that we have a
There is no reason for CONFIG_VHOST_NET to be specific to a single target;
it is a host feature that can be add to all targets, as long as they support
the virtio-net device. Currently CONFIG_VHOST_NET depends on CONFIG_KVM,
but ioeventfd support is present in the core memory API and works with
Patchew URL:
https://patchew.org/QEMU/20190214102816.3393-1-peter.mayd...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214102816.3393-1-peter.mayd...@linaro.org
Subject: [Qemu-devel] [PATCH v2 0/7] ui/cocoa: Use
This makes the tests more independent, and also the source and destination
TestServers in the migration test.
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
Message-Id: <1543851204-41186-15-git-send-email-pbonz...@redhat.com>
---
tests/vhost-user-test.c | 77
On Tue, 5 Feb 2019 at 17:33, Eric Auger wrote:
> This series aims to bump the 255GB RAM limit in machvirt and to
> support device memory in general, and especially PCDIMM/NVDIMM.
> Functionally, the series is split into 3 parts:
> 1) bump of the initial RAM limit [1 - 10] and change in
>the
On Tue, 5 Feb 2019 at 17:33, Eric Auger wrote:
>
> This patch implements the machine class kvm_type() callback.
> It returns the max IPA shift needed to implement the whole GPA
> range including the RAM and IO regions located beyond.
> The returned value in passed though the KVM_CREATE_VM ioctl
This makes the tests more independent and removes the need to defer
test_server_free
via an idle event source.
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
Message-Id: <1543851204-41186-13-git-send-email-pbonz...@redhat.com>
---
tests/vhost-user-test.c | 53
On Thu, 14 Feb 2019 at 04:33, Stefan Hajnoczi wrote:
>
> The following changes since commit 0b5e750bea635b167eb03d86c3d9a09bbd43bc06:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request'
> into staging (2019-02-12 10:53:37 +)
>
> are available in the Git repository
See also "[PATCH for-3.2 00/10] vhost: preparation for qgraph
conversion of vhost-user-test". Some of the other vhost-user-test
patches have gone in already, and this is what is left.
These patches are a prerequisite for both kconfig and qgraph.
I will probably test them on macOS myself before
After the conversion to qgraph, the equivalent of "main" will be in
a constructor and will run even if the tests are not being requested.
Therefore, it should not assert that init_hugepagefs succeeds and will
be called when creating the TestServer. This patch changes the prototype
of
vhost-user does not depend on Linux; it can run on any POSIX system. Restrict
vhost-kernel to Linux in hw/virtio/vhost-backend.c, everything else can be
compiled on all POSIX systems.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-Id:
On Thu, 14 Feb 2019 at 17:04, BALATON Zoltan wrote:
>
> On Thu, 14 Feb 2019, Peter Maydell wrote:
> > Currently the handleEvent method will directly call the NSApp
> > sendEvent method for any events that we want to let OSX deal
> > with. When we rearrange the event handling code, the way that
>
On Thu, 14 Feb 2019, Peter Maydell wrote:
Currently the switchSurface method takes a DisplaySurface. We want
to change our DisplayChangeListener's dpy_gfx_switch callback
to do this work asynchronously on a different thread. The caller
of the switch callback will free the old DisplaySurface
On Thu, 14 Feb 2019, Peter Maydell wrote:
When we switch away from our custom event handling, we still want to
be able to have first go at any events our application receives,
because in full-screen mode we want to send key events to the guest,
even if they would be menu item activation events.
On Thu, 14 Feb 2019, Peter Maydell wrote:
Currently the handleEvent method will directly call the NSApp
sendEvent method for any events that we want to let OSX deal
with. When we rearrange the event handling code, the way that
we say "let OSX have this event" is going to change. Prepare
for that
On 14/02/19 17:54, Michael S. Tsirkin wrote:
> On Thu, Feb 14, 2019 at 05:47:08PM +0100, Paolo Bonzini wrote:
>> On 01/02/19 16:05, Philippe Mathieu-Daudé wrote:
>>> This lacks a DISPLAY dependency?
>>>
>>> $ i386-softmmu/qemu-system-i386 -M q35
>>> qemu-system-i386: Unknown device 'VGA' for bus
The issue with testing asynchronous unplug requests it that they usually
require a running guest to handle the request. However, to test if
unplug of PCI devices works, we can apply a nice little trick on some
architectures:
On system reset, x86 ACPI, s390x and spapr will perform the unplug,
On Tue, 5 Feb 2019 at 17:33, Eric Auger wrote:
>
> On ARM, the kvm_type will be resolved by querying the KVMState.
> Let's add the MachineState handle to the callback so that we
> can retrieve the KVMState handle. in kvm_init, when the callback
> is called, the kvm_state variable is not yet set.
On Tue, 5 Feb 2019 at 17:33, Eric Auger wrote:
>
> In the prospect to introduce an extended memory map supporting more
> RAM, let's split the memory map array into two parts:
>
> - the former a15memmap contains regions below and including the RAM
> - extended_memmap, only initialized with entries
On Wed, Feb 13, 2019 at 20:06:48 -0800, Richard Henderson wrote:
> We've talked about this before, caching state to reduce the
> amount of computation that happens looking up each TB.
>
> I know that Peter has been concerned that we would not be able to
> reliably maintain all of the places that
On Thu, 14 Feb 2019, Peter Maydell wrote:
Factor out the long code sequence in main() which creates
the initial set of menus. This will make later patches
which move initialization code around a bit clearer.
Signed-off-by: Peter Maydell
Reviewed-by: BALATON Zoltan
Regards,
BALATON Zoltan
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