> > It seems to me that the C extension can be enabled at any point, since
> if C is
> > off, you know that the next insn is aligned modulo 4.
> >
>
Ok, This is mostly right. When C extension is enabled 32-bit base
instructions can be aligned on 2 bytes boundaries instead of 4 bytes only.
So mult
On Mon, Feb 25, 2019 at 17:40:01 +, Stefan Hajnoczi wrote:
> On Mon, Feb 25, 2019 at 10:28:46AM +0100, Peter Krempa wrote:
> > On Mon, Feb 25, 2019 at 09:50:26 +0100, Markus Armbruster wrote:
[...]
> > I'm slightly worried of misuse of the possibility to change the behavior
> > on runtime. In
Leverage __ATTR_RO_MODE to define rev sysfs instead of using open code
to define the attribute.
Signed-off-by: Wei Yang
---
drivers/firmware/qemu_fw_cfg.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/firmware/qemu_fw_cfg.c b/drivers/firmware/qemu_fw_c
Stefan Hajnoczi writes:
> On Mon, Feb 25, 2019 at 09:50:26AM +0100, Markus Armbruster wrote:
>> Stefan Hajnoczi writes:
>>
>> > QMP clients can usually detect the presence of features via schema
>> > introspection. There are rare features that do not involve schema
>> > changes and are therefo
Eric Blake writes:
> On 2/8/19 1:30 AM, Markus Armbruster wrote:
>> Short story: please add
>>
>> [am]
>> messageid = true
>>
>> to your .gitconfig.
>>
>> Long story. git-am can add a Message-id: tag. Looks like this:
>>
>
>>
>> Signed-off-by: Thomas Huth
>>
"Kővágó, Zoltán" writes:
> This patch adds structures into qapi to replace the existing
> configuration structures used by audio backends currently. This qapi
> will be the base of the -audiodev command line parameter (that replaces
> the old environment variables based config).
>
> This is not a
These functions are called when return CPUID xsave area
size information.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f6c7bdf
On Mon, Feb 25, 2019 at 09:49:22PM -0500, Programmingkid wrote:
>
> > On Feb 25, 2019, at 10:26 AM, Gerd Hoffmann wrote:
> >
> > On Mon, Feb 25, 2019 at 09:05:30AM -0500, G 3 wrote:
> >> Hi Gerd, I was wondering if you have made any documentation for your EDID
> >> patches. If you have could you
To support features such as live-migration,
CET runtime MSRs need to be saved in source machine and
restored on destination machine, this patch is to save
and restore CET_U, CET_S, PL0_SSP, PL3_SSP and SSP_TABL_ADDR
MSRs.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 12 +
target
Control-flow Enforcement Technology (CET) provides protection against
return/jump-oriented programming (ROP) attacks. To make kvm Guest OS own
the capability, this patch-set is required. It enables CET related CPUID
report, xsaves/xrstors and live-migration etc. in Qemu.
Changelog:
v3:
- Add CE
XSS[bit 11] and XSS[bit 12] correspond to CET
user mode area and supervisor mode area respectively.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 37 +++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/target/i386/c
CPUID bit definition as below:
CPUID.(EAX=d, ECX=1):ECX.CET_U(bit 11): user mode state
CPUID.(EAX=d, ECX=1):ECX.CET_S(bit 12): kernel mode state
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/i386
CET protection in user mode and kernel mode relies on
specific MSRs, these MSRs' contents are automatically
saved/restored by xsaves/xrstors instructions.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 36 +++-
1 file changed, 35 ins
CPUID bit definition as below:
CPUID.(EAX=d, ECX=1):ECX.CET_U(bit 11): user mode state
CPUID.(EAX=d, ECX=1):ECX.CET_S(bit 12): kernel mode state
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/i386
XSS[bit 11] and XSS[bit 12] correspond to CET
user mode area and supervisor mode area respectively.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 37 +++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/target/i386/c
On Tue, 2019-02-26 at 14:39 +1100, David Gibson wrote:
> On Tue, Feb 26, 2019 at 02:05:28PM +1100, Suraj Jitindar Singh wrote:
> > Add spapr_cap SPAPR_CAP_LARGE_DECREMENTER to be used to control the
> > availability and size of the large decrementer made available to
> > the
> > guest.
> >
> > Sig
These functions are called when return CPUID xsave area
size information.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f6c7bdf
To support features such as live-migration,
CET runtime MSRs need to be saved in source machine and
restored on destination machine, this patch is to save
and restore CET_U, CET_S, PL0_SSP, PL3_SSP and SSP_TABL_ADDR
MSRs.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 12 +
target
CET protection in user mode and kernel mode relies on
specific MSRs, these MSRs' contents are automatically
saved/restored by xsaves/xrstors instructions.
Signed-off-by: Zhang Yi
Signed-off-by: Yang Weijiang
---
target/i386/cpu.h | 36 +++-
1 file changed, 35 ins
Subject: [Qemu-devel][PATCH v3 0/5] This patch-set is to enable Guest
CET support.
Control-flow Enforcement Technology (CET) provides protection against
return/jump-oriented programming (ROP) attacks. To make kvm Guest OS own
the capability, this patch-set is required. It enables CET related CPUID
Eric Blake writes:
> I missed reviewing this before the pull request, so comments here are
> best for a followup patch:
I procrastinated, same result. My apologies.
Followup or quick respin is up to you. I'd respin as long as the
changes are trivial.
> On 2/25/19 6:31 AM, Daniel P. Berrangé
From: Zhang Chen
Fix three bugs after COLO failover.
Zhang Chen (3):
Migration/colo.c: Fix double close bug when occur COLO failover
Migration/colo.c: Fix COLO failover status error
Migration/colo.c: Make COLO node running after failover
migration/colo.c | 9 +
migration/mi
From: Zhang Chen
In migration_incoming_state_destroy(void) will check the mis->to_src_file
to double close the mis->to_src_file when occur COLO failover.
Signed-off-by: Zhang Chen
---
migration/colo.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/migration/colo.c b/migration/colo.c
index
From: Zhang Chen
When finished COLO failover, the status is FAILOVER_STATUS_COMPLETED.
The origin codes misunderstand the FAILOVER_STATUS_REQUIRE.
Signed-off-by: Zhang Chen
---
migration/colo.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/migration/colo.c b/migrat
From: Thomas Huth
Both functions, object_initialize() and object_property_add_child() increase
the reference counter of the new object, so one of the references has to be
dropped afterwards to get the reference counting right. Otherwise the child
object will not be properly cleaned up when the pa
From: Zhang Chen
Delay to close COLO for auto start VM after failover.
Signed-off-by: Zhang Chen
---
migration/colo.c | 1 -
migration/migration.c | 3 +++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/migration/colo.c b/migration/colo.c
index a13acac192..89325952c7 100644
From: Michael Roth
PHB hotplug re-uses PHB device tree generation code and passes
it to a guest via RTAS. Doing this requires knowledge of where
exactly in the device tree the node describing the PHB begins.
Provide this via a new optional pointer that can be used to
store the PHB node's start o
From: Greg Kurz
We can easily test this, just like PCI. PHB unplug is not supported
on s390x and x86 ACPI.
Signed-off-by: Greg Kurz
Message-Id:
<155059673939.1466090.14354001937819612724.st...@bahia.lab.toulouse-stg.fr.ibm.com>
Signed-off-by: David Gibson
---
tests/device-plug-test.c | 16 ++
From: Greg Kurz
The pseries machine only uses LSIs to support legacy PCI devices. Every
PHB claims 4 LSIs at realize time. When using in-kernel XICS (or upcoming
in-kernel XIVE), QEMU synchronizes the state of all irqs, including these
LSIs, later on at machine reset.
In order to support PHB hot
From: Murilo Opsfelder Araujo
The current 0x1000 value is actually 256MiB, not 128MB as the comment
suggests. Move it to a constant and fix the comment (no change in the size
value).
Signed-off-by: Murilo Opsfelder Araujo
Message-Id: <20190225170155.1972-3-muri...@linux.ibm.com>
Reviewed-by
From: Cédric Le Goater
Patch "target/ppc: Add POWER9 external interrupt model" should have
removed the section covering PPC_FLAGS_INPUT_POWER7.
Signed-off-by: Cédric Le Goater
Message-Id: <20190219142530.17807-1-...@kaod.org>
Signed-off-by: David Gibson
---
hw/intc/xive.c | 3 ---
1 file chan
From: Greg Kurz
Hotplugging PHBs is a machine-level operation, but PHBs reside on the
main system bus, so we register spapr machine as the handler for the
main system bus.
Provide the usual pre-plug, plug and unplug-request handlers.
Move the checking of the PHB index to the pre-plug handler. I
From: Murilo Opsfelder Araujo
Using IEC binary prefixes from qemu/units.h provides a more human-friendly value
to size constants.
Suggested-by: Eric Blake
Signed-off-by: Murilo Opsfelder Araujo
Message-Id: <20190225170155.1972-4-muri...@linux.ibm.com>
Reviewed-by: Cédric Le Goater
Signed-off-
From: Greg Kurz
This will be needed by PHB hotplug in order to access the "phandle"
property of the interrupt controller node.
Reviewed-by: Cédric Le Goater
Signed-off-by: Greg Kurz
Reviewed-by: David Gibson
Message-Id:
<155059668867.1466090.6339199751719123386.st...@bahia.lab.toulouse-stg.f
From: Murilo Opsfelder Araujo
Building kernel with CONFIG_DEBUG_INFO_REDUCED can generate a ~90MB image and
building with CONFIG_DEBUG_INFO can generate a ~225M one, both exceeds the
current limit of 32MiB.
Increasing kernel size limit to 256MiB should fit for now.
Signed-off-by: Murilo Opsfeld
From: Michael Roth
Signed-off-by: Michael Roth
Reviewed-by: David Gibson
Signed-off-by: Greg Kurz
Message-Id:
<155059670389.1466090.10015601248906623076.st...@bahia.lab.toulouse-stg.fr.ibm.com>
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 13 +
hw/ppc/spapr_drc.c
From: Greg Kurz
Signed-off-by: Greg Kurz
Message-Id:
<155059666331.1466090.676654076629713.st...@bahia.lab.toulouse-stg.fr.ibm.com>
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 33 ++---
hw/ppc/spapr_drc.c | 1 +
include/hw/ppc/spapr.h | 4 +++
From: Michael Roth
The 'dr_phb_enabled' field of that class can be set as part of
machine-specific init code. It will be used to conditionally
enable creation of DRC objects and device-tree description to
facilitate hotplug of PHBs.
Since we can't migrate this state to older machine types,
defau
From: Benjamin Herrenschmidt
(Might need more patch splitting)
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Cédric Le Goater
Message-Id: <20190215170029.15641-12-...@kaod.org>
[dwg: Hack to fix compile with some earlier include tweaks of mine]
Signed-off-by: David Gibson
---
target/p
From: Greg Kurz
The current logic is to provide the FDT fragment when attaching a device
to a DRC. This works perfectly fine for our current hotplug support, but
soon we will add support for PHB hotplug which has some constraints, that
CPU, PCI and LMB devices don't seem to have.
The first const
From: Michael Roth
Extend the existing EPOW event format we use for PCI
devices to emit PHB plug/unplug events.
Signed-off-by: Michael Roth
Reviewed-by: David Gibson
Signed-off-by: Greg Kurz
Message-Id:
<155059671405.1466090.535964535260503283.st...@bahia.lab.toulouse-stg.fr.ibm.com>
Signed-
From: Nathan Fontenot
This add entries to the root OF node to advertise our PHBs as being
DR-capable in accordance with PAPR specification.
Signed-off-by: Nathan Fontenot
Signed-off-by: Michael Roth
Reviewed-by: David Gibson
Signed-off-by: Greg Kurz
Message-Id:
<155059670897.1466090.1084392
From: Benjamin Herrenschmidt
The HW relies on LPCR:HR along with the PATE to determine whether
to use Radix or Hash mode. In fact it uses LPCR:HR more commonly
than the PATE.
For us, it's also more efficient to do so, especially since unlike
the HW we do not maintain a cache of the current PATE
From: Greg Kurz
To support PHB hotplug we need to clean up lingering references,
memory, child properties, etc. prior to the PHB object being
finalized. Generally this will be called as a result of calling
object_unparent() on the PHB object, which in turn would normally
be called as the result o
From: Benjamin Herrenschmidt
Historically the 64-bit server MMU supports two way of configuring the
guest "real mode" mapping:
- The "RMA" with is a single chunk of physically contiguous
memory remapped as guest real, and controlled by the RMLS
field in the LPCR register and the RMOR register.
From: Benjamin Herrenschmidt
With mttcg, we can have MMU lookups happening at the same time
as the guest modifying the page tables.
Since the HPTEs of the hash table MMU contains two words (or
double worlds on 64-bit), we need to make sure we read them
in the right order, with the correct memory
From: Greg Kurz
Signed-off-by: Greg Kurz
Message-Id:
<155059667346.1466090.326696113231137772.st...@bahia.lab.toulouse-stg.fr.ibm.com>
Signed-off-by: David Gibson
---
hw/ppc/spapr_drc.c | 1 +
hw/ppc/spapr_pci.c | 19 ---
include/hw/pci-host/spapr.h | 4 +++
From: David Hildenbrand
As CCW unplugs are surprise removals without asking the guest first,
we can test this without any guest interaction.
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Thomas Huth
Signed-off-by: David Hildenbrand
Message-Id: <20190218092202.26683-5-da...@redhat.com>
Acked-by
From: Benjamin Herrenschmidt
That "b" means "base address" and thus shouldn't be in the name
of actual entries and related constants.
This patch keeps the synthetic patb_entry field of the spapr
virtual hypervisor unchanged until I figure out if that has
an impact on the migration stream.
Signe
From: Michael Roth
This is needed to denote a boot-time PHB as being hot-pluggable.
Signed-off-by: Michael Roth
Reviewed-by: David Gibson
Signed-off-by: Greg Kurz
Message-Id:
<155059672420.1466090.15147504040270659866.st...@bahia.lab.toulouse-stg.fr.ibm.com>
Signed-off-by: David Gibson
---
From: Greg Kurz
All DRC subtypes have been converted to generate the FDT fragment at
configure connector time instead of attach time. The fdt and fdt_offset
arguments of spapr_drc_attach() aren't needed anymore. Drop them and
make the implementation of the dt_populate() method mandatory.
Signed-
From: Benjamin Herrenschmidt
Adds support for the Hypervisor directed interrupts in addition to the
OS ones.
Signed-off-by: Benjamin Herrenschmidt
[clg: - modified the icp_realize() and xive_tctx_realize() to take
into account explicitely the POWER9 interrupt model
- introduced a
From: Benjamin Herrenschmidt
Our TCG TLB only tags whether it's a HV vs a guest access, so it must
be flushed when the LPIDR is changed.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Cédric Le Goater
Message-Id: <20190215170029.15641-10-...@kaod.org>
Signed-off-by: David Gibson
---
ta
From: Greg Kurz
This will be used by PHB hotplug in order to create the "interrupt-map"
property of the PHB node.
Signed-off-by: Greg Kurz
Message-Id:
<155059669374.1466090.12943228478046223856.st...@bahia.lab.toulouse-stg.fr.ibm.com>
Signed-off-by: David Gibson
---
hw/ppc/spapr_irq.c
From: Benjamin Herrenschmidt
And use it to get the correct HILE bit in HID0
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Message-Id: <20190215161648.9600-7-...@kaod.org>
Signed-off-by: David Gibson
---
target/ppc/cpu-qom.h| 2 +
From: Greg Kurz
Signed-off-by: Greg Kurz
Message-Id:
<155059666839.1466090.3833376527523126752.st...@bahia.lab.toulouse-stg.fr.ibm.com>
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 52 +++---
hw/ppc/spapr_drc.c | 1 +
include/hw/ppc/spapr.h
From: Benjamin Herrenschmidt
Let's use the generic helper tlb_flush_all_cpus_synced() instead
of iterating the CPUs ourselves.
We do lose the optimization of clearing the "other" CPUs "need flush"
flags but this shouldn't be a problem in practice.
Signed-off-by: Benjamin Herrenschmidt
Signed-o
From: Benjamin Herrenschmidt
No guest support yet
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Cédric Le Goater
Message-Id: <20190215170029.15641-13-...@kaod.org>
Signed-off-by: David Gibson
---
target/ppc/mmu-radix64.c | 81 ++--
1 file changed, 6
From: Benjamin Herrenschmidt
Now that LPCR:HR is set properly for SPAPR, use it for deciding
the translation type, which also works for bare metal
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Cédric Le Goater
Message-Id: <20190215170029.15641-3-...@kaod.org>
Signed-off-by: David Gibson
From: Benjamin Herrenschmidt
POWER9 (arch v3) slightly changes the HPTE format. The B bits move
from the first to the second half of the HPTE, and the AVPN/ARPN
are slightly shorter.
However, under SPAPR, the hypercalls still take the old format
(and probably will for the foreseable future).
Th
From: David Hildenbrand
We can easily test this, just like PCI. On x86 ACPI, we need guest
interaction to make it work, so it is not that easy to test. We might
add tests for that later on.
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Greg Kurz
Reviewed-by: Thomas Huth
Signed-off-by: David Hi
From: Benjamin Herrenschmidt
This adds support for delivering that exception
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Message-Id: <20190215161648.9600-9-...@kaod.org>
Signed-off-by: David Gibson
---
target/ppc/cpu.h| 5
From: David Hildenbrand
We can easily test this, just like PCI. On s390x, cpu unplug is not
supported. On x86 ACPI, cpu unplug requires guest interaction to work, so
it can't be tested that easily. We might add tests for ACPI later.
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Greg Kurz
Review
From: Benjamin Herrenschmidt
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Cédric Le Goater
Message-Id: <20190215170029.15641-5-...@kaod.org>
Signed-off-by: David Gibson
---
target/ppc/mmu-book3s-v3.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/ppc/
From: David Hildenbrand
The issue with testing asynchronous unplug requests it that they usually
require a running guest to handle the request. However, to test if
unplug of PCI devices works, we can apply a nice little trick on some
architectures:
On system reset, x86 ACPI, s390x and spapr will
From: Benjamin Herrenschmidt
To better reflect what this does, as it's specific to some of the
P7/P8/P9 PM states, not generic.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Message-Id: <20190215161648.9600-6-...@kaod.org>
Signed-off-by: David
From: David Hildenbrand
This enables CPU unplug under qtest.
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Greg Kurz
Reviewed-by: Thomas Huth
Reviewed-by: David Gibson
Signed-off-by: David Hildenbrand
Message-Id: <20190218092202.26683-2-da...@redhat.com>
Signed-off-by: David Gibson
---
cpu
From: Prasad J Pandit
On ppc hosts, hypervisor shares following system attributes
- /proc/device-tree/system-id
- /proc/device-tree/model
with a guest. This could lead to information leakage and misuse.[*]
Add machine attributes to control such system information exposure
to a guest.
[*] h
From: David Hildenbrand
Fake availability of OV5_HP_EVT, so we can test memory unplug in qtest.
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Greg Kurz
Acked-by: David Gibson
Signed-off-by: David Hildenbrand
Message-Id: <20190218092202.26683-3-da...@redhat.com>
Signed-off-by: David Gibson
--
From: Benjamin Herrenschmidt
It's very easy for the CPU specific has_work() implementation
and the logic in ppc_hw_interrupt() to be subtly out of sync.
This can occasionally allow a CPU to wakeup from a PM state
and resume executing past the PM instruction when it should
resume at the 0x100 vec
From: Benjamin Herrenschmidt
This controls whether the External Interrupt (0x500) can be
delivered to the hypervisor or not.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Message-Id: <20190215161648.9600-11-...@kaod.org>
Signed-off-by: David G
From: Benjamin Herrenschmidt
This moves the code to handle waking up from the 0x100 vector
from powerpc_excp() to a separate function, as the former is
already way too big as it is.
No functional change.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Cédric Le Goater
Reviewed-by: David
From: Benjamin Herrenschmidt
Those instructions currently raise an exception from within
the helper. This tends to result in a bogus nip value in
the env context (typically the beginning of the TB). Such
a helper needs a gen_update_nip() first.
This fixes it with a different approach which is to
From: Benjamin Herrenschmidt
When issuing a power management instruction, we set MSR:EE
to force ppc_hw_interrupt() into calling powerpc_excp()
to deal with the fact that on P7 and P8, the system reset
caused by the wakeup needs to be generated regardless of
the MSR:EE value (using LPCR only).
T
The following changes since commit ef80b99ce7ffbd66b3efd493f4ca99f8abf59e79:
Merge remote-tracking branch
'remotes/stsquad/tags/pull-testing-next-220219-1' into staging (2019-02-25
14:04:20 +)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-4.0-20
From: Benjamin Herrenschmidt
STOP must act differently based on PSSCR:EC on POWER9. When set, it
acts like the P7/P8 power management instructions and wake up at 0x100
based on the wakeup conditions in LPCR.
When PSSCR:EC is clear however it will wakeup at the next instruction
after STOP (if EE
On Fri, Feb 22, 2019 at 02:13:22PM +0100, Cédric Le Goater wrote:
> Instead of switching off the sources, set their state to PENDING to
> possibly catch a hotplug event occuring while the VM is stopped. At
> resume, check the previous state and if an interrupt was queued,
> generate a trigger.
Fir
On Tue, Feb 26, 2019 at 02:05:30PM +1100, Suraj Jitindar Singh wrote:
> Implement support to allow KVM guests to take advantage of the large
> decrementer introduced on POWER9 cpus.
>
> To determine if the host can support the requested large decrementer
> size, we check it matches that specified
On Mon, Feb 25, 2019 at 08:20:09PM -0300, Murilo Opsfelder Araujo wrote:
> Hi, Maxiwell.
>
> On Mon, Feb 25, 2019 at 01:23:25PM -0300, Maxiwell S. Garcia wrote:
> > This adds a handler for ibm,get-vpd RTAS calls, allowing pseries
> > guest to collect host information. It is disabled by default to
On Tue, Feb 26, 2019 at 02:05:29PM +1100, Suraj Jitindar Singh wrote:
> Prior to POWER9 the decrementer was a 32-bit register which decremented
> with each tick of the timebase. From POWER9 onwards the decrementer can
> be set to operate in a mode called large decrementer where it acts as a
> n-bit
On Tue, Feb 26, 2019 at 02:05:31PM +1100, Suraj Jitindar Singh wrote:
> Enable the large decrementer by default on POWER9 cpu models. The
> default value applied is that provided in the cpu class.
>
> Signed-off-by: Suraj Jitindar Singh
> ---
> hw/ppc/spapr_caps.c | 7 +++
> 1 file changed,
On Tue, Feb 26, 2019 at 02:05:28PM +1100, Suraj Jitindar Singh wrote:
> Add spapr_cap SPAPR_CAP_LARGE_DECREMENTER to be used to control the
> availability and size of the large decrementer made available to the
> guest.
>
> Signed-off-by: Suraj Jitindar Singh
> ---
> hw/ppc/spapr.c | 2
On Mon, Feb 25, 2019 at 09:15:34AM +0800, Wei Yang wrote:
>On Mon, Feb 25, 2019 at 09:07:08AM +0800, Wei Yang wrote:
>>Currently we do device realization like below:
>>
>> hotplug_handler_pre_plug()
>> dc->realize()
>> hotplug_handler_plug()
>>
>>Before we do device realization and plug, we s
I would work around this issue
by applying "export QEMU_AUDIO_DRV=none" to shell before we run the qemu
command.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1816052
Title:
qemu system emulator f
On Fri, Feb 22, 2019 at 02:13:15PM +0100, Cédric Le Goater wrote:
> When the VM is stopped, the VM state handler stabilizes the XIVE IC
> and marks the EQ pages dirty. These are then transferred to destination
> before the transfer of the device vmstates starts.
>
> The sPAPRXive interrupt control
On Fri, Feb 22, 2019 at 02:13:13PM +0100, Cédric Le Goater wrote:
> This extends the KVM XIVE device backend with 'synchronize_state'
> methods used to retrieve the state from KVM. The HW state of the
> sources, the KVM device and the thread interrupt contexts are
> collected for the monitor usage
On Fri, Feb 22, 2019 at 02:13:14PM +0100, Cédric Le Goater wrote:
> This handler is in charge of stabilizing the flow of event notifications
> in the XIVE controller before migrating a guest. This is a requirement
> before transferring the guest EQ pages to a destination.
>
> When the VM is stoppe
On Fri, Feb 22, 2019 at 02:13:19PM +0100, Cédric Le Goater wrote:
> If a new interrupt mode is chosen by CAS, the machine generates a
> reset to reconfigure. At this point, the connection with the previous
> KVM device needs to be closed and a new connection needs to opened
> with the KVM device op
On Fri, Feb 22, 2019 at 02:13:16PM +0100, Cédric Le Goater wrote:
> When the thread interrupt management state is retrieved from the KVM
> VCPU, word2 is saved under the QEMU XIVE thread context to print out
> the OS CAM line under the QEMU monitor.
>
> This breaks the migration of a TCG guest (an
On Fri, Feb 22, 2019 at 02:13:11PM +0100, Cédric Le Goater wrote:
> XIVE hcalls are all redirected to QEMU as none are on a fast path.
> When necessary, QEMU invokes KVM through specific ioctls to perform
> host operations. QEMU should have done the necessary checks before
> calling KVM and, in cas
On Fri, Feb 22, 2019 at 02:13:20PM +0100, Cédric Le Goater wrote:
> The activation of the KVM IRQ device depends on the interrupt mode
> chosen at CAS time by the machine and some methods used at reset or by
> the migration need to be protected.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: D
On Tue, Feb 26, 2019 at 10:49:27AM +1100, David Gibson wrote:
> On Fri, Feb 22, 2019 at 02:13:12PM +0100, Cédric Le Goater wrote:
> > All is in place for KVM now. State synchronization and migration will
> > come next.
>
> As with the kernel side capability, this should be moved later in the
> ser
On Mon, Feb 25, 2019 at 01:23:25PM -0300, Maxiwell S. Garcia wrote:
> This adds a handler for ibm,get-vpd RTAS calls, allowing pseries
> guest to collect host information. It is disabled by default to
> avoid unwanted information leakage. To enable it, use:
> ‘-M pseries,vpd-export=on’
>
> Only th
On Fri, Feb 22, 2019 at 02:13:12PM +0100, Cédric Le Goater wrote:
> All is in place for KVM now. State synchronization and migration will
> come next.
As with the kernel side capability, this should be moved later in the
series to avoid breaking bisections.
>
> Signed-off-by: Cédric Le Goater
>
Prior to POWER9 the decrementer was a 32-bit register which decremented
with each tick of the timebase. From POWER9 onwards the decrementer can
be set to operate in a mode called large decrementer where it acts as a
n-bit decrementing register which is visible as a 64-bit register, that
is the valu
Implement support to allow KVM guests to take advantage of the large
decrementer introduced on POWER9 cpus.
To determine if the host can support the requested large decrementer
size, we check it matches that specified in the ibm,dec-bits device-tree
property. We also need to enable it in KVM by se
Add spapr_cap SPAPR_CAP_LARGE_DECREMENTER to be used to control the
availability and size of the large decrementer made available to the
guest.
Signed-off-by: Suraj Jitindar Singh
---
hw/ppc/spapr.c | 2 ++
hw/ppc/spapr_caps.c| 45 +
inclu
Enable the large decrementer by default on POWER9 cpu models. The
default value applied is that provided in the cpu class.
Signed-off-by: Suraj Jitindar Singh
---
hw/ppc/spapr_caps.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index e07568
> On Feb 25, 2019, at 10:26 AM, Gerd Hoffmann wrote:
>
> On Mon, Feb 25, 2019 at 09:05:30AM -0500, G 3 wrote:
>> Hi Gerd, I was wondering if you have made any documentation for your EDID
>> patches. If you have could you provide a link please?
>
> No docs.
>
>> Also could a feature be added t
On Mon, Feb 25, 2019 at 10:36 PM Eduardo Habkost
wrote:
> On Fri, Feb 22, 2019 at 02:26:13PM +0300, Andrey Shinkevich wrote:
> > The data type for bytes in Python3 differs from the one in Python2.
> > Those cases should be managed separately.
> >
> > v1:
> > In the first version, the TypeError in
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