> @cpaelzer, if you have any suggestions for specific tests/configurations
> that might be good to test the specific code changed here, please let me
> know.
I have ran the few test that would cover that area in the past on PPAs already.
Unfortunately this is a very specific path and I don't have
On 5/8/19 2:06 AM, Richard Henderson wrote:
> Fix all of the coding style errors in this file at once.
>
> Signed-off-by: Richard Henderson
> ---
> target/cris/op_helper.c | 817 +++-
> 1 file changed, 398 insertions(+), 419 deletions(-)
Reviewed using 'git d
From: Liu Jingqi
This structure describes the memory access latency and bandwidth
information from various memory access initiator proximity domains.
The latency and bandwidth numbers represented in this structure
correspond to rated latency and bandwidth for the platform.
The software could use
From: Liu Jingqi
Add -numa hmat-cache option to provide Memory Side Cache Information.
These memory attributes help to build Memory Side Cache Information
Structure(s) in ACPI Heterogeneous Memory Attribute Table (HMAT).
Signed-off-by: Liu Jingqi
Signed-off-by: Tao Xu
---
Changes in v4 -> v3:
From: Liu Jingqi
Add -numa hmat-lb option to provide System Locality Latency and
Bandwidth Information. These memory attributes help to build
System Locality Latency and Bandwidth Information Structure(s)
in ACPI Heterogeneous Memory Attribute Table (HMAT).
Signed-off-by: Liu Jingqi
Signed-off-
This series of patches will build Heterogeneous Memory Attribute Table (HMAT)
according to the command line. The ACPI HMAT describes the memory attributes,
such as memory side cache attributes and bandwidth and latency details,
related to the System Physical Address (SPA) Memory Ranges.
The softwar
From: Liu Jingqi
HMAT is defined in ACPI 6.2: 5.2.27 Heterogeneous Memory Attribute Table (HMAT).
The specification references below link:
http://www.uefi.org/sites/default/files/resources/ACPI_6_2.pdf
It describes the memory attributes, such as memory side cache
attributes and bandwidth and lat
The aim of this patch is to move some of the NFIT Aml-build codes into
build_acpi_aml_common(), and then NFIT and HMAT can both use it.
Reviewed-by: Liu Jingqi
Signed-off-by: Tao Xu
---
Changes in v4 -> v3:
- Split 8/8 of patch v3 into two parts, introduces NFIT
generalizations (build_a
On 5/8/19 2:06 AM, Richard Henderson wrote:
> Fix all of the coding style errors in this file at once.
>
> Signed-off-by: Richard Henderson
> ---
> target/cris/mmu.c | 479 +++---
> 1 file changed, 237 insertions(+), 242 deletions(-)
>
> diff --git a/targ
Currently we are doing log_clear() right after log_sync() which mostly
keeps the old behavior when log_clear() was still part of log_sync().
This patch tries to further optimize the migration log_clear() code
path to split huge log_clear()s into smaller chunks.
We do this by spliting the whole gu
Add build_mem_ranges callback to AcpiDeviceIfClass and use
it for generating SRAT and HMAT numa memory ranges.
Suggested-by: Igor Mammedov
Co-developed-by: Liu Jingqi
Signed-off-by: Liu Jingqi
Signed-off-by: Tao Xu
---
Changes in v4 -> v3:
- spilt the 1/8 of v3 patch into two patches, 4/1
From: Liu Jingqi
This structure describes memory side cache information for memory
proximity domains if the memory side cache is present and the
physical device(SMBIOS handle) forms the memory side cache.
The software could use this information to effectively place
the data in memory to maximize
Firstly detect the interface using KVM_CAP_MANUAL_DIRTY_LOG_PROTECT
and mark it. When failed to enable the new feature we'll fall back to
the old sync.
Provide the log_clear() hook for the memory listeners for both address
spaces of KVM (normal system memory, and SMM) and deliever the clear
messa
Introduce KVMMemoryListener.slots_lock to protect the slots inside the
kvm memory listener. Currently it is close to useless because all the
KVM code path now is always protected by the BQL. But it'll start to
make sense in follow up patches where we might do remote dirty bitmap
clear and also we
The aim of this patch is to move existing numa global numa_info
(renamed as "nodes") into NumaState.
Reviewed-by: Liu Jingqi
Suggested-by: Igor Mammedov
Suggested-by: Eduardo Habkost
Signed-off-by: Tao Xu
---
Changes in v4 -> v3:
- send the patch together with HMAT patches
Changes in v3
From: Liu Jingqi
OSPM evaluates HMAT only during system initialization.
Any changes to the HMAT state at runtime or information
regarding HMAT for hot plug are communicated using _HMA method.
_HMA is an optional object that enables the platform to provide
the OS with updated Heterogeneous Memory
Introduce a new memory region listener hook log_clear() to allow the
listeners to hook onto the points where the dirty bitmap is cleared by
the bitmap users.
Previously log_sync() contains two operations:
- dirty bitmap collection, and,
- dirty bitmap clear on remote site.
Let's take KVM as
When synchronizing dirty bitmap from kernel KVM we do it in a
per-kvmslot fashion and we allocate the userspace bitmap for each of
the ioctl. This patch instead make the bitmap cache be persistent
then we don't need to g_malloc0() every time.
More importantly, the cached per-kvmslot dirty bitmap
The aim of this patch is to add struct NumaState in MachineState
and move existing numa global nb_numa_nodes(renamed as "num_nodes")
into NumaState. And add variable numa_support into MachineClass to
decide which submachines support NUMA.
Reviewed-by: Liu Jingqi
Suggested-by: Igor Mammedov
Sugge
cpu_physical_memory_sync_dirty_bitmap() has one RAMBlock* as
parameter, which means that it must be with RCU read lock held
already. Taking it again inside seems redundant. Removing it.
Instead comment on the functions about the RCU read lock.
Signed-off-by: Peter Xu
---
include/exec/ram_addr.
The aim of this patch is to move existing numa global have_numa_distance
into NumaState.
Reviewed-by: Liu Jingqi
Suggested-by: Igor Mammedov
Suggested-by: Eduardo Habkost
Signed-off-by: Tao Xu
---
Changes in v4 -> v3:
- send the patch together with HMAT patches
---
hw/arm/virt-acpi-build
Also we change the 2nd parameter of it to be the relative offset
within the memory region. This is to be used in follow up patches.
Signed-off-by: Peter Xu
---
exec.c | 3 ++-
include/exec/ram_addr.h | 2 +-
memory.c| 3 +--
3 files changed, 4 insertions(+), 4 de
Summary
=
Based-on: <20190426062705.4651-1-pet...@redhat.com>
(It's "[PATCH] checkpatch: allow SPDX-License-Identifier", not a big
deal, just to make sure no spoil message since one patch used SPDX
license identifier and checkpatch doesn't like it...)
This series allows QEM
Similar to 9460dee4b2 ("memory: do not touch code dirty bitmap unless
TCG is enabled", 2015-06-05) but for the migration bitmap - we can
skip the MIGRATION bitmap update if migration not enabled.
Signed-off-by: Peter Xu
---
include/exec/memory.h | 2 ++
include/exec/ram_addr.h | 12 ++
It's never used anywhere.
Signed-off-by: Peter Xu
---
include/exec/memory.h | 17 -
memory.c | 8
2 files changed, 25 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 9144a47f57..e6140e8a04 100644
--- a/include/exec/memory.h
++
On 5/2/19 4:51 PM, Igor Mammedov wrote:
> In case of UEFI, RSDP doesn't have to be located in lowmem,
> it could be placed at any address. Make sure that test won't
> break if it is placed above the first 4Gb of address space.
>
> PS:
> While at it cleanup some local variables as we don't really
>
It's obviously obsolete. Do some update.
Signed-off-by: Peter Xu
---
accel/kvm/kvm-all.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index 524c4ddfbd..b686531586 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-a
These helpers copy the source bitmap to destination bitmap with a
shift either on the src or dst bitmap.
Meanwhile, we never have bitmap tests but we should.
This patch also introduces the initial test cases for utils/bitmap.c
but it only tests the newly introduced functions.
Signed-off-by: Pete
On 5/2/19 4:51 PM, Igor Mammedov wrote:
> boot_sector_init() won't be used by arm/virt board, so move it from
> global scope to x86 branch that uses it.
>
> Signed-off-by: Igor Mammedov
> Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
> ---
> v3:
> - fix checkpatch er
On 5/2/19 4:51 PM, Igor Mammedov wrote:
> once FW provides a pointer to SMBIOS entry point like it does for
> RSDP it should be possible to enable this one the same way.
>
> Signed-off-by: Igor Mammedov
> Reviewed-by: Laszlo Ersek
Tested-by: Philippe Mathieu-Daudé
> ---
> v3:
> - add ref to
On 4/3/19 5:43 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> target/alpha/cpu.h| 5 ++--
> target/alpha/cpu.c| 5 ++--
> target/alpha/helper.c | 50 +++
> target/alpha/mem_helper.c | 16 -
> 4 files ch
On 4/3/19 5:43 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> target/hppa/cpu.h| 8
> target/hppa/cpu.c| 5 ++---
> target/hppa/mem_helper.c | 22 +-
> 3 files changed, 23 insertions(+), 12 deletions(-)
>
> diff --git a/targ
On 4/3/19 5:43 AM, Richard Henderson wrote:
> This hook is now completely replaced by tlb_fill.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
> ---
> include/qom/cpu.h | 3 ---
> accel/tcg/user-exec.c | 13 +++--
> 2 files changed, 3 insertions(+), 13 d
On 4/29/19 7:28 PM, Peter Maydell wrote:
> On Wed, 3 Apr 2019 at 05:05, Richard Henderson
> wrote:
>>
>> We can now use the CPUClass hook instead of a named function.
>>
>> Create a static tlb_fill function to avoid other changes within
>> cputlb.c. This also which also isolates the asserts impli
>
> On Tue, May 07, 2019 at 08:37:01AM -0700, Dan Williams wrote:
> > On Thu, Apr 25, 2019 at 10:03 PM Pankaj Gupta wrote:
> > >
> > > Dont support 'MAP_SYNC' with non-DAX files and DAX files
> > > with asynchronous dax_device. Virtio pmem provides
> > > asynchronous host page cache flush mecha
On 4/3/19 5:43 AM, Richard Henderson wrote:
> Note that env->active_tc.PC is removed from the qemu_log as that value
> is garbage. The PC isn't recovered until cpu_restore_state, called from
> cpu_loop_exit_restore, called from do_raise_exception_err.
>
> Cc: Aleksandar Markovic
> Cc: Aleksandar
On 4/29/19 7:25 PM, Peter Maydell wrote:
> On Wed, 3 Apr 2019 at 04:49, Richard Henderson
> wrote:
>>
>> This hook will replace the (user-only mode specific) handle_mmu_fault
>> hook, and the (system mode specific) tlb_fill function.
>>
>> The handle_mmu_fault hook was written as if there was a va
Cc: Marcel in the hope of getting a pong.
Thomas Huth writes:
> On 29/03/2019 09.42, Thomas Huth wrote:
>> On 06/02/2019 17.43, Thomas Huth wrote:
>>> The license information in this file is rather confusing. The text
>>> declares LGPL first, but then says that contributions after Jan 2012
>>> a
On 5/7/19 7:01 PM, Peter Maydell wrote:
> On Tue, 7 May 2019 at 15:19, Daniel P. Berrangé wrote:
>> On Tue, May 07, 2019 at 09:11:09AM -0500, Eric Blake wrote:
>>> In the meantime, where do we stand on our goal of disabling in-tree builds?
>>
>> The view was largely positive when we discussed it.
Markus Armbruster writes:
> Eduardo Habkost writes:
>
>> Instead of requiring every architecture to implement a
>> class_by_name function, let them set a format string at
>> CPUClass::class_name_format.
>>
>> This will let us get rid of at least 16 class_by_name functions
>> in the next commits.
On Tue, May 07, 2019 at 12:04:08PM +0200, Igor Mammedov wrote:
>On Sun, 5 May 2019 09:27:45 +0800
>Wei Yang wrote:
>
>> On Thu, May 02, 2019 at 04:51:53PM +0200, Igor Mammedov wrote:
>> >that way it would be possible to test a DSDT pointed by
>> >64bit X_DSDT field in FADT.
>> >
>> >PS:
>> >it wil
On 07/05/2019 17.50, Eric Blake wrote:
> On 5/7/19 10:22 AM, Thomas Huth wrote:
>> On 07/05/2019 15.22, Markus Armbruster wrote:
>>> Thomas Huth writes:
>>>
Currently, all tests are in the "auto" group. This is a little bit
pointless.
OTOH, we need a group for the tests that we can
>
> From: Pankaj Gupta
> Date: Thu, Apr 25, 2019 at 10:00 PM
>
> > +static inline bool daxdev_mapping_supported(struct vm_area_struct *vma,
> > + struct dax_device *dax_dev)
> > +{
> > + return !(vma->flags & VM_SYNC);
> > +}
>
> Shouldn't it be rather `ret
-- Forwarded message -
From: fengyd
Date: Wed, 8 May 2019 at 12:50
Subject: Re: [Qemu-devel] Fwd: How live migration work for vhost-user
To: Dr. David Alan Gilbert
Hi,
I checked the DPDK code and found that the function rte_vhost_enqueue_burst
in virtio_net.c is used to receiv
On 5/7/19 8:58 PM, Richard Henderson wrote:
> On 5/7/19 2:03 AM, Laurent Vivier wrote:
>> This patch breaks linux-user statically linked build on Fedora.
>>
>> Fedora doesn't provide static version of nettle and gcrypt, so the configure
>> fails.
>>
>> You should update the configure for them like
It's OK for unicore32 codes.
Thanks.
Guan Xuetao
> -Original Messages-
> From: "Peter Maydell"
> Sent Time: 2019-04-30 18:06:03 (Tuesday)
> To: "Richard Henderson"
> Cc: "QEMU Developers" , "Guan Xuetao"
>
> Subject: Re: [Qemu-devel] [PATCH 22/26] target/unicore32: Convert to
> CP
On 5/7/19 7:13 AM, Laurent Vivier wrote:
>> - if (seed_optarg != NULL) {
>> - qemu_guest_random_seed_main(seed_optarg, &error_fatal);
>> + {
>> + Error *err = NULL;
>> + if (seed_optarg != NULL) {
>> + qemu_guest_random_seed_main(seed_optarg, &err);
>> +
On 5/7/19 2:03 AM, Laurent Vivier wrote:
> This patch breaks linux-user statically linked build on Fedora.
>
> Fedora doesn't provide static version of nettle and gcrypt, so the configure
> fails.
>
> You should update the configure for them like you did for gnutls in PATCH 1.
Which fedora? I j
On Tue, May 07, 2019 at 12:21:29PM +0200, Greg Kurz wrote:
> On Tue, 7 May 2019 16:23:16 +1000
> David Gibson wrote:
>
> > The only remaining caller of pci_get_bus_devfn() is pci_nic_init_nofail(),
> > itself an old compatibility function. Fold the two together to avoid
> > re-using the stale i
Hello.
I'am student studying QEMU hypervisor and SPICE.
In order to find out the calling order of functions in QEMU source, I input
and compiled 'printf ("% s \ n", __ func__) "into source.
And when I run the VM and open 'domain_name.log' in '/ var / log / libvirt
/ qemu', I see that no output f
As noted in "c7a88b52f6 i386: Add new model of Cascadelake-Server"
Because MSR based feature has been supported by QEMU, we add
CPUID_7_0_EDX_ARCH_CAPABILITIES on Cascadelake-Server CPU model,
and add IA32_ARCH_CAPABILITIES MSR based features (RDCL_NO,
IBRS_ALL and SKIP_L1DFL_VMENTRY).
And "014018
On Tue, May 07, 2019 at 06:34:01PM +0200, Philippe Mathieu-Daudé wrote:
> As explained in commit aff39be0ed97:
>
> Both functions, object_initialize() and object_property_add_child()
> increase the reference counter of the new object, so one of the
> references has to be dropped afterwards t
On Tue, May 07, 2019 at 06:34:02PM +0200, Philippe Mathieu-Daudé wrote:
> As explained in commit aff39be0ed97:
>
> Both functions, object_initialize() and object_property_add_child()
> increase the reference counter of the new object, so one of the
> references has to be dropped afterwards t
On 5/7/2019 11:06 PM, Eric Blake wrote:
On 5/7/19 8:07 AM, Daniel P. Berrangé wrote:
On Tue, May 07, 2019 at 08:48:53PM +0800, Tao Xu wrote:
As noted in
http://lists.gnu.org/archive/html/qemu-devel/2018-09/msg02212.html
Rather than pointing to the mailing list post, please just refer
to the g
On 5/7/2019 9:07 PM, Daniel P. Berrangé wrote:
On Tue, May 07, 2019 at 08:48:53PM +0800, Tao Xu wrote:
As noted in
http://lists.gnu.org/archive/html/qemu-devel/2018-09/msg02212.html
Rather than pointing to the mailing list post, please just refer
to the git commit hash that patch was merged un
Amusingly, we had already ignored the comment to keep this value at the
end of CPUState. This restores the minimum negative offset from TCG_AREG0
for code generation.
For the couple of uses within qom/cpu.c, add a pointer from the CPUState
object to the IcountDecr object within CPUNegativeOffsetS
There was nothing armv7 specific about the bic+cmp sequence, however
looking at the set of guests more closely shows that the 8-bit immediate
operand for the bic can only be satisfied with one guest in tree:
baseline m-profile -- 10-bit pages with aligned 4-byte memory ops.
Therefore it does not se
On Tue, 07 May 2019 15:36:46 PDT (-0700), jonat...@fintelia.io wrote:
According to the spec, "All bits besides SSIP, USIP, and UEIP in the sip
register are read-only." Further, if an interrupt is not delegated to mode x,
then "the corresponding bits in xip [...] should appear to be hardwired to
z
On 5/7/19 3:49 AM, Laurent Vivier wrote:
>> void start_auth_vnc(VncState *vs)
>> {
>> - make_challenge(vs);
>> + Error *err = NULL;
>> +
>> + if (qcrypto_random_bytes(vs->challenge, sizeof(vs->challenge), &err)) {
>> + trace_vnc_auth_fail(vs, vs->auth, "cannot get random bytes
Consolidate some boilerplate from foo_cpu_initfn.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 11 +++
target/alpha/cpu.c | 3 +--
target/arm/cpu.c| 3 +--
target/cris/cpu.c | 3 +--
targe
Move cpu_get_tb_cpu_state below the include of "exec/cpu-all.h"
so that the definition of env_cpu is available.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/xtensa/cpu.h | 17 ++---
hw/xtensa/pic_cpu.c | 2 +-
linux-user/xtensa/cpu_loop.c
Now that we have ArchCPU, we can define this generically,
in the one place that needs it.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/gen-icount.h | 2 ++
target/alpha/cpu.h| 1 -
target/arm/cpu.h | 2 --
target/cris/cpu.h | 1 -
target/
This changes the code generation for the tlb from e.g.
ldr ip, [r6, #-0x10]
ldr r2, [r6, #-0xc]
and ip, ip, r4, lsr #8
ldrd r0, r1, [r2, ip]!
ldr r2, [r2, #0x18]
to
ldrd r0, r1, [r6, #-0x10]
and r0, r0, r4,
This macro is now always empty, so remove it. This leaves the
entire contents of CPUArchState under the control of the guest
architecture.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h | 2 --
target/alpha/cpu.h | 3 ---
target/arm/cpu.h|
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/tricore/cpu.h | 5 -
target/tricore/op_helper.c | 4 ++--
2 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 4c997b6d30..fc3328fdf5 100644
--- a/target/t
This changes the code generation for the tlb from e.g.
ldur x0, [x19, #0xffe0]
ldur x1, [x19, #0xffe8]
and x0, x0, x20, lsr #8
add x1, x1, x0
ldr x0, [x1]
ldr x1, [x1, #0x18]
to
ldp x
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/unicore32/cpu.h | 5 -
hw/unicore32/puv3.c | 2 +-
target/unicore32/helper.c | 8 ++--
target/unicore32/op_helper.c| 2 +-
target/unicore32/softmmu.c | 11 ---
target/un
We have for some time had code within the tcg backends to
handle large positive offsets from env. This move makes
sure that need not happen. Indeed, we are able to assert
at build time that simple offsets suffice for all hosts.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
i
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/tilegx/cpu.h | 5 -
linux-user/tilegx/cpu_loop.c | 2 +-
target/tilegx/helper.c | 2 +-
3 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
index 135df63
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/ppc/cpu.h| 7 +-
target/ppc/helper_regs.h| 4 +-
hw/ppc/ppc.c| 18 ++---
hw/ppc/ppc405_uc.c | 2 +-
hw/ppc/ppc_booke.c | 4 +-
linux-user/ppc/cpu_
Nothing in there so far, but all of the plumbing done
within the target ArchCPU state.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 24
include/exec/cpu-defs.h | 8
target/alpha/cpu.h | 1 +
target/arm/cpu.h
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/cpu.h | 5 -
linux-user/riscv/cpu_loop.c | 2 +-
target/riscv/cpu_helper.c | 4 ++--
target/riscv/csr.c | 12 ++--
target/riscv/op_helper.c| 8
5 files changed, 13 ins
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/cpu.h | 5 -
bsd-user/main.c | 2 +-
hw/sparc/leon3.c| 4 ++--
hw/sparc/sun4m.c| 4 ++--
hw/sparc64/sparc64.c| 2 +-
linux-user/sparc/cpu_loop.c |
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sh4/cpu.h | 5 -
linux-user/sh4/cpu_loop.c | 2 +-
target/sh4/helper.c | 26 --
target/sh4/op_helper.c| 9 +++--
4 files changed, 16 insertions(+), 26 deletions(-
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/s390x/cpu.h | 5
linux-user/s390x/cpu_loop.c | 2 +-
target/s390x/cc_helper.c| 5 ++--
target/s390x/diag.c | 2 +-
target/s390x/excp_helper.c | 6 ++---
target/s390x/fpu_helper.c | 4 +--
ta
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/openrisc/cpu.h | 5 -
linux-user/openrisc/cpu_loop.c | 2 +-
target/openrisc/exception_helper.c | 5 ++---
target/openrisc/sys_helper.c | 8
4 files changed, 7 insertions(+), 13 deletions(-
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h | 5 -
hw/nios2/cpu_pic.c | 5 +
target/nios2/mmu.c | 10 +-
3 files changed, 6 insertions(+), 14 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index b14095b8dc..f2ffc1469f 1
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/mips/cpu.h| 5 -
hw/intc/mips_gic.c | 2 +-
hw/mips/mips_int.c | 2 +-
linux-user/mips/cpu_loop.c | 2 +-
target/mips/helper.c | 15 +-
Now that we have both ArchCPU and CPUArchState, we can define
this generically instead of via macro in each target's cpu.h.
Reviewed-by: Peter Maydell
Acked-by: Alistair Francis
Signed-off-by: Richard Henderson
---
accel/tcg/atomic_template.h | 8 +--
accel/tcg/softmmu_template.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/moxie/cpu.h | 5 -
target/moxie/helper.c| 6 +++---
target/moxie/translate.c | 2 +-
3 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index 5b9aae95d2..a481a
For all targets, into this new file move TARGET_LONG_BITS,
TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS,
TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES.
Include this new file from exec/cpu-defs.h.
This now removes the somewhat odd requirement that target/arch/cpu.h
defines TARGET_LONG_BITS before
Fix all of the coding style errors in this file at once.
Signed-off-by: Richard Henderson
---
target/cris/op_helper.c | 817 +++-
1 file changed, 398 insertions(+), 419 deletions(-)
diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c
index 0ee3a311
Combined uses of CPU(x86_env_get_cpu()) were failures to use
the more proper, ENV_GET_CPU macro, now replaced by env_cpu.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/i386/cpu.h | 5 -
bsd-user/main.c| 3 +--
hw/i386/kvmvapic.c | 4 +
Fix all of the coding style errors in this file at once.
Signed-off-by: Richard Henderson
---
target/cris/mmu.c | 479 +++---
1 file changed, 237 insertions(+), 242 deletions(-)
diff --git a/target/cris/mmu.c b/target/cris/mmu.c
index b8db908823..9cb73bbf
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/lm32/cpu.h | 5 -
target/lm32/helper.c| 19 ++-
target/lm32/op_helper.c | 6 +++---
target/lm32/translate.c | 2 +-
4 files changed, 10 insertions(+), 22 deletions(-)
diff --git a/target/lm32
Combined uses of CPU(hppa_env_get_cpu()) were failures to use
the more proper, ENV_GET_CPU macro, now replaced by env_cpu.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/hppa/cpu.h | 5 -
linux-user/hppa/cpu_loop.c | 2 +-
target/hppa/helper.c | 3 +
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
linux-user/m68k/target_cpu.h | 2 +-
target/m68k/cpu.h| 5 -
linux-user/m68k-sim.c| 3 +--
linux-user/m68k/cpu_loop.c | 2 +-
target/m68k/helper.c | 33 -
target/
Combined uses of CPU(arm_env_get_cpu()) were failures to use
the more proper, ENV_GET_CPU macro, now replaced by env_cpu.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5 --
linux-user/aarch64/cpu_loop.c | 6 +-
linux-user/aarch64/signal.c
Move cpu_mmu_index below the include of "exec/cpu-all.h",
so that the definition of env_archcpu is available.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/microblaze/cpu.h | 35 ++--
linux-user/microblaze/cpu_loop.c | 2 +-
target/
For all targets, do this just before including exec/cpu-all.h.
Reviewed-by: Peter Maydell
Acked-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/alpha/cpu.h | 1 +
target/arm/cpu.h| 1 +
target/cris/cpu.h | 1 +
target/hppa/cpu.h | 1 +
target/i386/cpu.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/cris/cpu.h | 5 -
linux-user/cris/cpu_loop.c | 2 +-
target/cris/mmu.c | 3 +--
target/cris/op_helper.c| 10 +++---
target/cris/translate.c| 2 +-
5 files changed, 6 insertions(+), 16 del
Move all softmmu tlb data into this structure. Arrange the
members so that we are able to place mask+table together and
at a smaller absolute offset from ENV.
Reviewed-by: Peter Maydell
Acked-by: Alistair Francis
Signed-off-by: Richard Henderson
---
accel/tcg/softmmu_template.h | 4 +-
incl
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h | 17 -
accel/tcg/cputlb.c | 24
2 files changed, 16 insertions(+), 25 deletions(-)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 8f2a848bf5
This will replace foo_env_get_cpu with a generic definition.
No changes to the target specific code so far.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/include/exec/cpu
With exactly one exception, most uses of alpha_env_get_cpu
were failures to use the more proper, ENV_GET_CPU macro,
now replaced by env_cpu.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/alpha/cpu.h | 5 -
linux-user/alpha/cpu_loop.c | 2 +-
target/alpha/he
For all targets, do this just before including exec/cpu-all.h.
Reviewed-by: Peter Maydell
Acked-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/alpha/cpu.h | 4 ++--
target/arm/cpu.h| 4 ++--
target/cris/cpu.h | 4 ++--
target/hppa/cpu.h | 4 ++--
targ
Patches missing review/ack:
0010-target-cris-Reindent-mmu.c.patch (new)
0011-target-cris-Reindent-op_helper.c.patch (new)
0034-cpu-Move-icount_decr-to-CPUNegativeOffsetState.patch
0037-tcg-aarch64-Use-LDP-to-load-tlb-mask-table.patch
0038-tcg-arm-Use-LDRD-to-load-tlb-mask-table.patch
0039-tcg-arm-R
>
> are available in the Git repository at:
>
> git://git.kraxel.org/qemu tags/vga-20190507-pull-request
>
> for you to fetch changes up to 6306cae275c7091aa4e785809d956b475bfedab4:
>
> i2c-ddc: move it to hw/display (2019-05-07 09:56:10 +0200)
>
> --
On 5/7/19 3:37 PM, Peter Maydell wrote:
> I just ran into this test failure:
>
> PYTHONPATH=/home/linux1/qemu/scripts python3 -B
> /home/linux1/qemu/tests/qapi-schema/test-qapi.py
> /home/linux1/qemu/tests/qapi-schema/unicode-str.json
>> tests/qapi-schema/unicode-str.test.out
> 2>tests/qapi-schema
Yes, I was pasting the output of `git format-patch`. Gmail displays
properly for me, but seems to have hard-wrapped the plaintext version of my
outgoing message to 78 characters. I've tried re-sending from a different
address where I can use `git send-email` directly, please let me know if it
works
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