On Apr 2, 2019 3:49 PM, "Mateja Marjanovic"
wrote:
>
> From: Mateja Marjanovic
>
> The old version of the helper for the INSERT. MSA instructions
> has been replaced with four helpers that don't use switch, and change
> the endianness of the given index, when executed on a big endian host.
>
>
On May 19, 2019 6:35 AM, "Richard Henderson"
wrote:
>
> For Altivec, this is always an expansion.
>
> Signed-off-by: Richard Henderson
> ---
Large portions of this patch have nothing to do with what title or commit
message say.Reorganize.
Thanks, Aleksandar
> tcg/ppc/tcg-target.h | 2
For Altivec, this is done via vector shift by vector,
and loading the immediate into a register.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 58 ++--
2 files changed, 57 insertions(+), 3 deletions(-)
diff
There are a few missing operations yet, like expansion of
multiply and shifts. But this has move, load, store, and
basic arithmetic.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 36 +-
tcg/ppc/tcg-target.opc.h | 3 +
tcg/ppc/tcg-target.inc.c | 707
For Altivec, this is always an expansion.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.opc.h | 8 +++
tcg/ppc/tcg-target.inc.c | 112 ++-
3 files changed, 120 insertions(+), 2 deletions(-)
diff --git
Based-on: <20190518190157.21255-1-richard.hender...@linaro.org>
Aka "tcg: misc gvec improvements".
Version 3 was last posted in March,
https://lists.gnu.org/archive/html/qemu-devel/2019-03/msg05859.html
Changes since v3:
* Add support for bitsel, with the vsx xxsel insn.
* Rely on the new
This is only used for 32-bit hosts.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.inc.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 9d58db9eb1..3219df2e90 100644
--- a/tcg/ppc/tcg-target.inc.c
+++
This includes vector load/store with immediate offset, some extra
move and splat insns, compare ne, and negate.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 3 +-
tcg/ppc/tcg-target.inc.c | 103 ++-
2 files changed, 94 insertions(+), 12
This includes single-word loads and stores, lots of double-word
arithmetic, and a few extra logical operations.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 3 +-
tcg/ppc/tcg-target.inc.c | 111 +++
2 files changed, 91 insertions(+), 23
This includes double-word loads and stores, double-word load and splat,
double-word permute, and bit select. All of which require multiple
operations in the base Altivec instruction set.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 5 ++--
tcg/ppc/tcg-target.inc.c | 51
I just noticed when I had replied that my e-mail was sent from a different
name, by accident, as I was testing something with my e-mail client.
On 5/18/2019 5:27 PM, Jim Payne wrote:
On 5/16/2019 9:04 PM, Thomas Huth wrote:
On 10/05/2019 12.46, Gerd Hoffmann wrote:
This patch series changes
Section 3.6 in RISC-V v1.10 privilege specification states that PMP violations
report "access exceptions." The current PMP implementation has
a bug which wrongly reports "page exceptions" on PMP violations.
This patch fixes this bug by reporting the correct PMP access exceptions
trap values.
The current implementation unnecessarily checks for PMP even if MMU translation
failed. This may trigger a wrong PMP access exception instead of
a page exception.
For example, the very first instruction fetched after the first satp write in
S-Mode will trigger a PMP access fault instead of an
The PMP should be checked when doing a page table walk, and report access
fault exception if the to-be-read PTE address failed the PMP check.
Suggested-by: Jonathan Behrens
Signed-off-by: Hesham Almatary
---
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 10 +-
2 files
Hi Jonathan,
Thanks for your feedback.
On Sat, 18 May 2019 at 22:51, Jonathan Behrens wrote:
>
> This patch assumes that translation failure should always raise a paging
> fault, but it should be possible for it to raise an access fault as well
> (since according to the spec "PMP checks are
Hi Gerd,
On 5/10/19 12:46 PM, Gerd Hoffmann wrote:
> Instead of fetching the prebuilt image from patchew download the install
> iso and prepare the image locally. Install to disk, using the serial
> console. Create qemu user, configure ssh login. Install packages
> needed for qemu builds.
I'm
Hi Gerd,
On 5/10/19 12:46 PM, Gerd Hoffmann wrote:
> Signed-off-by: Gerd Hoffmann
> ---
> tests/vm/Makefile.include | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/tests/vm/Makefile.include b/tests/vm/Makefile.include
> index 47084d5717c6..8714b5947958 100644
> ---
On 5/10/19 12:46 PM, Gerd Hoffmann wrote:
> Configure apt proxy so package downloads
> can be cached and can pass firewalls.
>
> Signed-off-by: Gerd Hoffmann
> ---
> tests/vm/ubuntu.i386 | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/tests/vm/ubuntu.i386 b/tests/vm/ubuntu.i386
>
On 5/10/19 12:46 PM, Gerd Hoffmann wrote:
> Packages are fetched via proxy that way, if configured on the host.
> That might be required to pass firewalls, and it allows to route
> package downloads through a caching proxy server.
>
> Needs AcceptEnv setup in sshd_config on the guest side to
> I've never been fully convinced of this, why not just use the generic
loader?
If I understand you are proposing passing bbl (or other firmware) with the
-kernel flag, and then vmlinux (or another kernel) with the -initrd flag?
Wouldn't this result in losing the ability to pass a real init
This patch assumes that translation failure should always raise a paging
fault, but it should be possible for it to raise an access fault as well
(since according to the spec "PMP checks are also applied to
page-table accesses for virtual-address translation, for which the
effective
On 5/16/2019 9:04 PM, Thomas Huth wrote:
On 10/05/2019 12.46, Gerd Hoffmann wrote:
This patch series changes the way virtual machines for test builds are
managed. They are created locally on the developer machine now. The
installer is booted on the serial console and the scripts walks
I applied the four patches you indicated and the image boots up and
runs. Everything seems to be working now. Thank You.
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https://bugs.launchpad.net/bugs/1829576
Title:
Based-on: <20190518190157.21255-1-richard.hender...@linaro.org>
Aka "tcg: misc gvec improvements".
We've added (or are adding) generic support for variable vector shifts
and bitsel. This trivially replaces the implementations of BSL, BIT,
and BSL. It enables a reasonable implementation of
These instructions shift left or right depending on the sign
of the input, and 7 bits are significant to the shift. This
requires several masks and selects in addition to the actual
shifts to form the complete answer.
That said, the operation is still a small improvement even for
two 64-bit
This replaces 3 target-specific implementations for BIT, BIF, and BSL.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.h | 2 +
target/arm/translate.h | 3 --
target/arm/translate-a64.c | 15 ++--
target/arm/translate.c | 78 +++---
4
The current implementation unnecessarily checks for PMP even if MMU translation
failed. This may trigger a wrong PMP access exception instead of
a page exception.
For example, the very first instruction fetched after the first satp write in
S-Mode will trigger a PMP access fault instead of an
The gvec expanders take care of masking the shift amount
against the element width.
Signed-off-by: Richard Henderson
---
target/ppc/helper.h | 12 --
target/ppc/int_helper.c | 37 -
target/ppc/translate/vmx-impl.inc.c | 24
Section 3.6 in RISC-V v1.10 privilege specification states that PMP violations
report "access exceptions." The current PMP implementation has
a bug which wrongly reports "page exceptions" on PMP violations.
This patch fixes this bug by reporting the correct PMP access exceptions
trap values.
The paths through tcg_gen_dup_mem_vec and through MO_128 were
missing the check_size_align. The path through MO_128 was also
missing the expand_clr. This last was not visible because the
only user is ARM SVE, which would set oprsz == maxsz, and not
require the clear.
Fix by adding the
Replace the target-specific implementation of XXSEL.
Signed-off-by: Richard Henderson
---
target/ppc/translate/vsx-impl.inc.c | 24 ++--
1 file changed, 2 insertions(+), 22 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
Based-on: <20190518190157.21255-1-richard.hender...@linaro.org>
Aka "tcg: misc gvec improvements".
Since Mark's initial patches, we've added (or are adding)
generic support for variable vector shifts and bitsel.
r~
Richard Henderson (2):
target/ppc: Use vector variable shifts for VSL, VSR,
The VBROADCASTSD instruction only allows %ymm registers as destination.
Rather than forcing VEX.L and writing to the entire 256-bit register,
revert to using MOVDDUP with an %xmm register. This is sufficient for
an avx1 host since we do not support TCG_TYPE_V256 for that case.
Also fix the
This operation performs d = (b & a) | (c & ~a), and is present
on a majority of host vector units. Include gvec expanders.
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.h | 2 ++
tcg/aarch64/tcg-target.h | 1 +
tcg/i386/tcg-target.h| 1 +
tcg/tcg-op-gvec.h
Perform a per-element conditional move. This combination operation is
easier to implement on some host vector units than plain cmp+bitsel.
Omit the usual gvec interface, as this is intended to be used by
target-specific gvec expansion call-backs.
Signed-off-by: Richard Henderson
---
We already had backend support for this feature. Expand the new
cmpsel opcode using vpblendb. The combination allows us to avoid
an extra NOT for some comparison codes.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 2 +-
tcg/i386/tcg-target.inc.c | 39
Add support for bitsel and cmpsel primitives, which will be
used by target/* patches that I'll post shortly.
Improvements to the i386 and aarch64 backends.
A handfull of bug fixes.
Assert that we haven't forgotten a QEMU_ALIGNED() marker,
by using MOVDQA for x86_64.
r~
Richard Henderson
This makes do_op3 match do_op2 in allowing for failure,
and thus fall back expansions.
Signed-off-by: Richard Henderson
---
tcg/tcg-op-vec.c | 45 +++--
1 file changed, 27 insertions(+), 18 deletions(-)
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
This is now handled by code within tcg-op-vec.c.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.inc.c | 37 -
1 file changed, 37 deletions(-)
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index ffcafb1e14..569a2c2120 100644
---
Using umin(a, b) == a as an expansion for TCG_COND_LEU is a
better alternative to (a - INT_MIN) <= (b - INT_MIN).
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.inc.c | 80 +--
1 file changed, 61 insertions(+), 19 deletions(-)
diff --git
Use MOVI+ORR or MVNI+BIC in order to build some vector constants,
as opposed to dropping them to the constant pool. This includes
all 16-bit constants and a similar set of 32-bit constants.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.inc.c | 47
This instruction raises #GP, aka SIGSEGV, if the effective address
is not aligned to 16-bytes.
We have assertions in tcg-op-gvec.c that the offset from ENV is
aligned, for vector types <= V128. But the offset itself does not
validate that the final pointer is aligned -- one must also remember
to
The compliment of a subset of immediates can be computed
with a single instruction.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.inc.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index
Provide a generic fallback for the min/max operations.
Signed-off-by: Richard Henderson
---
tcg/tcg-op-vec.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index 004a34935b..501d9630a2 100644
--- a/tcg/tcg-op-vec.c
The instruction set has 3 insns that perform the same operation,
only varying in which operand must overlap the destination. We
can represent the operation without overlap and choose based on
the operands seen.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 2 +-
There are several sub-classes of vector immediate, and only MOVI
can use them all. This will enable usage of MVNI and ORRI, which
use progressively fewer sub-classes.
This patch adds no new functionality, merely splits the function
and moves part of the logic into tcg_out_dupi_vec.
The allows immediates to be used for ORR and BIC,
as well as the trivial inversions, ORC and AND.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.inc.c | 90 +---
1 file changed, 83 insertions(+), 7 deletions(-)
diff --git
If INDEX_op_foo is always expanded by tcg_expand_vec_op, then
there may be no reasonable set of constraints to return from
tcg_target_op_def for that opcode.
Let TCG_TARGET_HAS_foo be specified as -1 in that case. Thus a
boolean test for TCG_TARGET_HAS_foo is true, but we will not
assert within
On 5/18/2019 1:39 AM, Klaus Birkelund Jensen wrote:
`nvme_dma_read_prp` erronously used `qemu_iovec_*to*_buf` instead of
`qemu_iovec_*from*_buf` when the request involved the controller memory
buffer.
Signed-off-by: Klaus Birkelund Jensen
---
hw/block/nvme.c | 2 +-
1 file changed, 1
On 5/17/19 3:44 PM, Jan Bobek wrote:
> Have the --xfeature option accept "sse", "avx" and "avx512" in
> addition to a plain numerical value, purely for users' convenience.
>
> Suggested-by: Richard Henderson
> Signed-off-by: Jan Bobek
> ---
> risu_reginfo_i386.c | 11 ++-
> 1 file
On 5/17/19 3:44 PM, Jan Bobek wrote:
> The original code used "magic numbers", which made it unclear in
> some places. Include a reference to the Intel manual where the
> constants' meaning is discussed.
>
> Signed-off-by: Jan Bobek
> ---
> risu_reginfo_i386.c | 48
On Apr 2, 2019 3:44 PM, "Mateja Marjanovic"
wrote:
>
> From: Mateja Marjanovic
>
> The old version of the helper for the COPY_U. MSA instructions
> has been replaced with four helpers that don't use switch, and change
> the endianness of the given index, when executed on a big endian host.
>
>
On 5/17/19 3:44 PM, Jan Bobek wrote:
> CPU-specific code in risu_reginfo_* is expected to define and export
> the following symbols:
>
> - arch_long_opts, arch_extra_help, process_arch_opt
> - reginfo_size
> - reginfo_init
> - reginfo_is_eq
> - reginfo_dump, reginfo_dump_mismatch
>
> Make
On 5/17/19 3:44 PM, Jan Bobek wrote:
> The code being removed is a remnant of the past implementation; it has
> since been replaced by its more powerful, architecture-independent
> counterpart in reginfo.c.
>
> Reviewed-by: Alex Bennée
> Signed-off-by: Jan Bobek
> ---
> risu_i386.c | 58
On Apr 2, 2019 3:44 PM, "Mateja Marjanovic"
wrote:
>
> From: Mateja Marjanovic
>
> The old version of the helper for the COPY_S. MSA instructions
> has been replaced with four helpers that don't use switch, and change
> the endianness of the given index, when executed on a big endian host.
>
>
On 5/17/19 3:44 PM, Jan Bobek wrote:
> risu_i386.c is expected to implement the following functions:
>
> - advance_pc
> - get_reginfo_paramreg, set_ucontext_paramreg
> - get_risuop
> - get_pc
>
> This patch adds the necessary code. We use EAX as the parameter
> register and opcode "UD1
On 5/17/19 3:44 PM, Jan Bobek wrote:
> This allows us to drop dependency on NASM and build the test image
> with GCC only. Adds support for x86_64, too.
>
> Suggested-by: Richard Henderson
> Signed-off-by: Jan Bobek
> ---
> Makefile| 3 +++
> test_i386.S | 41
On 5/17/19 3:44 PM, Jan Bobek wrote:
> Now that i386 and x86_64 architectures are supported by RISU, we want
> to detect them and build RISU for them automatically.
>
> Suggested-by: Richard Henderson
> Signed-off-by: Jan Bobek
> ---
> configure | 10 ++
> 1 file changed, 6
On 5/17/19 3:44 PM, Jan Bobek wrote:
> In order to build risu successfully for i386, we need files
> risu_reginfo_i386.{h,c}; this patch adds the latter by extracting the
> relevant code from risu_i386.c.
>
> This patch is pure code motion; no functional changes were made.
>
> Reviewed-by: Alex
On 5/17/19 3:44 PM, Jan Bobek wrote:
> In order to build risu successfully for i386, we need files
> risu_reginfo_i386.{h,c}; this patch adds the former by extracting the
> relevant code from risu_i386.c.
>
> This patch is pure code motion; no functional changes were made.
>
> Reviewed-by: Alex
On 5/17/19 3:44 PM, Jan Bobek wrote:
> At least GCC defines the symbol "i386" to 1 to signal the target
> platform. We need to use "i386" as an undefined symbol in order to
> correctly include risu_reginfo_i386.h from risu.h. Add an -U option to
> the build command to make sure the symbol remains
On Fri, 17 May 2019 20:28:11 -0700
Li Qiang wrote:
Lacking commit message.
> CC: qemu-triv...@nongnu.org
> Signed-off-by: Li Qiang
> ---
> hw/pci/msix.c | 2 --
> hw/vfio/pci.c | 2 --
> include/hw/pci/msix.h | 2 ++
> 3 files changed, 2 insertions(+), 4 deletions(-)
>
> diff
On Fri, 17 May 2019 20:28:10 -0700
Li Qiang wrote:
An actual trivial patch, but it could still use a commit message.
> CC: qemu-triv...@nongnu.org
> Signed-off-by: Li Qiang
> ---
> hw/vfio/platform.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git
On Fri, 17 May 2019 20:28:09 -0700
Li Qiang wrote:
> As the vmstate structure names aren't related with
> the QOM type names.
Seems contrary to the first patch in the series.
> CC: qemu-triv...@nongnu.org
> Signed-off-by: Li Qiang
> ---
> hw/vfio/amd-xgbe.c | 2 +-
> hw/vfio/ap.c
On Fri, 17 May 2019 20:28:08 -0700
Li Qiang wrote:
Why? (No commit message, nor cover letter)
> CC: qemu-triv...@nongnu.org
> Signed-off-by: Li Qiang
> ---
> hw/vfio/pci.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
> index
Jan Bobek writes:
> This patch series adds support for i386 and x86_64 architectures to
> RISU. Notably, vector registers (SSE, AVX, AVX-512) are supported for
> verification of the apprentice. This is V2 of the series posted in
> [1].
>
> I decided not to drop the register definitions from
Remove multiple errors and warnings generated by checkpatch.pl tool.\nERROR:
code indent should never use tabs\nERROR: trailing whitespace\nWARNING: Block
comments use a leading /* on a separate line
---
target/sparc/asi.h | 352 -
1 file
Fix applied to qemu 4.1
** Changed in: qemu
Status: New => Fix Released
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https://bugs.launchpad.net/bugs/1824622
Title:
Qemu 4.0.0-rc3 COLO Primary Crashes with "Assertion
I suspect that this may be related to the VSR register conversion. Can
you try applying all of the patches below on top of 4.0 to see if they
resolve the issue?
https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg01254.html
https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg01256.html
`nvme_dma_read_prp` erronously used `qemu_iovec_*to*_buf` instead of
`qemu_iovec_*from*_buf` when the request involved the controller memory
buffer.
Signed-off-by: Klaus Birkelund Jensen
---
hw/block/nvme.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/block/nvme.c
On Fri, May 17, 2019 at 07:49:18PM -0600, Heitke, Kenneth wrote:
> > > > > > +if (qemu_iovec_from_buf(, 0, ptr, len) != len) {
> > > > >
> > > > > This should be `qemu_iovec_to_buf`.
> > > > >
> > > >
> > > > This function is transferring data from the "host" to the device so I
> > > >
On 17/05/2019 20.32, Markus Armbruster wrote:
> Fixes: a442fe2f2b2f20e7be0934277e9400b844b11999
> Cc: qemu-triv...@nongnu.org
> Signed-off-by: Markus Armbruster
> ---
> configure | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/configure b/configure
> index
72 matches
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