On 24/05/2019 22:14, Eduardo Habkost wrote:
On Fri, May 24, 2019 at 04:39:12PM +0200, Laurent Vivier wrote:
On 24/05/2019 16:10, Igor Mammedov wrote:
On Fri, 24 May 2019 12:35:21 +0200
Laurent Vivier wrote:
On pseries, core-ids are strongly binded to a node-id by the command
line option. If
On 24/05/2019 20.59, Aaro Koskinen wrote:
> Hi,
>
> On Fri, May 24, 2019 at 06:00:18PM +0300, Aaro Koskinen wrote:
>> Please don't delete OMAP boards quite yet :) In the mainline kernel
>> they are not orphaned, they frequently get tested using actual hardware,
>> and QEMU would help in additional
Paolo Bonzini writes:
> On 23/05/19 21:57, Markus Armbruster wrote:
A large number of headers don't pass this test, by design or by
accident. To keep things more manageable, exclude all headers outside
include/ for now.
>>> A lot of these, either in include/ or outside, are _meant
migration_version attribute is used to check migration compatibility
between two mdev device of the same mdev type.
The key is that it's rw and its data is opaque to userspace.
Userspace reads migration_version of mdev device at source side and
writes the value to migration_version attribute of md
This feature implements the migration_version attribute for Intel's vGPU
mdev devices.
migration_version attribute is rw.
It's used to check migration compatibility for two mdev devices of the
same mdev type.
migration_version string is defined by vendor driver and opaque to
userspace.
For Intel
This patchset introduces a migration_version attribute under sysfs of VFIO
Mediated devices.
This migration_version attribute is used to check migration compatibility
between two mdev devices of the same mdev type.
Patch 1 defines migration_version attribute in
Documentation/vfio-mediated-device.
> On Sunday, May 26, 2019, 10:10:39 PM GMT+9, Laurent Vivier
wrote: > On 26/05/2019 09:28, Lucien Murray-Pitts wrote:
>> On CPU32 and the early 68000 and 68010 the ISP doesnt exist.
>> These CPUs only have SSP/USP.
>> [SNIP]
>> The movec instruction when accessing these shadow registers
>> i
On Tue, Mar 26, 2019 at 10:43:20AM +0800, Wei Yang wrote:
>arm and i386 has almost the same function acpi_add_rom_blob(), except
>giving different FWCfgCallback function.
>
>This patch moves acpi_add_rom_blob() to utils.c by passing
>FWCfgCallback to it.
>
>Signed-off-by: Wei Yang
>Reviewed-by: Ig
On Thu, Apr 11, 2019 at 10:32:39AM +0200, Thomas Huth wrote:
>On 11/04/2019 09.17, Wei Yang wrote:
>> pc_memory_pre_plug() is called during hotplug for both pc-dimm and
>> nvdimm. This is more proper to check apci hotplug capability before
>> check nvdimm specific capability.
>>
>> Signed-off-by:
It might be a red herring...
The AIX Boot procedure under 3.1.0 issues a
LED{814}
which it doesn't issue under 4.0.50 (so a different path is taken at
some point by the AIX kernel)
First I need to determine what AIX code 814 stands for (but it could be
auxiliary)
Before going into the ".dispat
This is the result at the same breakpoint under 3.1.0 (note the
difference in the TLB) (notably Segment Lookaside Buffer entry #1)
(qemu) info tlb
info tlb
SLB ESIDVSID
0 0x0800 0x04002400
1 0xf0002800 0x000802001080
3
On May 24, 2019 9:29 AM, "Alex Bennée" wrote:
>
>
> Laurent Vivier writes:
>
> > In current code, __NR_msgrcv and__NR_semtimedop are supposed to be
> > defined if __NR_msgsnd is defined.
> >
> > But linux headers 5.2-rc1 for MIPS define __NR_msgsnd without defining
> > __NR_semtimedop and it brea
On 26/05/2019 03:01, Keno Fischer wrote:
> Drive by comment, since I spotted this in my inbox.
> When I tried to make this change (two years ago though),
> I additionally needed the following. Unfortunately, I don't quite remember
> exactly what the issue was, but I think qemu would crash trying to
Am Sun, 26 May 2019 00:50:13 +0200
schrieb Laurent Vivier :
> If you want to test the machine, it doesn't yet boot a MacROM, but
> you can boot a linux kernel from the command line.
>
> You can install your own disk using debian-installer with:
>
> ./qemu-system-m68k \
> -M q800 \
>
>From qemu monitor :
(qemu) info tlb
info tlb
SLB ESIDVSID
0 0x0800 0x04002400
3 0xf10005000800 0x40500400
4 0xf1001800 0x41000400
5 0xf10008000800 0x40800400
6 0xf1
From: Mateja Marjanovic
MSA instructions MOD_. when dividing by zero,
didn't return the same value when executed on a referent hardware
(FPGA MIPS 64 r6, little endian) and when executed on QEMU, which
is not a real bug, because the result when dividing by zero is
UNPREDICTABLE [1] (page 255, 256
From: Mateja Marjanovic
Fix the case when the host is a big endian machine, and change
the approach toward LD. instruction helpers.
Signed-off-by: Mateja Marjanovic
Signed-off-by: Aleksandar Markovic
Reviewed-by: Aleksandar Markovic
Message-Id: <1554212605-16457-2-git-send-email-mateja.marjan
From: Aleksandar Markovic
The following changes since commit a7b21f6762a2d6ec08106d8a7ccb11829914523f:
Merge remote-tracking branch
'remotes/vivier2/tags/linux-user-for-4.1-pull-request' into staging (2019-05-24
12:47:49 +0100)
are available in the git repository at:
https://github.com/A
From: Mateja Marjanovic
The old version of the helper for the COPY_S. MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.
Signed-off-by: Mateja Marjanovic
Signed-off-by: Aleksandar Markovic
From: Laurent Vivier
In current code, __NR_msgrcv and__NR_semtimedop are supposed to be
defined if __NR_msgsnd is defined.
But linux headers 5.2-rc1 for MIPS define __NR_msgsnd without defining
__NR_semtimedop and it breaks the QEMU build.
__NR_semtimedop is defined in asm-mips/unistd_n64.h and
From: Mateja Marjanovic
MSA instructions DIV_. when dividing by zero,
didn't return the same value when executed on a referent hardware
(FPGA MIPS 64 r6, little endian) and when executed on QEMU, which
is not a real bug, because the result when dividing by zero is
UNPREDICTABLE [1] (page 141, 142
From: Jules Irenge
Realign comments to fix warnings issued by checkpatc.pl tool
"WARNING: Block comments use a leading /* on a separate line"
within "target/mips/cpu.h" file.
Signed-off-by: Jules Irenge
Signed-off-by: Aleksandar Markovic
Reviewed-by: Aleksandar Markovic
Message-Id: <20190413
From: Jakub Jermář
This commit addresses QEMU Bug #1825311:
mips_cpu_handle_mmu_fault renders all accessed pages executable
It allows finer-grained control over whether the accessed page should
be executable by moving the decision to the underlying map_address
function, which has more informa
From: Mateja Marjanovic
The old version of the helper for the INSERT. MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.
Signed-off-by: Mateja Marjanovic
Signed-off-by: Aleksandar Markovic
From: Mateja Marjanovic
Fix the case when the host is a big endian machine, and change
the approach toward ST. instruction helpers.
Signed-off-by: Mateja Marjanovic
Signed-off-by: Aleksandar Markovic
Reviewed-by: Aleksandar Markovic
Message-Id: <1554212605-16457-3-git-send-email-mateja.marjan
From: Philippe Mathieu-Daudé
This tests boot a full VM and check the serial console until
the SSH daemon is running, then start a SSH session and run
some commands.
This test can be run using:
$ avocado --show=ssh run -t arch:mips tests/acceptance/linux_ssh_mips_malta.py
ssh: Entering inter
Am Sun, 26 May 2019 00:50:05 +0200
schrieb Laurent Vivier :
> There is no DMA in Quadra 800, so the CPU reads/writes the data from
> the PDMA register (offset 0x100, ESP_PDMA in hw/m68k/q800.c) and
> copies them to/from the memory.
>
> There is a nice assembly loop in the kernel to do that, see
>
From: Jules Irenge
Add or remove space to fix errors issued by checkpatch.pl tool
"ERROR: spaces required around that..."
"ERROR: space required after that..."
"ERROR: space required before the open parenthesis"
"ERROR: space required after that..."
"ERROR: space prohibited between function name
From: Mateja Marjanovic
The old version of the helper for the COPY_U. MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.
Signed-off-by: Mateja Marjanovic
Signed-off-by: Aleksandar Markovic
Am Sun, 26 May 2019 00:50:04 +0200
schrieb Laurent Vivier :
> On Sparc and PowerMac, the bit 0 of the address
> selects the register type (control or data) and
> bit 1 selects the channel (B or A).
>
> On m68k Macintosh, the bit 0 selects the channel and
> bit 1 the register type.
>
> This patch
On Fri 24 May 2019 07:28:10 PM CEST, Max Reitz wrote:
> +##
> +# @ImageRotationalInfo:
> +#
> +# Indicates whether an image is stored on a rotating disk or not.
> +#
> +# @solid-state: Image is stored on a solid-state drive
> +#
> +# @rotating:Image is stored on a rotating disk
What happens w
On Fri 24 May 2019 03:56:21 PM CEST, Max Reitz wrote:
>> +---+---+--+---+--+--+
>> | file|before| after| gain |
>> +---+---+--+---+--+--+
>> |ssd| 61.153 | 36.313 | 41% |
>> |
From: Antonio Ospite
The configure script breaks when the qemu source directory is in a path
containing white spaces, in particular the list of targets is not
correctly generated when calling "./configure --help" because of how the
default_target_list variable is built.
In addition to that, *bui
From: Antonio Ospite
Since commit 79d77bcd36 (configure: Remove --source-path option,
2019-04-29) source_path cannot be overridden anymore, move it out of the
"default parameters" block since the word "default" may suggest that the
value can change, while in fact it does not.
While at it, only s
Hi,
Here is a v3 set to address
https://bugs.launchpad.net/qemu/+bug/1817345
CCing Laurent Vivier as the patch is going through the trivial-patches
branch.
The series follows up to:
https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg00562.html
Changes since v2:
- Shorten 'if' check as s
On 2019/5/19 4:54, Like Xu wrote:
This patch series make existing cores/threads/sockets into machine
properties and get rid of global smp_* variables they use currently.
The purpose of getting rid of globals is disentangle layer violations and
let's do it one step at a time by replacing the smp_
On 26/05/2019 09:28, Lucien Murray-Pitts wrote:
On CPU32 and the early 68000 and 68010 the ISP doesnt exist.
These CPUs only have SSP/USP.
The availability of this feature is determined by the
implementation of Master mode bit in the SR register.
Those with the master-mode bit have ISP.
Additi
On 26/05/2019 09:50, Lucien Murray-Pitts wrote:
A regression that was introduced, with the refactor to TranslatorOps,
drops two lines that update the PC when single-stepping is being performed.
( short commit 11ab74b )
This patch resolves that issue.
Signed-off-by: Lucien Murray-Pitts
---
ta
On 26/05/2019 09:45, Lucien Murray-Pitts wrote:
The register request via gdbstub would return the SR part
which contains the Trace/Master/IRQ state flags, but
would be missing the CR (Condition Register) state bits.
This fix adds this support by merging them in the m68k
specific gdbstub handler
On 5/26/19 9:41 AM, Yuval Shaia wrote:
On Fri, May 24, 2019 at 08:24:30AM +0300, Marcel Apfelbaum wrote:
Hi Yuval,
On 5/5/19 1:55 PM, Yuval Shaia wrote:
Any GID change in guest must be propogate to host. This is already done
by firing QMP event to managment system such as libvirt which in t
> On Sunday, May 26, 2019, 4:45:26 PM GMT+9, wrote: >
Subject; [Qemu-devel] [PATCH] Incorrect Stack Pointer shadow register support
on some m68k CPUs > .> snip> .> === OUTPUT BEGIN ===
> ERROR: Author email address is mangled by the mailing list
> #2:
> Author: Lucien Murray-Pitts
Patchew URL:
https://patchew.org/QEMU/20190526075056.33865-1-lucienmp_antis...@yahoo.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190526075056.33865-1-lucienmp_antis...@yahoo.com
Type: series
Subject: [Qemu-devel] [PATCH]
The register request via gdbstub would return the SR part
which contains the Trace/Master/IRQ state flags, but
would be missing the CR (Condition Register) state bits.
This fix adds this support by merging them in the m68k
specific gdbstub handler
Signed-off-by: Lucien Murray-Pitts
---
target/m
Patchew URL:
https://patchew.org/QEMU/20190526072826.32956-1-lucienmp_antis...@yahoo.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190526072826.32956-1-lucienmp_antis...@yahoo.com
Type: series
Subject: [Qemu-devel] [PATCH]
A regression that was introduced, with the refactor to TranslatorOps,
drops two lines that update the PC when single-stepping is being performed.
( short commit 11ab74b )
This patch resolves that issue.
Signed-off-by: Lucien Murray-Pitts
---
target/m68k/translate.c | 2 ++
1 file changed, 2 ins
On CPU32 and the early 68000 and 68010 the ISP doesnt exist.
These CPUs only have SSP/USP.
The availability of this feature is determined by the
implementation of Master mode bit in the SR register.
Those with the master-mode bit have ISP.
Additional comments added to the features set to claify
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