On Tue, Jun 25, 2019 at 10:38:24PM -0700, no-re...@patchew.org wrote:
> Patchew URL:
> https://patchew.org/QEMU/20190626051903.26829-1-sjitindarsi...@gmail.com/
>
>
>
> Hi,
>
> This series seems to have some coding style problems. See output below for
> more information:
Suraj, please fix up
Patchew URL:
https://patchew.org/QEMU/20190628002844.24894-1-ehabk...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190628002844.24894-1-ehabk...@redhat.com
Type: series
Subject: [Qemu-devel] [PATCH v2 0/9] x86 CPU
From: Like Xu
To make smp_parse() more flexible and expansive, a smp_parse function
pointer is added to MachineClass that machine types could override.
The generic smp_parse() code in vl.c is moved to hw/core/machine.c, and
become the default implementation of MachineClass::smp_parse. A
From: Wei Yang
Use the same definition as features/user_features in CPUX86State.
Signed-off-by: Wei Yang
Message-Id: <20190620023746.9869-1-richardw.y...@linux.intel.com>
Signed-off-by: Eduardo Habkost
---
target/i386/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Roman Kagan
X86CPU.hv-spinlocks is a uint32 property that has a special setter
validating the value to be no less than 0xFFF and no bigger than
UINT_MAX. The latter check is redundant; as for the former, there
appears to be no reason to prohibit the user from setting it to a lower
value.
Ping, what's the status of this patch.
Li Qiang 于2019年6月22日周六 上午8:21写道：
> When emulating irqchip in qemu, such as following command:
>
> x86_64-softmmu/qemu-system-x86_64 -m 1024 -smp 4 -hda /home/test/test.img
> -machine kernel-irqchip=off --enable-kvm -vnc :0 -device edu -monitor stdio
>
>
On Sun, Jun 16, 2019 at 01:37:36PM +0100, Mark Cave-Ayland wrote:
> With the conversion of PPC VSX registers to host endian during the 4.0
> development
> cycle, the VSX helpers getVSR() and putVSR() which were used to convert
> between big
> endian and host endian (and are currently just a
From: Like Xu
The CPUID.1F as Intel V2 Extended Topology Enumeration Leaf would be
exposed if guests want to emulate multiple software-visible die within
each package. Per Intel's SDM, the 0x1f is a superset of 0xb, thus they
can be generated by almost same code as 0xb except die_offset setting.
The variable is completely unused, probably a leftover from
previous code clean up.
Signed-off-by: Eduardo Habkost
Message-Id: <20190625050008.12789-3-ehabk...@redhat.com>
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Eduardo Habkost
---
target/i386/cpu.c | 6 --
1 file changed, 6
From: Igor Mammedov
Fallback might affect guest or worse whole host performance
or functionality if backing file were used to share guest RAM
with another process.
Patch deprecates fallback so that we could remove it in future
and ensure that QEMU will provide expected behavior and fail if
it
From: Igor Mammedov
Implicit RAM distribution between nodes has exactly the same issues as:
"numa: deprecate 'mem' parameter of '-numa node' option"
only with QEMU being the user that's 'adding' 'mem' parameter.
Deprecate it, to get it out of the way so that we could consolidate
guest RAM
From: Alex Bennée
Commit 2d384d7c8 broken the build when built with:
configure --without-default-devices --disable-user
The reason was the conversion of cpu->hyperv_synic to
cpu->hyperv_synic_kvm_only although the rest of the patch introduces a
feature checking mechanism. So I've fixed the
From: Like Xu
The field die_id (default as 0) and has_die_id are introduced to X86CPU.
Following the legacy smp check rules, the die_id validity is added to
the same contexts as leagcy smp variables such as hmp_hotpluggable_cpus(),
machine_set_cpu_numa_node(), cpu_slot_to_string() and
hppa_cpu_list() is dead code and is never called. Delete it.
Cc: Richard Henderson
Reviewed-by: Igor Mammedov
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Eduardo Habkost
Message-Id: <20190517191332.23400-1-ehabk...@redhat.com>
Acked-by: Richard
From: Igor Mammedov
Legacy '-numa node,mem' option has a number of issues and mgmt often
defaults to it. Unfortunately it's no possible to replace it with
an alternative '-numa memdev' without breaking migration compatibility.
What's possible though is to deprecate it, keeping option working
From: Like Xu
The global smp variables in vl.c are completely replaced with machine
properties.
Form this commit, the smp_cpus/smp_cores/smp_threads/max_cpus are deprecated
and only machine properties within MachineState are fully applied and enabled.
Signed-off-by: Like Xu
Reviewed-by:
From: Like Xu
In new sockets/dies/cores/threads model, the apicid of logical cpu could
imply die level info of guest cpu topology thus x86_apicid_from_cpu_idx()
need to be refactored with #dies value, so does apicid_*_offset().
To keep semantic compatibility, the legacy pkg_offset which helps
From: Like Xu
The global smp variables in i386 are replaced with smp machine properties.
To avoid calling qdev_get_machine() as much as possible, some related funtions
for acpi data generations are refactored. No semantic changes.
A local variable of the same name would be introduced in the
The current default value for hv-spinlocks is 0x (meaning
"never retry"). However, the value is stored as a signed
integer, making the getter of the hv-spinlocks QOM property
return -1 instead of 0x.
Fix this by changing the type of X86CPU::hyperv_spinlock_attempts
to uint32_t.
From: Like Xu
The global smp variables in s390x are replaced with smp machine properties.
A local variable of the same name would be introduced in the declaration
phase if it's used widely in the context OR replace it on the spot if it's
only used once. No semantic changes.
Signed-off-by: Like
If cpu->host_phys_bits_limit is set, QEMU will make
cpu->phys_bits be lower than host_phys_bits on some cases. This
triggers a warning that was supposed to be printed only if
phys-bits was explicitly set in the command-line.
Reorder the code so the value of cpu->phys_bits is validated
before the
From: Igor Mammedov
QEMU will crash when device-memory-region-size property is read if
ms->device_memory
wasn't initialized yet.
Crash can be reproduced with:
$QEMU -preconfig -qmp unix:qmp_socket,server,nowait &
./scripts/qmp/qom-get -s qmp_socket /machine.device-memory-region-size
Instead
From: Like Xu
For PC target, users could configure the number of dies per one package
via command line with this patch, such as "-smp dies=2,cores=4".
The parsing rules of new cpu-topology model obey the same restrictions/logic
as the legacy socket/core/thread model especially on missing values
From: Like Xu
The die-level as the first PC-specific cpu topology is added to the leagcy
cpu topology model, which has one die per package implicitly and only the
numbers of sockets/cores/threads are configurable.
In the new model with die-level support, the total number of logical
processors
From: Like Xu
The global smp variables in riscv are replaced with smp machine properties.
A local variable of the same name would be introduced in the declaration
phase if it's used widely in the context OR replace it on the spot if it's
only used once. No semantic changes.
Signed-off-by: Like
From: Like Xu
The global smp variables in arm are replaced with smp machine properties.
The init_cpus() and *_create_rpu() are refactored to pass MachineState.
A local variable of the same name would be introduced in the declaration
phase if it's used widely in the context OR replace it on the
From: Igor Mammedov
The parameter allows to configure fake NUMA topology where guest
VM simulates NUMA topology but not actually getting performance
benefits from it. The same or better results could be achieved
using 'memdev' parameter.
Beside of unpredictable performance, '-numa node.mem'
From: Like Xu
The global smp variables in ppc are replaced with smp machine properties.
A local variable of the same name would be introduced in the declaration
phase if it's used widely in the context OR replace it on the spot if it's
only used once. No semantic changes.
Signed-off-by: Like
From: Like Xu
Basically, the context could get the MachineState reference via call
chains or unrecommended qdev_get_machine() in !CONFIG_USER_ONLY mode.
A local variable of the same name would be introduced in the declaration
phase out of less effort OR replace it on the spot if it's only used
From: Like Xu
The global smp variables in alpha/hppa/mips/openrisc/sparc*/xtensa codes
are replaced with smp properties from MachineState.
A local variable of the same name would be introduced in the declaration
phase if it's used widely in the context OR replace it on the spot if it's
only
From: Like Xu
To support multiple dies configuration on PCMachine, the best place to
set CPUX86State->nr_dies with requested PCMachineState->smp_dies is in
pc_new_cpu() and pc_cpu_pre_plug(). Refactoring pc_new_cpu() is applied
and redundant parameter "const char *typename" would be removed.
The following changes since commit 474f3938d79ab36b9231c9ad3b5a9314c2aeacde:
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-21-2019'
into staging (2019-06-21 15:40:50 +0100)
are available in the Git repository at:
git://github.com/ehabkost/qemu.git
From: Like Xu
To get rid of the global smp_* variables we're currently using, it's recommended
to pass MachineState in the list of incoming parameters for functions that use
global smp variables, thus some redundant parameters are dropped. It's applied
for legacy smbios_*(), *_machine_reset(),
From: Like Xu
The cpu topology property CpuTopology is added to the MachineState
and its members are initialized with the leagcy global smp variables.
>From this commit, the code in the system emulation mode is supposed to
use cpu topology variables from MachineState instead of the global ones
Add new version of Cascadelake-Server CPU model, setting
stepping=5 and enabling the IA32_ARCH_CAPABILITIES MSR
with some flags.
The new feature will introduce a new host software requirement,
breaking our CPU model runnability promises. This means we can't
enable the new CPU model version by
This will make unversioned CPU models behavior depend on the
machine type:
* "pc-*-4.0" and older will not report them as aliases.
This is done to keep compatibility with older QEMU versions
after management software starts translating aliases.
* "pc-*-4.1" will translate unversioned CPU
The old CPU models will be just aliases for specific versions of
the original CPU models.
Signed-off-by: Eduardo Habkost
---
(New patch, added to series in v2)
---
target/i386/cpu.c | 601 ++
1 file changed, 21 insertions(+), 580 deletions(-)
diff
Document that CPU model runnability guarantees won't apply to
unversioned CPU models anymore.
Signed-off-by: Eduardo Habkost
---
Changes v1 -> v2:
* (none)
Cc: libvir-l...@redhat.com
---
qemu-deprecated.texi | 19 +++
1 file changed, 19 insertions(+)
diff --git
Add support for registration of multiple versions of CPU models.
The existing CPU models will be registered with a "-v1" suffix.
The -noTSX, -IBRS, and -IBPB CPU model variants will become
versions of the original models in a separate patch, so
make sure we register no versions for them.
Add versions of CPU models that are equivalent to their -IBRS,
-noTSX and -IBRS variants.
The separate variants will eventually be removed and become
aliases for these CPU versions.
Signed-off-by: Eduardo Habkost
---
(New patch, added to series in v2)
---
target/i386/cpu.c | 186
Add a new option that can be used to disable feature flag
filtering. This will allow CPU model compatibility test cases to
work without host hardware dependencies.
Signed-off-by: Eduardo Habkost
---
Changes v1 -> v2:
* (none)
---
target/i386/cpu.h | 6 ++
target/i386/cpu.c | 8 ++--
2
Management software will be expected to resolve CPU model name
aliases using the new field.
Signed-off-by: Eduardo Habkost
---
Changes v1 -> v2:
* (none)
Cc: Eric Blake
Cc: Markus Armbruster
---
qapi/target.json | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git
When introducing versioned CPU models, the string at
X86CPUDefinition::model_id might not be the model-id we'll really
use. Instantiate a CPU object and check the model-id property on
"-cpu help"
Signed-off-by: Eduardo Habkost
---
(New patch, added to series in v2)
---
target/i386/cpu.c | 16
Changes v1 -> v2:
* Patch "i386: Infrastructure for versioned CPU models" was
rewritten and split in two:
* i386: Register versioned CPU models
* i386: Make unversioned CPU models be aliases
* -IBRS, -noTSX, -IBPB CPU models are now aliases
* Enable rdctl-no, ibrs-all, skip-l1dfl-vmentry in
On Thu, Jun 27, 2019 at 07:09:39PM +0200, Richard Henderson wrote:
> On 6/27/19 3:22 PM, Lucien Anti-Spam wrote:
> > Hi Laurent / Richard,
> > (resent email )
> >
> > Does anyone have any knowledge why
> > gen_exception(s, s->base.pc_next, EXCP_RTE);
> >
> > is generated for "RTE"
On 6/17/19 7:37 AM, Vladimir Sementsov-Ogievskiy wrote:
> 08.06.2019 1:26, John Snow wrote:
>>
>>
>> On 6/3/19 8:00 AM, Vladimir Sementsov-Ogievskiy wrote:
>>> Hi all!
>>>
>>> Here is block-dirty-bitmap-remove transaction action.
>>>
>>> It is used to do transactional movement of the bitmap
On Thu, Jun 27, 2019 at 3:45 PM John Snow wrote:
>
>
>
> On 6/27/19 3:43 PM, Jason Dillaman wrote:
> > On Thu, Jun 27, 2019 at 1:24 PM John Snow wrote:
> >>
> >>
> >>
> >> On 6/27/19 4:48 AM, Stefano Garzarella wrote:
> >>> On Wed, Jun 26, 2019 at 05:04:25PM -0400, John Snow wrote:
> It
unittest-style tests generally do not use the log file, but VM.run_job()
can still be useful to them. Add a parameter to it that hides its
output from the log file.
Signed-off-by: Max Reitz
---
tests/qemu-iotests/iotests.py | 18 +-
1 file changed, 13 insertions(+), 5
Currently, TestParallelOps in 030 creates images that are too small for
job throttling to be effective. This is reflected by the fact that it
never undoes the throttling.
Increase the image size and undo the throttling when the job should be
completed. Also, add throttling in
We recently removed the dependency of the stream job on its base node.
That makes it OK to use a commit filter node there. Test that.
Signed-off-by: Max Reitz
---
tests/qemu-iotests/030 | 25 +
tests/qemu-iotests/030.out | 4 ++--
2 files changed, 27 insertions(+),
As it is, this series depends on my block branch, most importantly
Andrey’s series “block/stream: get rid of the base”.
Depends-on: <1559152576-281803-1-git-send-email-andrey.shinkev...@virtuozzo.com>
This series made the problem apparent to me, but it existed before:
Namely, the commit and
Currently, 030 just compares the error class, which does not say
anything.
Before HEAD^ added throttling to test_overlapping_4, that test actually
usually failed because node2 was already gone, not because it was the
commit and stream job were not allowed to overlap.
Prevent such problems in the
The commit and the mirror block job must be able to drop their filter
node at any point. However, this will not be possible if any of the
BdrvChild links to them is frozen. Therefore, we need to prevent them
from ever becoming frozen.
Signed-off-by: Max Reitz
---
include/block/block_int.h | 3
On 27.06.2019 13:01, Philippe Mathieu-Daudé wrote:
> +bios_url = ('ftp://ftp.boulder.ibm.com/rs6000/firmware/'
> +'7020-40p/P12H0456.IMG')
> +bios_hash = '1775face4e6dc27f3a6ed955ef6eb331bf817f03'
> +bios_path = self.fetch_asset(bios_url,
Hi Phil,
Thanks for pushing this forward! I'll try to get to the rest of these early
next week.
> On Jun 27, 2019, at 16:26, Philippe Mathieu-Daudé wrote:
>
> Call the read() trace function after the value is set, so we can
> log the returned value.
> Rename the I/O trace functions with
It's not obvious that something named __init__.py actually houses
important code that isn't relevant to python packaging glue. Move the
QEMUMachine and related error classes out into their own module.
Adjust users to the new import location.
Signed-off-by: John Snow
---
python/qemu/__init__.py
Since we're out in a new module, do a quick cursory pass of some of the
more obvious style issues.
Signed-off-by: John Snow
---
python/qemu/machine.py | 33 ++---
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/python/qemu/machine.py
I didn't actually mean to retain the RFC tag, but oh well.
On 6/27/19 5:28 PM, John Snow wrote:
> There's a lot of code hiding in what is ostensibly a package
> configuration file. Let's break that out into something more visible.
>
> V2:
> - Retain python 2.7+ compatibility :(
> - Refactor
We do need to run cleanup, but we should re-raise the error.
Rename _post_shutdown to _shutdown_cleanup, then use the
_post_shutdown name for the routine that will always run
at the conclusion of the shutdown() method.
Signed-off-by: John Snow
---
python/qemu/machine.py | 41
There's a lot of code hiding in what is ostensibly a package
configuration file. Let's break that out into something more visible.
V2:
- Retain python 2.7+ compatibility :(
- Refactor shutdown a little more aggressively
John Snow (3):
python/qemu: split QEMUMachine out from underneath
From: Stephen Checkoway
When erasing the chip, use the typical time specified in the CFI table
rather than arbitrarily selecting 5 seconds.
Since the currently unconfigurable value set in the table is 12, this
means a chip erase takes 4096 ms so this isn't a big change in behavior.
On 06/21/2019 07:07 PM, Cleber Rosa wrote:
On Fri, Jun 21, 2019 at 11:38:06AM -0400, Wainer dos Santos Moschetta wrote:
Hi all,
I'm still unsure this is the best solution. I tend to think that
any arch-independent test case (i.e. not tagged 'arch') should
be skipped on all arches except for
From: Stephen Checkoway
After a flash device enters CFI mode from autoselect mode, the reset
command returns the device to autoselect mode. An additional reset
command is necessary to return to read array mode.
Signed-off-by: Stephen Checkoway
Acked-by: Thomas Huth
Message-Id:
From: Stephen Checkoway
When the flash device is performing a chip erase, all commands are
ignored. When it is performing a sector erase, only the erase suspend
command is valid, which is currently not supported.
In particular, the reset command should not cause the device to reset to
read
From: Stephen Checkoway
After two unlock cycles and a sector erase command, the AMD flash chips
start a 50 us erase time out. Any additional sector erase commands add a
sector to be erased and restart the 50 us timeout. During the timeout,
status bit DQ3 is cleared. After the time out, DQ3 is
We can directly use pfl->total_len, remove the local 'chip_len'
variable.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-6-stephen.checko...@oberlin.edu>
[PMD: Extracted from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 14 ++
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 40 +++-
1 file changed, 19 insertions(+), 21 deletions(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index e9519cbae8..db9dc7d8fb 100644
--- a/hw/block/pflash_cfi02.c
+++
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-5-stephen.checko...@oberlin.edu>
[PMD: Extracted from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
---
TODO: Why? To respect the datasheet? Which model is this?
---
hw/block/pflash_cfi02.c | 4 ++--
1 file changed, 2
The 'page mode' feature entry was implicitly set as zero
(not supported). Document it exists, so we won't discard
it if we squeeze the CFI table.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-6-stephen.checko...@oberlin.edu>
[PMD: Extracted from bigger patch]
Signed-off-by:
Parallel NOR flashes are limited to 16-bit bus accesses.
Remove the 32-bit dead code.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index
The load/store API eases code review.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch, simplified tracing]
Signed-off-by: Philippe
Extract the pflash_regions_count() function, the code will be
easier to review.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-6-stephen.checko...@oberlin.edu>
[PMD: Extracted from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git
From: Stephen Checkoway
During a sector erase (but not a chip erase), the embeded erase program
can be suspended. Once suspended, the sectors not selected for erasure
may be read and programmed. Autoselect mode is allowed during erase
suspend mode. Presumably, CFI queries are similarly allowed
Introduce the FlashConfig structure, to be able to run the same set
of tests on different flash models/configurations.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-6-stephen.checko...@oberlin.edu>
[PMD: Extracted from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
---
Pull out all of the code to modify the status into simple helper
functions. Status handling becomes more complex once multiple
chips are interleaved to produce a single device.
No change in functionality is intended with this commit.
Signed-off-by: Stephen Checkoway
Message-Id:
Extract the code block in a new function, remove a goto statement.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch, remove the XXX tracing
The load/store API eases code review.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
---
Split the if() condition check and arrange the indentation to
ease the review of the next patches. No logical change.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/block/pflash_cfi02.c
No change in functionality is intended with this commit.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch]
Signed-off-by: Philippe
From: Stephen Checkoway
Most AMD commands only examine 11 bits of the address. This masks the
addresses used in the comparison to 11 bits. The exceptions are word or
sector addresses which use offset directly rather than the shifted
offset, boff.
Signed-off-by: Stephen Checkoway
Acked-by:
From: Stephen Checkoway
Some flash chips support sectors of different sizes. For example, the
AMD AM29LV160DT has 31 64 kB sectors, one 32 kB sector, two 8 kB
sectors, and a 16 kB sector, in that order. The AM29LV160DB has those in
the reverse order.
The `num-blocks` and `sector-length`
The pflash_read()/pflash_write() can check the device endianess
via the pfl->be variable, so remove the 'int be' argument.
Since the big/little MemoryRegionOps are now identical, it is
pointless to declare them both. Unify them.
Signed-off-by: Stephen Checkoway
Message-Id:
Call the read() trace function after the value is set, so we can
log the returned value.
Rename the I/O trace functions with '_io_' in their name.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi01.c | 5 +++--
hw/block/pflash_cfi02.c | 6 ++
hw/block/trace-events | 4 ++--
3
Always compile the debug code to prevent format string to bitrot.
Delete dead code.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch, use
Manufacturers are allowed to move the PRI table, this is why the
offset is queryable via fixed offsets 0x15/0x16.
Add a variable to hold the offset, so it will be easier to later
move the PRI table.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 31
From: Stephen Checkoway
Test the AMD command set for parallel flash chips. This test uses an
ARM musicpal board with a pflash drive to test the following list of
currently-supported commands.
- Autoselect
- CFI
- Sector erase
- Chip erase
- Program
- Unlock bypass
- Reset
Signed-off-by: Stephen
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 6 +++---
1 file
Use a field width format to have a single function to log
the different width accesses.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi01.c | 6 ++
hw/block/pflash_cfi02.c | 6 ++
hw/block/trace-events | 6 ++
3 files changed, 6 insertions(+), 12 deletions(-)
diff
Hi,
This series is based on Stephen Checkoway work (v4):
https://lists.gnu.org/archive/html/qemu-devel/2019-04/msg04595.html
Stephen work is a great improvement of the actual code, however
while reviewing his patches, I found them quite dense, so I started
to split each logical change to be able
On Thu, Jun 27, 2019 at 12:56 PM Stefan Brankovic <
stefan.branko...@rt-rk.com> wrote:
>
> V4:
>
> Addressed Richard's Henderson's suggestions.
> Removed vpkpx's optimization for further investigation on graphical
> distortions
> it caused on OSX 10.2-4 guests.
> Added opcodes for vector
On Wed, Jun 26, 2019 at 1:25 AM Palmer Dabbelt wrote:
>
> On Tue, 25 Jun 2019 23:58:34 PDT (-0700), bmeng...@gmail.com wrote:
> > On Wed, Jun 26, 2019 at 4:23 AM Jonathan Behrens wrote:
> >>
> >> I just did some testing on a HiFive Unleashed board and can confirm what
> >> you are saying. The
On 6/27/19 3:43 PM, Jason Dillaman wrote:
> On Thu, Jun 27, 2019 at 1:24 PM John Snow wrote:
>>
>>
>>
>> On 6/27/19 4:48 AM, Stefano Garzarella wrote:
>>> On Wed, Jun 26, 2019 at 05:04:25PM -0400, John Snow wrote:
It looks like this has hit a 30 day expiration without any reviews or
On Thu, Jun 27, 2019 at 1:24 PM John Snow wrote:
>
>
>
> On 6/27/19 4:48 AM, Stefano Garzarella wrote:
> > On Wed, Jun 26, 2019 at 05:04:25PM -0400, John Snow wrote:
> >> It looks like this has hit a 30 day expiration without any reviews or
> >> being merged; do we still want this? If so, can you
On 06/24/2019 05:37 AM, Andrea Bolognani wrote:
On Sat, 2019-06-22 at 16:58 +0100, Peter Maydell wrote:
On Fri, 21 Jun 2019 at 20:04, Cleber Rosa wrote:
You can consider me biased (I do consider myself), but trying to wear
the hat of a user first interacting with QEMU, I would expect a
Patchew URL:
https://patchew.org/QEMU/1561648298-18100-1-git-send-email-aleksandar.marko...@rt-rk.com/
Hi,
This series failed build test on s390x host. Please find the details below.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invoked under the git checkout with
# HEAD
Patchew URL:
https://patchew.org/QEMU/1561649510-21183-1-git-send-email-aleksandar.marko...@rt-rk.com/
Hi,
This series failed build test on s390x host. Please find the details below.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invoked under the git checkout with
# HEAD
I meant that if I take the proposed code it fails in the mentioned way
Sent from my cell phone, please ignore typos
On Thu, Jun 27, 2019, 7:02 PM Michael Rolnik wrote:
> Hi Igor,
>
> if I run `make check` it fails with
> qemu-system-rx: unable to find CPU model 'rx62n'
> or
> qemu-system-avr:
Patchew URL: https://patchew.org/QEMU/20190627131252.ga14...@olga.proxmox.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190627131252.ga14...@olga.proxmox.com
Subject: [Qemu-devel] balloon config change seems to
Patchew URL:
https://patchew.org/QEMU/1561648298-18100-1-git-send-email-aleksandar.marko...@rt-rk.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v13 0/5] linux-user: A set of miscellaneous patches
Message-id:
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