Re: [Qemu-devel] [PULL 1/6] i2c: Move bitbang_i2c.h to include/hw/i2c/

2019-06-28 Thread David Gibson
On Fri, Jun 28, 2019 at 12:39:52PM +0200, Gerd Hoffmann wrote: > From: BALATON Zoltan > > The bitbang i2c implementation is also useful for other device models > such as DDC in display controllers. Move the header to include/hw/i2c/ > to allow it to be used from other device models and adjust

Re: [Qemu-devel] [QEMU-PPC] [PATCH 1/2] ppc/spapr: Add implementation of hcall H_PURR

2019-06-28 Thread David Gibson
On Mon, Jun 24, 2019 at 03:58:11PM +1000, Suraj Jitindar Singh wrote: > The hcall H_PURR is used by a guest to read the PURR (processor > utilisation of resources register). A guest expects that this register > will count at a rate of timebase scaled by the number of guest vcpus > present in the

Re: [Qemu-devel] [PATCH v16 1/5] linux-user: Add support for translation of statx() syscall

2019-06-28 Thread Jim Wilson
On Fri, Jun 28, 2019 at 5:53 PM Aleksandar Markovic wrote: > This patch went trough several transformations in last few days, and I am a > little worried that we forgot the primary reasons/scenarios why want it in > the first place. In that light, may I ask you to recheck this latest version >

Re: [Qemu-devel] [PATCH v16 1/5] linux-user: Add support for translation of statx() syscall

2019-06-28 Thread Aleksandar Markovic
Hello, Jim. On Jun 28, 2019 12:51 PM, "Aleksandar Markovic" < aleksandar.marko...@rt-rk.com> wrote: > > From: Aleksandar Rikalo > > Implement support for translation of system call statx(). > This patch went trough several transformations in last few days, and I am a little worried that we

Re: [Qemu-devel] [PATCH v2 07/14] target/arm/cpu64: max cpu: Introduce sve properties

2019-06-28 Thread Richard Henderson
On 6/28/19 9:27 AM, Andrew Jones wrote: > Also, while it's true we can always > get the max vq with next-smaller(ARM_MAX_VQ + 1), having it cached in > cpu->sve_max_vq is convenient. That said, I think we'd rather keep it. When is it convenient, and for what? Certainly the only thing that we

Re: [Qemu-devel] patch to swap SIGRTMIN + 1 and SIGRTMAX - 1

2019-06-28 Thread Marlies Ruck
Hi, I just wanted to follow up since I sent this patch a week ago to make sure it was a received. An ack would be appreciated. Thanks, Marli On Fri, Jun 21, 2019 at 3:58 PM Marlies Ruck wrote: > Hi, > > Attached is a patch to let guest programs use SIGRTMIN + 1 by swapping > with SIGRTMAX -

Re: [Qemu-devel] [PATCH] fixup! hw/s390x: Replace global smp variables with machine smp properties

2019-06-28 Thread no-reply
Patchew URL: https://patchew.org/QEMU/20190628183321.ge1...@habkost.net/ Hi, This series failed build test on s390x host. Please find the details below. === TEST SCRIPT BEGIN === #!/bin/bash # Testing script will be invoked under the git checkout with # HEAD pointing to a commit that has the

Re: [Qemu-devel] [PATCH v5 28/28] hw/block/pflash_cfi02: Reduce I/O accesses to 16-bit

2019-06-28 Thread Alistair Francis
On Thu, Jun 27, 2019 at 1:55 PM Philippe Mathieu-Daudé wrote: > > Parallel NOR flashes are limited to 16-bit bus accesses. > Remove the 32-bit dead code. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Alistair > --- > hw/block/pflash_cfi02.c | 5 + > 1 file

Re: [Qemu-devel] [PATCH v5 27/28] hw/block/pflash_cfi02: Document commands

2019-06-28 Thread Alistair Francis
On Thu, Jun 27, 2019 at 1:58 PM Philippe Mathieu-Daudé wrote: > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Alistair > --- > hw/block/pflash_cfi02.c | 40 +++- > 1 file changed, 19 insertions(+), 21 deletions(-) > > diff --git

Re: [Qemu-devel] [PATCH v5 25/28] hw/block/pflash_cfi02: Use chip erase time specified in the CFI table

2019-06-28 Thread Alistair Francis
On Thu, Jun 27, 2019 at 2:12 PM Philippe Mathieu-Daudé wrote: > > From: Stephen Checkoway > > When erasing the chip, use the typical time specified in the CFI table > rather than arbitrarily selecting 5 seconds. > > Since the currently unconfigurable value set in the table is 12, this > means a

Re: [Qemu-devel] [PATCH v5 22/28] hw/block/pflash_cfi02: Fix reset command not ignored during erase

2019-06-28 Thread Alistair Francis
On Thu, Jun 27, 2019 at 2:06 PM Philippe Mathieu-Daudé wrote: > > From: Stephen Checkoway > > When the flash device is performing a chip erase, all commands are > ignored. When it is performing a sector erase, only the erase suspend > command is valid, which is currently not supported. > > In

Re: [Qemu-devel] [PATCH v5 21/28] hw/block/pflash_cfi02: Fix CFI in autoselect mode

2019-06-28 Thread Alistair Francis
On Thu, Jun 27, 2019 at 2:09 PM Philippe Mathieu-Daudé wrote: > > From: Stephen Checkoway > > After a flash device enters CFI mode from autoselect mode, the reset > command returns the device to autoselect mode. An additional reset > command is necessary to return to read array mode. > >

Re: [Qemu-devel] [PATCH v5 20/28] hw/block/pflash_cfi02: Split if() condition

2019-06-28 Thread Alistair Francis
On Thu, Jun 27, 2019 at 1:44 PM Philippe Mathieu-Daudé wrote: > > Split the if() condition check and arrange the indentation to > ease the review of the next patches. No logical change. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Alistair > --- >

Re: [Qemu-devel] [PATCH 1/3] migration/postcopy: the valid condition is one less then end

2019-06-28 Thread Wei Yang
On Fri, Jun 28, 2019 at 04:09:50PM +0100, Dr. David Alan Gilbert wrote: >* Wei Yang (richardw.y...@linux.intel.com) wrote: >> If one equals end, it means we have gone through the whole bitmap. >> >> Use a more restrict check to skip a unnecessary condition. >> >> Signed-off-by: Wei Yang > >Yes,

Re: [Qemu-devel] [PATCH 4/4] hw/i386: Introduce the microvm machine type

2019-06-28 Thread Sergio Lopez
Maran Wilson writes: > On 6/28/2019 2:05 PM, Sergio Lopez wrote: >> Maran Wilson writes: >> >>> This seems like a good overall direction to be headed with Qemu. >>> >>> But there is a lot of Linux OS specific startup details being baked >>> into the Qemu machine type here. Things that are

Re: [Qemu-devel] [PATCH v1 1/1] hw/scsi: Report errors and sense to guests through scsi-block

2019-06-28 Thread Alistair Francis
On Fri, Jun 28, 2019 at 3:14 PM Paolo Bonzini wrote: > > On 28/06/19 23:57, Alistair Francis wrote: > > > > I tried to run my VM with option "-drive > > ...,rerror=report,werror=report" as he noted, but the eternal loop > > symptom still happens when host block-scsi device returns EIO. Then I > >

[Qemu-devel] [PATCH v5] memory: do not notify for non inclusive overlap entry

2019-06-28 Thread Yan Zhao
if an entry has non inclusive overlap with the notifier, print warning message and do not do notification for it. Out of scope mapping/unmapping would cause problem, as in below case: 1. initially there are two notifiers with ranges 0-0xfedf, 0xfef0-0x, IOVAs from

Re: [Qemu-devel] [PATCH 4/4] hw/i386: Introduce the microvm machine type

2019-06-28 Thread Paolo Bonzini
On 28/06/19 16:06, Michael S. Tsirkin wrote: >> +assert(kvm_irqchip_in_kernel()); > Hmm - irqchip in kernel actually increases the attack surface, > does it not? Or at least, the severity of the attacks. Yeah, we should at least support split irqchip. But, irqchip completely in userspace is

Re: [Qemu-devel] [PATCH v1 1/1] hw/scsi: Report errors and sense to guests through scsi-block

2019-06-28 Thread Paolo Bonzini
On 28/06/19 23:57, Alistair Francis wrote: > > I tried to run my VM with option "-drive > ...,rerror=report,werror=report" as he noted, but the eternal loop > symptom still happens when host block-scsi device returns EIO. Then I > believe EIO should be added to the report target error list. What

Re: [Qemu-devel] [PATCH] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren

2019-06-28 Thread Alistair Francis
On Fri, Jun 28, 2019 at 2:20 PM Jonathan Behrens wrote: > > > Can you wrap your commit message at ~70 lines? > > Sure. > > > Isn't CSR_TIME & 31 just 0? Can this just be changed 1 << 1 or even better > > add a macro? > > Any of those options work. Unless anyone feels strongly otherwise, I'll add

Re: [Qemu-devel] [PATCH v1 1/1] hw/scsi: Report errors and sense to guests through scsi-block

2019-06-28 Thread Alistair Francis
On Thu, Jun 27, 2019 at 2:01 AM Paolo Bonzini wrote: > > On 27/06/19 00:46, Alistair Francis wrote: > > From: Shin'ichiro Kawasaki > > > > When host block devices are bridged to a guest system through > > virtio-scsi-pci and scsi-block driver, scsi_handle_rw_error() in > > hw/scsi/scsi-disk.c

Re: [Qemu-devel] [PATCH 4/4] hw/i386: Introduce the microvm machine type

2019-06-28 Thread Paolo Bonzini
On 28/06/19 23:42, Sergio Lopez wrote: > I though it could be a good idea to have versioning already in place, in > case we need it in the future. But, perhaps we can do a simple machine > definition and just add versioning when it's really needed? > I think if the use case is really short-lived

Re: [Qemu-devel] [PATCH 4/4] hw/i386: Introduce the microvm machine type

2019-06-28 Thread Paolo Bonzini
On 28/06/19 23:05, Sergio Lopez wrote: > The main reason for relying on Linux's Zero Page, is to be able to > pass the e820 table with the basic physical memory layout to the kernel > through it, as there isn't a BIOS nor ACPI. AFAIK, we can't do that with > PVH. e820 is passed through both PVH

Re: [Qemu-devel] [PATCH 4/4] hw/i386: Introduce the microvm machine type

2019-06-28 Thread Maran Wilson
On 6/28/2019 2:05 PM, Sergio Lopez wrote: Maran Wilson writes: This seems like a good overall direction to be headed with Qemu. But there is a lot of Linux OS specific startup details being baked into the Qemu machine type here. Things that are usually pushed into firmware or option ROM.

Re: [Qemu-devel] [PATCH 1/4] hw/i386: Factorize CPU routine

2019-06-28 Thread Sergio Lopez
Eduardo Habkost writes: > On Fri, Jun 28, 2019 at 01:53:46PM +0200, Sergio Lopez wrote: > [...] >> /* Enables contiguous-apic-ID mode, for compatibility */ >> -static bool compat_apic_id_mode; >> +bool compat_apic_id_mode; > > We can get rid of this global variable, see the patch I have just >

Re: [Qemu-devel] [PATCH 4/4] hw/i386: Introduce the microvm machine type

2019-06-28 Thread Sergio Lopez
Eduardo Habkost writes: > Hi, > > This looks good, overall, I'm just confused by the versioning > system. Comments below: > > > On Fri, Jun 28, 2019 at 01:53:49PM +0200, Sergio Lopez wrote: >> Microvm is a machine type inspired by both NEMU and Firecracker, and >> constructed after the machine

Re: [Qemu-devel] [PATCH v4 00/13] Add migration support for VFIO device

2019-06-28 Thread Yan Zhao
On Fri, Jun 28, 2019 at 05:44:47PM +0800, Dr. David Alan Gilbert wrote: > * Yan Zhao (yan.y.z...@intel.com) wrote: > > On Tue, Jun 25, 2019 at 03:00:24AM +0800, Dr. David Alan Gilbert wrote: > > > * Kirti Wankhede (kwankh...@nvidia.com) wrote: > > > > > > > > > > > > On 6/21/2019 2:16 PM, Yan

Re: [Qemu-devel] [PATCH v4 08/13] vfio: Add save state functions to SaveVMHandlers

2019-06-28 Thread Yan Zhao
On Fri, Jun 28, 2019 at 04:50:30PM +0800, Dr. David Alan Gilbert wrote: > * Yan Zhao (yan.y.z...@intel.com) wrote: > > On Fri, Jun 21, 2019 at 08:31:53AM +0800, Yan Zhao wrote: > > > On Thu, Jun 20, 2019 at 10:37:36PM +0800, Kirti Wankhede wrote: > > > > Added .save_live_pending,

Re: [Qemu-devel] [PATCH] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren

2019-06-28 Thread Jonathan Behrens
> Can you wrap your commit message at ~70 lines? Sure. > Isn't CSR_TIME & 31 just 0? Can this just be changed 1 << 1 or even better add a macro? Any of those options work. Unless anyone feels strongly otherwise, I'll add macros for the bits associated with the three named counters but not the

Re: [Qemu-devel] [PATCH 4/4] hw/i386: Introduce the microvm machine type

2019-06-28 Thread Sergio Lopez
Maran Wilson writes: > This seems like a good overall direction to be headed with Qemu. > > But there is a lot of Linux OS specific startup details being baked > into the Qemu machine type here. Things that are usually pushed into > firmware or option ROM. > > Instead of hard coding all the

Re: [Qemu-devel] [PATCH] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren

2019-06-28 Thread Alistair Francis
On Fri, Jun 28, 2019 at 1:12 PM wrote: > > From: Jonathan Behrens > > QEMU currently always triggers an illegal instruction exception when code > attempts to read the time CSR. This is valid behavor, but only if the TM bit > in > mcounteren is hardwired to zero. This change also corrects

Re: [Qemu-devel] [PATCH 4/4] hw/i386: Introduce the microvm machine type

2019-06-28 Thread Sergio Lopez
Michael S. Tsirkin writes: > On Fri, Jun 28, 2019 at 01:53:49PM +0200, Sergio Lopez wrote: >> Microvm is a machine type inspired by both NEMU and Firecracker, and >> constructed after the machine model implemented by the latter. >> >> It's main purpose is providing users a KVM-only machine

Re: [Qemu-devel] [PATCH 2/2] Acceptance tests: add SPICE protocol check

2019-06-28 Thread Wainer dos Santos Moschetta
On 06/21/2019 03:09 AM, Cleber Rosa wrote: This fires a QEMU binary with SPICE enabled, and does a basic handshake, doing a basic client/server interaction and protocol validation. Signed-off-by: Cleber Rosa --- .travis.yml | 5 +++- tests/Makefile.include| 6 +

Re: [Qemu-devel] [PATCH v3 19/50] tcg: let plugins instrument memory accesses

2019-06-28 Thread Alex Bennée
Aaron Lindsay OS writes: > On Jun 28 18:11, Alex Bennée wrote: >> Aaron Lindsay OS writes: >> > On Jun 14 18:11, Alex Bennée wrote: >> >> From: "Emilio G. Cota" >> >> >> >> Here the trickiest feature is passing the host address to >> >> memory callbacks that request it. Perhaps it would be

Re: [Qemu-devel] [PATCH 2/4] hw/virtio: Factorize virtio-mmio headers

2019-06-28 Thread Sergio Lopez
Michael S. Tsirkin writes: > On Fri, Jun 28, 2019 at 01:53:47PM +0200, Sergio Lopez wrote: >> Put QOM and main struct definition in a separate header file, so it >> can be accesed from other components. >> >> This is needed for the microvm machine type implementation. >> >> Signed-off-by:

Re: [Qemu-devel] [PATCH 0/4] Introduce the microvm machine type

2019-06-28 Thread Sergio Lopez
Paolo Bonzini writes: > On 28/06/19 13:53, Sergio Lopez wrote: >> qemu-system-x86_64 -M microvm,legacy -m 512m -smp 2 \ >> -kernel vmlinux -append "console=ttyS0 root=/dev/vda" \ >> -nodefaults -no-user-config \ >> -drive id=test,file=test.img,format=raw,if=none \ >> -device

Re: [Qemu-devel] [PATCH 1/2] Acceptance tests: exclude "flaky" tests

2019-06-28 Thread Wainer dos Santos Moschetta
On 06/21/2019 11:38 AM, Cleber Rosa wrote: On Fri, Jun 21, 2019 at 09:03:33AM +0200, Philippe Mathieu-Daudé wrote: On 6/21/19 8:09 AM, Cleber Rosa wrote: It's a fact that some tests may not be 100% reliable in all environments. While it's a tough call to remove a useful test that from the

Re: [Qemu-devel] [PATCH 3/3] tests/acceptance: Add boot linux with kvm test

2019-06-28 Thread Eduardo Habkost
On Fri, Jun 28, 2019 at 11:02:17AM -0400, Wainer dos Santos Moschetta wrote: > Until now the suite of acceptance tests doesn't exercise > QEMU with kvm enabled. So this introduces a simple test > that boots the Linux kernel and checks it boots on the > accelerator correctly. > > Signed-off-by:

Re: [Qemu-devel] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren

2019-06-28 Thread Jonathan Behrens
> Taking a patch that matches the out-of-spec FU540 behavior doesn't make any > sense, I don't want to implement errata in QEMU :) QEMU actually currently matches the out of spec behavior of the FU540, I just sent out a patch to fix this. Jonathan On Fri, Jun 28, 2019 at 2:26 PM Alistair

[Qemu-devel] [PATCH] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren

2019-06-28 Thread jonathan
From: Jonathan Behrens QEMU currently always triggers an illegal instruction exception when code attempts to read the time CSR. This is valid behavor, but only if the TM bit in mcounteren is hardwired to zero. This change also corrects mcounteren and scounteren CSRs to be 32-bits on both 32-bit

Re: [Qemu-devel] [PATCH 1/4] hw/i386: Factorize CPU routine

2019-06-28 Thread Eduardo Habkost
On Fri, Jun 28, 2019 at 01:53:46PM +0200, Sergio Lopez wrote: [...] > /* Enables contiguous-apic-ID mode, for compatibility */ > -static bool compat_apic_id_mode; > +bool compat_apic_id_mode; We can get rid of this global variable, see the patch I have just sent: [PATCH] pc: Move

[Qemu-devel] [PATCH] pc: Move compat_apic_id_mode variable to PCMachineClass

2019-06-28 Thread Eduardo Habkost
Replace the static variable with a PCMachineClass field. This will help us eventually get rid of the pc_compat_*() init functions. Signed-off-by: Eduardo Habkost --- include/hw/i386/pc.h | 3 +++ hw/i386/pc.c | 22 +- hw/i386/pc_piix.c| 3 ++- 3 files changed,

Re: [Qemu-devel] [PATCH 4/4] hw/i386: Introduce the microvm machine type

2019-06-28 Thread Eduardo Habkost
Hi, This looks good, overall, I'm just confused by the versioning system. Comments below: On Fri, Jun 28, 2019 at 01:53:49PM +0200, Sergio Lopez wrote: > Microvm is a machine type inspired by both NEMU and Firecracker, and > constructed after the machine model implemented by the latter. > >

[Qemu-devel] [PATCH v4 3/4] crypto.c: cleanup created file when block_crypto_co_create_opts_luks fails

2019-06-28 Thread Daniel Henrique Barboza
When using a non-UTF8 secret to create a volume using qemu-img, the following error happens: $ qemu-img create -f luks --object secret,id=vol_1_encrypt0,file=vol_resize_pool.vol_1.secret.qzVQrI -o key-secret=vol_1_encrypt0 /var/tmp/pool_target/vol_1 10240K Formatting

[Qemu-devel] [PATCH v4 4/4] qemu-iotests: adding LUKS cleanup for non-UTF8 secret error

2019-06-28 Thread Daniel Henrique Barboza
This patch adds a new test file, 257, to exercise the case where qemu-img fails to complete for the LUKS format when a non-UTF8 secret is used. If using an existing image file, do not erase it. If the file was created by the failed qemu-img call, clean it up. Signed-off-by: Daniel Henrique

[Qemu-devel] [PATCH v4 0/4] delete created files when block_crypto_co_create_opts_luks fails

2019-06-28 Thread Daniel Henrique Barboza
Changes from previous version [1]: - added an extra patch including a new qemu-iotest to exercise the fix [1] https://lists.gnu.org/archive/html/qemu-devel/2019-03/msg07159.html Daniel Henrique Barboza (4): block: introducing 'bdrv_co_delete_file' interface block.c: adding bdrv_delete_file

[Qemu-devel] [PATCH v4 1/4] block: introducing 'bdrv_co_delete_file' interface

2019-06-28 Thread Daniel Henrique Barboza
Adding to Block Drivers the capability of being able to clean up its created files can be useful in certain situations. For the LUKS driver, for instance, a failure in one of its authentication steps can leave files in the host that weren't there before. This patch adds the 'bdrv_co_delete_file'

[Qemu-devel] [PATCH v4 2/4] block.c: adding bdrv_delete_file

2019-06-28 Thread Daniel Henrique Barboza
Using the new 'bdrv_co_delete_file' interface, bdrv_delete_file can be used in a way similar of the existing bdrv_create_file to to clean up a created file. The logic is also similar to what is already done in bdrv_create_file: a qemu_coroutine is created if needed, a specialized function

[Qemu-devel] [PULL v2 26/29] i386: Remove unused host_cpudef variable

2019-06-28 Thread Eduardo Habkost
The variable is completely unused, probably a leftover from previous code clean up. Signed-off-by: Eduardo Habkost Message-Id: <20190625050008.12789-3-ehabk...@redhat.com> Reviewed-by: Dr. David Alan Gilbert Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 6 -- 1 file changed, 6

Re: [Qemu-devel] [PATCH v0 2/3] qcow2: add compression type processing

2019-06-28 Thread Eric Blake
On 6/28/19 9:54 AM, Kevin Wolf wrote: >>> We would save most of this code if we added a new field to the header >>> instead of adding a header extension. Not saying that we should >>> definitely do this, but let's discuss it at least. >> >> If we add the new field to the

Re: [Qemu-devel] [PATCH 4/4] hw/i386: Introduce the microvm machine type

2019-06-28 Thread Maran Wilson
This seems like a good overall direction to be headed with Qemu. But there is a lot of Linux OS specific startup details being baked into the Qemu machine type here. Things that are usually pushed into firmware or option ROM. Instead of hard coding all the Zero page stuff into the Qemu

[Qemu-devel] [PULL v2 21/29] deprecate -mem-path fallback to anonymous RAM

2019-06-28 Thread Eduardo Habkost
From: Igor Mammedov Fallback might affect guest or worse whole host performance or functionality if backing file were used to share guest RAM with another process. Patch deprecates fallback so that we could remove it in future and ensure that QEMU will provide expected behavior and fail if it

[Qemu-devel] [PULL v2 27/29] target/i386: Add CPUID.1F generation support for multi-dies PCMachine

2019-06-28 Thread Eduardo Habkost
From: Like Xu The CPUID.1F as Intel V2 Extended Topology Enumeration Leaf would be exposed if guests want to emulate multiple software-visible die within each package. Per Intel's SDM, the 0x1f is a superset of 0xb, thus they can be generated by almost same code as 0xb except die_offset setting.

[Qemu-devel] [PULL v2 20/29] target/i386: fix feature check in hyperv-stub.c

2019-06-28 Thread Eduardo Habkost
From: Alex Bennée Commit 2d384d7c8 broken the build when built with: configure --without-default-devices --disable-user The reason was the conversion of cpu->hyperv_synic to cpu->hyperv_synic_kvm_only although the rest of the patch introduces a feature checking mechanism. So I've fixed the

[Qemu-devel] [PULL v2 29/29] vl.c: Add -smp, dies=* command line support and update doc

2019-06-28 Thread Eduardo Habkost
From: Like Xu For PC target, users could configure the number of dies per one package via command line with this patch, such as "-smp dies=2,cores=4". The parsing rules of new cpu-topology model obey the same restrictions/logic as the legacy socket/core/thread model especially on missing values

[Qemu-devel] [PULL v2 25/29] x86/cpu: use FeatureWordArray to define filtered_features

2019-06-28 Thread Eduardo Habkost
From: Wei Yang Use the same definition as features/user_features in CPUX86State. Signed-off-by: Wei Yang Message-Id: <20190620023746.9869-1-richardw.y...@linux.intel.com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Qemu-devel] [PULL v2 17/29] numa: deprecate 'mem' parameter of '-numa node' option

2019-06-28 Thread Eduardo Habkost
From: Igor Mammedov The parameter allows to configure fake NUMA topology where guest VM simulates NUMA topology but not actually getting performance benefits from it. The same or better results could be achieved using 'memdev' parameter. Beside of unpredictable performance, '-numa node.mem'

[Qemu-devel] [PULL v2 28/29] machine: Refactor smp_parse() in vl.c as MachineClass::smp_parse()

2019-06-28 Thread Eduardo Habkost
From: Like Xu To make smp_parse() more flexible and expansive, a smp_parse function pointer is added to MachineClass that machine types could override. The generic smp_parse() code in vl.c is moved to hw/core/machine.c, and become the default implementation of MachineClass::smp_parse. A

[Qemu-devel] [PULL v2 23/29] i386: Fix signedness of hyperv_spinlock_attempts

2019-06-28 Thread Eduardo Habkost
The current default value for hv-spinlocks is 0x (meaning "never retry"). However, the value is stored as a signed integer, making the getter of the hv-spinlocks QOM property return -1 instead of 0x. Fix this by changing the type of X86CPU::hyperv_spinlock_attempts to uint32_t.

[Qemu-devel] [PULL v2 14/29] i386: Update new x86_apicid parsing rules with die_offset support

2019-06-28 Thread Eduardo Habkost
From: Like Xu In new sockets/dies/cores/threads model, the apicid of logical cpu could imply die level info of guest cpu topology thus x86_apicid_from_cpu_idx() need to be refactored with #dies value, so does apicid_*_offset(). To keep semantic compatibility, the legacy pkg_offset which helps

[Qemu-devel] [PULL v2 22/29] i386: Don't print warning if phys-bits was set automatically

2019-06-28 Thread Eduardo Habkost
If cpu->host_phys_bits_limit is set, QEMU will make cpu->phys_bits be lower than host_phys_bits on some cases. This triggers a warning that was supposed to be printed only if phys-bits was explicitly set in the command-line. Reorder the code so the value of cpu->phys_bits is validated before the

[Qemu-devel] [PULL v2 12/29] hw/i386: Adjust nr_dies with configured smp_dies for PCMachine

2019-06-28 Thread Eduardo Habkost
From: Like Xu To support multiple dies configuration on PCMachine, the best place to set CPUX86State->nr_dies with requested PCMachineState->smp_dies is in pc_new_cpu() and pc_cpu_pre_plug(). Refactoring pc_new_cpu() is applied and redundant parameter "const char *typename" would be removed.

[Qemu-devel] [PULL v2 19/29] hppa: Delete unused hppa_cpu_list() function

2019-06-28 Thread Eduardo Habkost
hppa_cpu_list() is dead code and is never called. Delete it. Cc: Richard Henderson Reviewed-by: Igor Mammedov Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Eduardo Habkost Message-Id: <20190517191332.23400-1-ehabk...@redhat.com> Acked-by: Richard

[Qemu-devel] [PULL v2 18/29] numa: deprecate implict memory distribution between nodes

2019-06-28 Thread Eduardo Habkost
From: Igor Mammedov Implicit RAM distribution between nodes has exactly the same issues as: "numa: deprecate 'mem' parameter of '-numa node' option" only with QEMU being the user that's 'adding' 'mem' parameter. Deprecate it, to get it out of the way so that we could consolidate guest RAM

[Qemu-devel] [PULL v2 15/29] pc: fix possible NULL pointer dereference in pc_machine_get_device_memory_region_size()

2019-06-28 Thread Eduardo Habkost
From: Igor Mammedov QEMU will crash when device-memory-region-size property is read if ms->device_memory wasn't initialized yet. Crash can be reproduced with: $QEMU -preconfig -qmp unix:qmp_socket,server,nowait & ./scripts/qmp/qom-get -s qmp_socket /machine.device-memory-region-size Instead

[Qemu-devel] [PULL v2 10/29] vl.c: Replace smp global variables with smp machine properties

2019-06-28 Thread Eduardo Habkost
From: Like Xu The global smp variables in vl.c are completely replaced with machine properties. Form this commit, the smp_cpus/smp_cores/smp_threads/max_cpus are deprecated and only machine properties within MachineState are fully applied and enabled. Signed-off-by: Like Xu Reviewed-by:

[Qemu-devel] [PULL v2 16/29] machine: show if CLI option '-numa node, mem' is supported in QAPI schema

2019-06-28 Thread Eduardo Habkost
From: Igor Mammedov Legacy '-numa node,mem' option has a number of issues and mgmt often defaults to it. Unfortunately it's no possible to replace it with an alternative '-numa memdev' without breaking migration compatibility. What's possible though is to deprecate it, keeping option working

[Qemu-devel] [PULL v2 09/29] hw: Replace global smp variables with MachineState for all remaining archs

2019-06-28 Thread Eduardo Habkost
From: Like Xu The global smp variables in alpha/hppa/mips/openrisc/sparc*/xtensa codes are replaced with smp properties from MachineState. A local variable of the same name would be introduced in the declaration phase if it's used widely in the context OR replace it on the spot if it's only

[Qemu-devel] [PULL v2 08/29] hw/arm: Replace global smp variables with machine smp properties

2019-06-28 Thread Eduardo Habkost
From: Like Xu The global smp variables in arm are replaced with smp machine properties. The init_cpus() and *_create_rpu() are refactored to pass MachineState. A local variable of the same name would be introduced in the declaration phase if it's used widely in the context OR replace it on the

[Qemu-devel] [PULL v2 13/29] i386/cpu: Consolidate die-id validity in smp context

2019-06-28 Thread Eduardo Habkost
From: Like Xu The field die_id (default as 0) and has_die_id are introduced to X86CPU. Following the legacy smp check rules, the die_id validity is added to the same contexts as leagcy smp variables such as hmp_hotpluggable_cpus(), machine_set_cpu_numa_node(), cpu_slot_to_string() and

[Qemu-devel] [PULL v2 24/29] i386: make 'hv-spinlocks' a regular uint32 property

2019-06-28 Thread Eduardo Habkost
From: Roman Kagan X86CPU.hv-spinlocks is a uint32 property that has a special setter validating the value to be no less than 0xFFF and no bigger than UINT_MAX. The latter check is redundant; as for the former, there appears to be no reason to prohibit the user from setting it to a lower value.

[Qemu-devel] [PULL v2 07/29] hw/i386: Replace global smp variables with machine smp properties

2019-06-28 Thread Eduardo Habkost
From: Like Xu The global smp variables in i386 are replaced with smp machine properties. To avoid calling qdev_get_machine() as much as possible, some related funtions for acpi data generations are refactored. No semantic changes. A local variable of the same name would be introduced in the

[Qemu-devel] [PULL v2 11/29] i386: Add die-level cpu topology to x86CPU on PCMachine

2019-06-28 Thread Eduardo Habkost
From: Like Xu The die-level as the first PC-specific cpu topology is added to the leagcy cpu topology model, which has one die per package implicitly and only the numbers of sockets/cores/threads are configurable. In the new model with die-level support, the total number of logical processors

[Qemu-devel] [PULL v2 06/29] hw/s390x: Replace global smp variables with machine smp properties

2019-06-28 Thread Eduardo Habkost
From: Like Xu The global smp variables in s390x are replaced with smp machine properties. A local variable of the same name would be introduced in the declaration phase if it's used widely in the context OR replace it on the spot if it's only used once. No semantic changes. Signed-off-by: Like

Re: [Qemu-devel] [PULL 00/29] Machine next patches

2019-06-28 Thread Eduardo Habkost
On Thu, Jun 27, 2019 at 07:49:47PM -0700, no-re...@patchew.org wrote: > === TEST SCRIPT END === > > /var/tmp/patchew-tester-tmp-vfw4sa78/src/target/s390x/kvm.c:367: undefined > reference to `max_cpus' > /usr/bin/ld: target/s390x/kvm.o: in function > `kvm_s390_vcpu_interrupt_pre_save': >

[Qemu-devel] [PULL v2 03/29] general: Replace global smp variables with smp machine properties

2019-06-28 Thread Eduardo Habkost
From: Like Xu Basically, the context could get the MachineState reference via call chains or unrecommended qdev_get_machine() in !CONFIG_USER_ONLY mode. A local variable of the same name would be introduced in the declaration phase out of less effort OR replace it on the spot if it's only used

[Qemu-devel] [PULL v2 05/29] hw/riscv: Replace global smp variables with machine smp properties

2019-06-28 Thread Eduardo Habkost
From: Like Xu The global smp variables in riscv are replaced with smp machine properties. A local variable of the same name would be introduced in the declaration phase if it's used widely in the context OR replace it on the spot if it's only used once. No semantic changes. Signed-off-by: Like

[Qemu-devel] [PULL v2 04/29] hw/ppc: Replace global smp variables with machine smp properties

2019-06-28 Thread Eduardo Habkost
From: Like Xu The global smp variables in ppc are replaced with smp machine properties. A local variable of the same name would be introduced in the declaration phase if it's used widely in the context OR replace it on the spot if it's only used once. No semantic changes. Signed-off-by: Like

[Qemu-devel] [PULL v2 02/29] machine: Refactor smp-related call chains to pass MachineState

2019-06-28 Thread Eduardo Habkost
From: Like Xu To get rid of the global smp_* variables we're currently using, it's recommended to pass MachineState in the list of incoming parameters for functions that use global smp variables, thus some redundant parameters are dropped. It's applied for legacy smbios_*(), *_machine_reset(),

[Qemu-devel] [PULL v2 01/29] hw/boards: Add struct CpuTopology to MachineState

2019-06-28 Thread Eduardo Habkost
From: Like Xu The cpu topology property CpuTopology is added to the MachineState and its members are initialized with the leagcy global smp variables. >From this commit, the code in the system emulation mode is supposed to use cpu topology variables from MachineState instead of the global ones

[Qemu-devel] [PULL v2 00/29] Machine and x86 queue, 2019-06-28

2019-06-28 Thread Eduardo Habkost
Changes v1 -> v2: * Fix s390x build failure The following changes since commit 474f3938d79ab36b9231c9ad3b5a9314c2aeacde: Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-21-2019' into staging (2019-06-21 15:40:50 +0100) are available in the Git repository at:

Re: [Qemu-devel] [PATCH 0/4] Introduce the microvm machine type

2019-06-28 Thread no-reply
Patchew URL: https://patchew.org/QEMU/20190628115349.60293-1-...@redhat.com/ Hi, This series failed build test on s390x host. Please find the details below. === TEST SCRIPT BEGIN === #!/bin/bash # Testing script will be invoked under the git checkout with # HEAD pointing to a commit that has

[Qemu-devel] [PATCH v2 4/4] m68k: Add an entry for the NeXTcube machine to the MAINTAINERS file

2019-06-28 Thread Thomas Huth
I don't have much clue about the NeXT hardware, but at least I know now the source files a little bit, so I volunteer to pick up patches and send PULL requests for them until someone else with more knowledge steps up to do this job instead. Signed-off-by: Thomas Huth --- MAINTAINERS | 7 +++

[Qemu-devel] [PATCH v2 2/4] m68k: Add NeXTcube keyboard device

2019-06-28 Thread Thomas Huth
It is likely still quite incomplete (e.g. mouse and interrupts are not implemented yet), but it is good enough for keyboard input at the firmware monitor. This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-kbd.c and

[Qemu-devel] [PATCH v2 3/4] m68k: Add NeXTcube machine

2019-06-28 Thread Thomas Huth
It is still quite incomplete (no SCSI, no floppy emulation, no network, etc.), but the firmware already shows up the debug monitor prompt in the framebuffer display, so at least the very basics are already working. This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at

[Qemu-devel] [PATCH v2 1/4] m68k: Add NeXTcube framebuffer device emulation

2019-06-28 Thread Thomas Huth
The NeXTcube uses a linear framebuffer with 4 greyscale colors and a fixed resolution of 1120 * 832. This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-fb.c and altered to fit the latest interface of the current QEMU

[Qemu-devel] [PATCH v2 0/4] m68k: Add basic support for the NeXTcube machine

2019-06-28 Thread Thomas Huth
Bryce apparently never got around to work on this again, so I'll have another try now ... During Google Summer of Code 2011, Bryce Lanham added the possibility to emulate the NeXTcube machine in QEMU, e.g. see this URL for some details:

[Qemu-devel] [PATCH] fixup! hw/s390x: Replace global smp variables with machine smp properties

2019-06-28 Thread Eduardo Habkost
On Sun, May 19, 2019 at 04:54:24AM +0800, Like Xu wrote: > The global smp variables in s390x are replaced with smp machine properties. > > A local variable of the same name would be introduced in the declaration > phase if it's used widely in the context OR replace it on the spot if it's > only

Re: [Qemu-devel] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren

2019-06-28 Thread Alistair Francis
On Thu, Jun 27, 2019 at 11:12 PM Palmer Dabbelt wrote: > > On Thu, 27 Jun 2019 12:56:57 PDT (-0700), alistai...@gmail.com wrote: > > On Wed, Jun 26, 2019 at 1:25 AM Palmer Dabbelt wrote: > >> > >> On Tue, 25 Jun 2019 23:58:34 PDT (-0700), bmeng...@gmail.com wrote: > >> > On Wed, Jun 26, 2019 at

[Qemu-devel] [PULL 30/34] hw/riscv: Split out the boot functions

2019-06-28 Thread Palmer Dabbelt
From: Alistair Francis Split the common RISC-V boot functions into a seperate file. This allows us to share the common code. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/Makefile.objs | 1 + hw/riscv/boot.c |

Re: [Qemu-devel] [PATCH v3 19/50] tcg: let plugins instrument memory accesses

2019-06-28 Thread Aaron Lindsay OS via Qemu-devel
On Jun 28 18:11, Alex Bennée wrote: > Aaron Lindsay OS writes: > > On Jun 14 18:11, Alex Bennée wrote: > >> From: "Emilio G. Cota" > >> > >> Here the trickiest feature is passing the host address to > >> memory callbacks that request it. Perhaps it would be more > >> appropriate to pass a

[Qemu-devel] [PULL 29/34] riscv: sifive_u: Update the plic hart config to support multicore

2019-06-28 Thread Palmer Dabbelt
From: Bin Meng At present the PLIC is instantiated to support only one hart, while the machine allows at most 4 harts to be created. When more than 1 hart is configured, PLIC needs to instantiated to support multicore, otherwise an SMP OS does not work. Signed-off-by: Bin Meng Reviewed-by:

[Qemu-devel] [PULL 28/34] riscv: sifive_u: Do not create hard-coded phandles in DT

2019-06-28 Thread Palmer Dabbelt
From: Bin Meng At present the cpu, plic and ethclk nodes' phandles are hard-coded to 1/2/3 in DT. If we configure more than 1 cpu for the machine, all cpu nodes' phandles conflict with each other as they are all 1. Fix it by removing the hardcode. Signed-off-by: Bin Meng Reviewed-by: Alistair

[Qemu-devel] [PULL 33/34] roms: Add OpenSBI version 0.3

2019-06-28 Thread Palmer Dabbelt
From: Alistair Francis Add OpenSBI version 0.3 as a git submodule and as a prebult binary. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- .gitmodules | 3 ++ Makefile

[Qemu-devel] [PULL 27/34] disas/riscv: Fix `rdinstreth` constraint

2019-06-28 Thread Palmer Dabbelt
From: "Wladimir J. van der Laan" The constraint for `rdinstreth` was comparing the csr number to 0xc80, which is `cycleh` instead. Fix this. Signed-off-by: Wladimir J. van der Laan Signed-off-by: Michael Clark Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer

[Qemu-devel] [PULL 19/34] target/riscv: Remove user version information

2019-06-28 Thread Palmer Dabbelt
From: Alistair Francis Remove the user version information. This was never used and never publically exposed in a release of QEMU, so let's just remove it. In future to manage versions we can extend the extension properties to specify version. Signed-off-by: Alistair Francis Reviewed-by:

[Qemu-devel] [PULL 31/34] hw/riscv: Add support for loading a firmware

2019-06-28 Thread Palmer Dabbelt
From: Alistair Francis Add support for loading a firmware file for the virt machine and the SiFive U. This can be run with the following command: qemu-system-riscv64 -machine virt -bios fw_jump.bin -kernel vmlinux Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng

[Qemu-devel] [PULL 34/34] hw/riscv: Load OpenSBI as the default firmware

2019-06-28 Thread Palmer Dabbelt
From: Alistair Francis If the user hasn't specified a firmware to load (with -bios) or specified no bios (with -bios none) then load OpenSBI by default. This allows users to boot a RISC-V kernel with just -kernel. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng

[Qemu-devel] [PULL 22/34] RISC-V: Add support for the Zicsr extension

2019-06-28 Thread Palmer Dabbelt
The various CSR instructions have been split out of the base ISA as part of the ratification process. This patch adds a Zicsr argument, which disables all the CSR instructions. Signed-off-by: Palmer Dabbelt Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 +

[Qemu-devel] [PULL 16/34] target/riscv: Set privledge spec 1.11.0 as default

2019-06-28 Thread Palmer Dabbelt
From: Alistair Francis Set the priv spec version 1.11.0 as the default and allow selecting it via the command line. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-)

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