From: Greg Kurz
kvmppc_set_interrupt() has a stub that does nothing when CONFIG_KVM is
not defined.
Signed-off-by: Greg Kurz
Message-Id: <156051055182.224162.15842560287892241124.st...@bahia.lan>
Signed-off-by: David Gibson
---
hw/ppc/ppc.c | 2 --
1 file changed, 2 deletions(-)
diff --git a
From: Mark Cave-Ayland
Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_X1 macro which performs the decode based
upon xB at translation time.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Message-Id: <20190616123751.781-10-
From: Mark Cave-Ayland
Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_R2 macro which performs the decode based
upon rD and rB at translation time.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Message-Id: <20190616123751.
From: Cédric Le Goater
When a CPU is reseted, the hypervisor (Linux or OPAL) invalidates the
POOL interrupt context of a CPU with this special command. It returns
the POOL CAM line value and resets the VP bit.
Fixes: 4836b45510aa ("ppc/xive: activate HV support")
Signed-off-by: Cédric Le Goater
From: Cédric Le Goater
When an interrupt needs to be delivered, the XIVE interrupt controller
presenter scans the CAM lines of the thread interrupt contexts of the
HW threads of the chip to find a matching vCPU. The interrupt context
is composed of 4 different sets of registers: Physical, HV, OS
From: Mark Cave-Ayland
Since commit 8a14d31b00 "target/ppc: switch fpr/vsrl registers so all VSX
registers are in host endian order" functions getVSR() and putVSR() which used
to convert the VSR registers into host endian order are no longer required.
Signed-off-by: Mark Cave-Ayland
Message-Id:
From: Mark Cave-Ayland
Introduce a new GEN_VSX_HELPER_VSX_MADD macro for the generator function which
enables the source and destination registers to be decoded at translation time.
This enables the determination of a or m form to be made at translation time so
that a single helper function can
From: Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Message-Id: <20190616123751.781-15-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: David Gibson
---
target/ppc/helper.h | 4 ++--
target/ppc/int_helper.c | 12
target/
From: Cédric Le Goater
The init_emu() handles are now empty. Remove them and rename
spapr_irq_init_device() to spapr_irq_init_kvm().
Signed-off-by: Cédric Le Goater
Message-Id: <20190614165920.12670-3-...@kaod.org>
Reviewed-by: Greg Kurz
Signed-off-by: David Gibson
---
hw/ppc/spapr_irq.c
From: Mark Cave-Ayland
Since commit 8a14d31b00 "target/ppc: switch fpr/vsrl registers so all VSX
registers are in host endian order" functions getVSR() and putVSR() which used
to convert the VSR registers into host endian order are no longer required.
Now that there are now no more users of getV
From: Greg Kurz
Commit 9fb6eb7ca50c added the declaration of xics_spapr_connect(), which
has no implementation and no users.
This is a leftover from a previous iteration of this patch. Drop it.
Signed-off-by: Greg Kurz
Message-Id: <156077919546.433243.8748677531446035746.st...@bahia.lan>
Revie
From: Mark Cave-Ayland
Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_R3 macro which performs the decode based
upon rD, rA and rB at translation time.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Message-Id: <20190616123
From: Mark Cave-Ayland
Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_X2_AB macro which performs the decode based
upon xA and xB at translation time.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Message-Id: <201906161237
From: Greg Kurz
This allows errors happening there to be propagated up to spapr_irq,
just like XIVE already does.
Signed-off-by: Greg Kurz
Message-Id: <156077921763.433243.4614327010172954196.st...@bahia.lan>
Reviewed-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics.c
From: Mark Cave-Ayland
Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_R2_AB macro which performs the decode based
upon rA and rB at translation time.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Message-Id: <201906161237
From: Mark Cave-Ayland
Rather than perform the VSR register decoding within the helper itself,
introduce a new GEN_VSX_HELPER_X3 macro which performs the decode based
upon xT, xA and xB at translation time.
With the previous changes to the VSX_CMP generator and helper macros the
opcode parameter
From: Greg Kurz
Passing both errp and &local_err to functions is a recipe for messing
things up.
Since we must use &local_err for icp_kvm_realize(), use &local_err
everywhere where rollback must happen and have a single call to
error_propagate() them all. While here, add errno to the error
messa
From: Greg Kurz
kvm_enabled() expands to (0) when CONFIG_KVM is not defined. The first
CONFIG_KVM guard is thus useless and it is likely that the compiler
will optimize the code out in the case of the second guard. And even
if it doesn't, we have a stub for kvmppc_get_hypercall().
Signed-off-by:
From: Greg Kurz
Make xics_kvm_disconnect() able to undo the changes of a partial execution
of xics_kvm_connect() and use it to perform rollback.
Note that kvmppc_define_rtas_kernel_token(0) never fails, no matter the
RTAS call has been defined or not.
Signed-off-by: Greg Kurz
Message-Id: <1560
From: Greg Kurz
Older KVMs on POWER9 don't support destroying/recreating a KVM XICS
device, which is required by 'dual' interrupt controller mode. This
causes QEMU to emit a warning when the guest is rebooted and to fall
back on XICS emulation:
qemu-system-ppc64: warning: kernel_irqchip allowed
From: Greg Kurz
There is no need to rollback anything at this point, so just return an
error.
Signed-off-by: Greg Kurz
Message-Id: <156077920657.433243.13541093940589972734.st...@bahia.lan>
Reviewed-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics_kvm.c | 2 +-
1 file change
From: Greg Kurz
So that no one is tempted to drop that code, which is never called
for cold plugged CPUs.
Signed-off-by: Greg Kurz
Message-Id: <156078063349.435533.12283208810037409702.st...@bahia.lan>
Reviewed-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics.c | 1 +
1 file
From: Cédric Le Goater
Today, the interrupt device is fully initialized at reset when the CAS
negotiation process has completed. Depending on the KVM capabilities,
the SpaprXive memory regions (ESB, TIMA) are initialized with a host
MMIO backend or a QEMU emulated backend. This results in a compl
From: Greg Kurz
Hot-unplugging a PHB with a VFIO device connected to it crashes QEMU:
-device spapr-pci-host-bridge,index=1,id=phb1 \
-device vfio-pci,host=0034:01:00.3,id=vfio0
(qemu) device_del phb1
[ 357.207183] iommu: Removing device 0001:00:00.0 from group 1
[ 360.375523] rpadlpar_io: sl
From: Greg Kurz
This allows to drop the CONFIG_KVM guard from the code.
Signed-off-by: Greg Kurz
Message-Id: <156051056289.224162.15553539098911498678.st...@bahia.lan>
Signed-off-by: David Gibson
---
target/ppc/kvm_ppc.h | 5 +
target/ppc/machine.c | 2 --
2 files changed, 5 insertions(+)
From: Greg Kurz
The XICS-related RTAS calls and hypercalls in QEMU are not supposed to
be called when the KVM in-kernel XICS is in use.
Add some explicit checks to detect that, print an error message and report
an hardware error to the guest.
Signed-off-by: Greg Kurz
Message-Id:
<156044429419
From: Greg Kurz
spapr_dt_drc() scans the aliases of all DRConnector objects and filters
the ones that it will use to generate OF properties according to their
owner and type.
Passing bus->parent_dev _works_ if bus belongs to a PCI bridge, but it is
NULL if it is the PHB's root bus. This causes a
From: Greg Kurz
kvm_enabled() expands to (0) when CONFIG_KVM is not defined.
Signed-off-by: Greg Kurz
Message-Id: <156051052977.224162.17306829691809502082.st...@bahia.lan>
Signed-off-by: David Gibson
---
hw/ppc/spapr_pci.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/ppc/spapr_pci
From: Greg Kurz
Checking that we're not using the in-kernel XICS is ok with the "xics"
interrupt controller mode, but it is definitely not enough with the
other modes since the guest could be using XIVE.
Ensure XIVE is not in use when emulated XICS RTAS/hypercalls are
called.
Signed-off-by: Gre
From: Greg Kurz
Switch to using the connect/disconnect terminology like we already do for
XIVE.
Signed-off-by: Greg Kurz
Message-Id: <156077920102.433243.6605099291134598170.st...@bahia.lan>
Reviewed-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics_kvm.c | 2 +-
hw/
From: Greg Kurz
QEMU may crash when running a spapr machine in 'dual' interrupt controller
mode on some older (but not that old, eg. ubuntu 18.04.2) KVMs with partial
XIVE support:
qemu-system-ppc64: hw/ppc/spapr_rtas.c:411: spapr_rtas_register:
Assertion `!name || !rtas_table[token].name' fail
From: Greg Kurz
kvm_enabled() expands to (0) when CONFIG_KVM is not defined. It is
likely that the compiler will optimize the code out. And even if
it doesn't, we have a stub for kvmppc_get_hypercall().
Signed-off-by: Greg Kurz
Message-Id: <156051053529.224162.3489943067148134636.st...@bahia.la
From: Cédric Le Goater
gcc9 reports :
In file included from /usr/include/string.h:494,
from ./include/qemu/osdep.h:101,
from ./target/ppc/kvm.c:17:
In function ‘strncpy’,
inlined from ‘kvmppc_define_rtas_kernel_token’ at ./target/ppc/kvm.c:2648:5:
/usr/inclu
From: Mark Cave-Ayland
Since commit 8a14d31b00 "target/ppc: switch fpr/vsrl registers so all VSX
registers are in host endian order" functions getVSR() and putVSR() which used
to convert the VSR registers into host endian order are no longer required.
Signed-off-by: Mark Cave-Ayland
Message-Id:
From: Cédric Le Goater
This includes various small updates and a better description of the
chosen interrupt mode resulting from the combination of the 'ic-mode'
machine option, the 'kernel_irqchip' option, guest support and KVM
support.
Signed-off-by: Cédric Le Goater
Message-Id: <2019061216042
From: Cédric Le Goater
The PNV_XSCOM_BASE and PNV_XSCOM_SIZE macros are specific to POWER8
and they are used when the device tree is populated and the MMIO
region created, even for POWER9 chips. This is not too much of a
problem today because we don't have important devices on the second
chip, bu
From: Philippe Mathieu-Daudé
Commit 14e714900f6 refactored the call to spapr_dt_drc(),
introducing a potential NULL pointer dereference while
accessing bus->parent_dev.
A trivial audit show 'bus' is not null in the two places
the static function spapr_dt_drc() is called.
Since the 'bus' paramete
The following changes since commit 7d0e02405fc02a181319b1ab8681d2f72246b7c6:
Merge remote-tracking branch
'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2019-07-01
17:40:32 +0100)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-4.1-
From: Alexey Kardashevskiy
At the moment the rtas's Makefile uses generic QEMU rules which means
that when QEMU is compiled on a little endian system, the spapr-rtas.bin
is compiled as little endian too which is incorrect as it is always
executed in big endian mode.
This enforces -mbig by defini
From: Cédric Le Goater
It has now became useless with the previous patch.
Signed-off-by: Cédric Le Goater
Message-Id: <20190612174345.9799-3-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 10 --
include/hw/ppc/pnv.h | 5 +
2 files changed, 1 insertion(+), 14
From: Cédric Le Goater
The firmware (skiboot) of the PowerNV machines can configure the XIVE
interrupt controller to activate StoreEOI on the ESB pages of the
interrupts. This feature lets software do an EOI with a store instead
of a load. It is not activated today on P9 for rare race condition
i
Markus Armbruster writes:
> There are just two HMP commands related to QOM: qom-list and qom-set.
> Move their handlers from monitor/hmp-cmds.c to new qom/qom-hmp-cmds.c,
> where they are covered by MAINTAINERS section QOM.
Actually three: hmp_info_qom_tree(). I'm squashing the obvious movement
Le 25/06/2019 à 16:27, Aleksandar Markovic a écrit :
From: Aleksandar Markovic
The size is one byte less than it should be:
address-space: rc4030-dma
-fffe (prio 0, i/o): rc4030.dma
rc4030 is used in MIPS Jazz board context.
Signed-off-by: Aleksandar Markovic
Le 25/06/2019 à 16:27, Aleksandar Markovic a écrit :
From: Aleksandar Markovic
Fix some simple checkpatch.pl warnings in rc4030.c.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Hervé Poussineau
---
hw/dma/rc4030.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletion
On Wed, Jun 26, 2019 at 10:43:33AM +0530, Aravinda Prasad wrote:
>
>
> On Tuesday 25 June 2019 12:30 PM, Greg Kurz wrote:
> > On Tue, 25 Jun 2019 11:46:06 +0530
> > Aravinda Prasad wrote:
> >
> >> On Monday 24 June 2019 07:59 PM, Greg Kurz wrote:
> >>> On Wed, 12 Jun 2019 14:51:38 +0530
> >>> A
On Wed, Jun 12, 2019 at 02:51:13PM +0530, Aravinda Prasad wrote:
> Memory error such as bit flips that cannot be corrected
> by hardware are passed on to the kernel for handling.
> If the memory address in error belongs to guest then
> the guest kernel is responsible for taking suitable action.
> P
On 7/1/19 8:12 PM, Philippe Mathieu-Daudé wrote:
> When the state machine is ready to accept command, the bit 7 of
> the status register (SR) is set to 1.
> The guest polls the status register and check this bit before
> writting command to the internal 'Write State Machine' (WSM).
writing
>
Peter Maydell writes:
> On Mon, 1 Jul 2019 at 18:50, Alistair Francis
> wrote:
>>
>> On Mon, 2019-07-01 at 17:54 +0100, Peter Maydell wrote:
>> > On Thu, 27 Jun 2019 at 16:24, Palmer Dabbelt
>> > wrote:
>> > > From: Alistair Francis
>> > >
>> > > Add OpenSBI version 0.3 as a git submodule and
On 7/1/19 8:12 PM, Philippe Mathieu-Daudé wrote:
> The same pattern is used when setting the flash in READ_ARRAY mode:
> - Set the state machine command to READ_ARRAY
> - Reset the write_cycle counter
> - Reset the memory region in ROMD
>
> Refactor the current code by extracting this pattern.
On 7/1/19 8:12 PM, Philippe Mathieu-Daudé wrote:
> In the "Read Array Flowchart" the command has a value of 0xFF.
>
> In the document [*] the "Read Array Flowchart", the READ_ARRAY
> command has a value of 0xff.
>
> Use the correct value in the pflash model.
>
> There is no change of behavior
The following changes since commit 7d0e02405fc02a181319b1ab8681d2f72246b7c6:
Merge remote-tracking branch
'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2019-07-01
17:40:32 +0100)
are available in the Git repository at:
https://github.com/XanClic/qemu.git tags/pull-block
On Wed, Jun 12, 2019 at 02:51:21PM +0530, Aravinda Prasad wrote:
> Upon a machine check exception (MCE) in a guest address space,
> KVM causes a guest exit to enable QEMU to build and pass the
> error to the guest in the PAPR defined rtas error log format.
>
> This patch builds the rtas error log,
On Wed, Jun 12, 2019 at 02:51:04PM +0530, Aravinda Prasad wrote:
> Introduce the KVM capability KVM_CAP_PPC_FWNMI so that
> the KVM causes guest exit with NMI as exit reason
> when it encounters a machine check exception on the
> address belonging to a guest. Without this capability
> enabled, KVM
From: Andrey Shinkevich
The bottom node is the intermediate block device that has the base as its
backing image. It is used instead of the base node while a block stream
job is running to avoid dependency on the base that may change due to the
parallel jobs. The change may take place due to a fil
From: Zhang Chen
Add chardev handler to send notification to remote(current from Xen) colo-frame.
Signed-off-by: Zhang Chen
Signed-off-by: Jason Wang
---
net/colo-compare.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/net/colo-compare.c b/net/co
On Wed, Jun 12, 2019 at 02:51:38PM +0530, Aravinda Prasad wrote:
> This patch adds support in QEMU to handle "ibm,nmi-register"
> and "ibm,nmi-interlock" RTAS calls and sets the default
> value of SPAPR_CAP_FWNMI_MCE to SPAPR_CAP_ON for machine
> type 4.0.
>
> The machine check notification addres
On Mon, 1 Jul 2019 at 22:54, Peter Maydell wrote:
>
> On Sun, 30 Jun 2019 at 11:21, Hongbo Zhang wrote:
> >
> > For the Aarch64, there is one machine 'virt', it is primarily meant to
> > run on KVM and execute virtualization workloads, but we need an
> > environment as faithful as possible to phy
From: Zhang Chen
We need to notify net filter to do checkpoint for Xen COLO, like KVM side.
Signed-off-by: Zhang Chen
Signed-off-by: Jason Wang
---
migration/colo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/migration/colo.c b/migration/colo.c
index 8c16440..9f84b1f 100644
--- a/mi
From: "Dr. David Alan Gilbert"
Expand self-announce test to check we can stop an announce timer.
We set it up to send 300 packets, but after we receive
the first one we tell it to stop.
We error if:
a) We receive more than 30 of the packets
b) We're still receiving packets after a lot long
From: Zhang Chen
This patch make colo-compare can send message to remote COLO frame(Xen) when
occur checkpoint.
Signed-off-by: Zhang Chen
Signed-off-by: Jason Wang
---
net/colo-compare.c | 54 --
1 file changed, 44 insertions(+), 10 deletio
On Tue, 2 Jul 2019 at 00:08, Leif Lindholm wrote:
>
> Hi Peter,
>
> On Mon, Jul 01, 2019 at 03:54:24PM +0100, Peter Maydell wrote:
> > I've pointed out a number of issues with these patches, but they
> > all turn out to be very minor (mostly fixable by moving code between
> > patch 1 and 2). The o
On 7/1/19 8:12 PM, Philippe Mathieu-Daudé wrote:
> A "system reset" sets the device state machine in READ_ARRAY mode
> and, after some delay, set the SR.7 READY bit.
>
> We do not model timings, so we set the SR.7 bit directly.
>
> This pflash device is a child of TYPE_DEVICE.
> The TYPE_DEVIC
From: "Dr. David Alan Gilbert"
Add the optional interface list to the HMP command.
i.e.
All interfaces
announce_self
Just the named interfaces:
announce_self vn1,vn2
Signed-off-by: Dr. David Alan Gilbert
Signed-off-by: Jason Wang
---
hmp-commands.hx| 6 --
mo
From: Zhang Chen
We add the "notify_dev=chardevID" parameter. After that colo-compare can
connect with
remote(currently just for Xen, KVM-COLO didn't need it.) colo-frame through
chardev socket,
it can notify remote(Xen) colo-frame to handle checkpoint event.
Signed-off-by: Zhang Chen
Signed-
From: Stefano Garzarella
Since the get_str_sep() function is no longer used in
net/net.c, we can remove it.
Signed-off-by: Stefano Garzarella
Reviewed-by: Markus Armbruster
Signed-off-by: Jason Wang
---
net/net.c | 20
1 file changed, 20 deletions(-)
diff --git a/net/ne
From: Andrey Shinkevich
This patch is used in the 'block/stream: introduce a bottom node'
that is following. Instead of the base node, the caller may pass
the node that has the base as its backing image to the function
bdrv_is_allocated_above() with a new parameter include_base = true
and get rid
From: "Dr. David Alan Gilbert"
Add the optional ID to the HMP command.
e.g.
# start an announce for a long time on eth1
migrate_set_parameter announce-rounds 1000
announce_self "eth1" e1
# start an announce on eth2
announce_self "eth2" e2
# Change e1 to be announcing on eth1
From: Cédric Le Goater
qdev_set_nic_properties() is already used in the Aspeed SoC level to
bind the ftgmac100 device to the netdev.
This is fixing support for multiple net devices.
Signed-off-by: Cédric Le Goater
Signed-off-by: Jason Wang
---
hw/net/ftgmac100.c | 2 --
1 file changed, 2 del
From: "Dr. David Alan Gilbert"
Previously there was a single instance of the timer used by
monitor triggered announces, that's OK, but when combined with the
previous change that lets you have announces for subsets of interfaces
it's a bit restrictive if you want to do different things to differe
From: Stefano Garzarella
net_client_init() uses a variable length array to store the prefix
of 'ipv6-net' parameter (e.g. if ipv6-net=fec0::0/64, the prefix
is 'fec0::0').
This patch introduces g_strsplit() to split the 'ipv6-net' parameter,
so we can remove the variable length array.
Suggested-
The following changes since commit 7d0e02405fc02a181319b1ab8681d2f72246b7c6:
Merge remote-tracking branch
'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2019-07-01
17:40:32 +0100)
are available in the git repository at:
https://github.com/jasowang/qemu.git tags/net-pull-
From: Markus Armbruster
Signed-off-by: Markus Armbruster
Signed-off-by: Jason Wang
---
qemu-bridge-helper.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/qemu-bridge-helper.c b/qemu-bridge-helper.c
index f9940de..95624bc 100644
--- a/qemu-bridge-helper.c
+++
From: Andrey Shinkevich
The goto is unnecessary in the stream_run() since the common exit
code was removed in the commit eb23654dbe43b549ea2a9ebff9d8e:
"jobs: utilize job_exit shim".
Signed-off-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Andrey Shinkevich
Reviewed-by: Alberto Garcia
Revie
From: Markus Armbruster
Signed-off-by: Markus Armbruster
Signed-off-by: Jason Wang
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8206fc5..c7b0c2c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1934,6 +1934,7 @@ M: Jason Wang
S: Maintained
On 7/1/2019 7:25 PM, Igor Mammedov wrote:
On Fri, 14 Jun 2019 23:56:24 +0800
Tao Xu wrote:
From: Liu Jingqi
HMAT is defined in ACPI 6.2: 5.2.27 Heterogeneous Memory Attribute Table (HMAT).
The specification references below link:
http://www.uefi.org/sites/default/files/resources/ACPI_6_2.pdf
From: Stefano Garzarella
RBD APIs don't allow us to write more than the size set with
rbd_create() or rbd_resize().
In order to support growing images (eg. qcow2), we resize the
image before write operations that exceed the current size.
Signed-off-by: Stefano Garzarella
Message-id: 20190509145
From: Stefano Garzarella
If 'ipv6-prefixlen' is not a number, the current behaviour
produces an assertion failure:
$ qemu-system-x86_64 -net user,ipv6-net=feca::0/a
qemu-system-x86_64: qemu/util/qemu-option.c:1175: qemu_opts_foreach:
Assertion `!errp || !*errp' failed.
Aborted (co
On 7/1/2019 6:59 PM, Igor Mammedov wrote:
On Fri, 14 Jun 2019 23:56:23 +0800
Tao Xu wrote:
Add build_mem_ranges callback to AcpiDeviceIfClass and use
it for generating SRAT and HMAT numa memory ranges.
Suggested-by: Igor Mammedov
Co-developed-by: Liu Jingqi
Signed-off-by: Liu Jingqi
Signed
On Tue, Jul 2, 2019 at 8:20 AM Alistair Francis wrote:
>
> On Mon, Jul 1, 2019 at 8:56 AM wrote:
> >
> > From: Jonathan Behrens
> >
> > QEMU currently always triggers an illegal instruction exception when
> > code attempts to read the time CSR. This is valid behavor, but only if
> > the TM bit i
From: Zhang Chen
We need use this function to send notification message for remote
colo-frame(Xen).
So we add new parameter for this job.
Signed-off-by: Zhang Chen
Signed-off-by: Jason Wang
---
net/colo-compare.c | 41 +
1 file changed, 33 insertions(+
From: Stephen Checkoway
Most AMD commands only examine 11 bits of the address. This masks the
addresses used in the comparison to 11 bits. The exceptions are word or
sector addresses which use offset directly rather than the shifted
offset, boff.
Signed-off-by: Stephen Checkoway
Message-Id: <20
From: "Dr. David Alan Gilbert"
Allow the caller to restrict the set of interfaces that announces are
sent on. The default is still to send on all interfaces.
e.g.
{ "execute": "announce-self", "arguments": { "initial": 50, "max": 550,
"rounds": 5, "step": 50, "interfaces": ["vn2", "vn1"] }
Reviewed-by: Alistair Francis
Message-Id: <20190627202719.17739-28-phi...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 40 +++-
1 file changed, 19 insertions(+), 21 deletions(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/bloc
Introduce the FlashConfig structure, to be able to run the same set
of tests on different flash models/configurations.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-6-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD:
On 2019/6/10 上午12:44, Zhang Chen wrote:
From: Zhang Chen
Xen COLO based on KVM COLO architecture, it shared COLO proxy and block
replication with KVM COLO. The only differece is Xen COLO have own
COLO-frame to handle live migration related function, so we need this
series make Xen COLO frame
From: Stephen Checkoway
After a flash device enters CFI mode from autoselect mode, the reset
command returns the device to autoselect mode. An additional reset
command is necessary to return to read array mode.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-7-stephen.checko.
From: Stefano Garzarella
Use the glib function to split host address and port in
the parse_host_port() function.
Suggested-by: Markus Armbruster
Signed-off-by: Stefano Garzarella
Reviewed-by: Markus Armbruster
Signed-off-by: Jason Wang
---
net/net.c | 43 +++-
Extract the pflash_regions_count() function, the code will be
easier to review.
Reviewed-by: Alistair Francis
Message-Id: <20190627202719.17739-20-phi...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
Extract the code block in a new function, remove a goto statement.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch, remove the XXX tracing
The 'page mode' feature entry was implicitly set as zero
(not supported). Document it exists, so we won't discard
it if we squeeze the CFI table.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-6-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Phi
Parallel NOR flashes are limited to 16-bit bus accesses.
Remove the 32-bit dead code.
Reviewed-by: Alistair Francis
Message-Id: <20190627202719.17739-29-phi...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
From: Stephen Checkoway
When the flash device is performing a chip erase, all commands are
ignored. When it is performing a sector erase, only the erase suspend
command is valid, which is currently not supported.
In particular, the reset command should not cause the device to reset to
read array
Manufacturers are allowed to move the PRI table, this is why the
offset is queryable via fixed offsets 0x15/0x16.
Add a variable to hold the offset, so it will be easier to later
move the PRI table.
Reviewed-by: Alistair Francis
Message-Id: <20190627202719.17739-17-phi...@redhat.com>
Signed-off-b
From: Stephen Checkoway
During a sector erase (but not a chip erase), the embeded erase program
can be suspended. Once suspended, the sectors not selected for erasure
may be read and programmed. Autoselect mode is allowed during erase
suspend mode. Presumably, CFI queries are similarly allowed so
The pflash_read()/pflash_write() can check the device endianess
via the pfl->be variable, so remove the 'int be' argument.
Since the big/little MemoryRegionOps are now identical, it is
pointless to declare them both. Unify them.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-6-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch]
Acked-by: Alistair Francis
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 11 ++-
1 file chang
The load/store API eases code review.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch, simplified tracing]
Reviewed-by: Alistair Francis
S
We can directly use pfl->total_len, remove the local 'chip_len'
variable.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-6-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch]
Reviewed-by: Ali
From: Stephen Checkoway
After two unlock cycles and a sector erase command, the AMD flash chips
start a 50 us erase time out. Any additional sector erase commands add a
sector to be erased and restart the 50 us timeout. During the timeout,
status bit DQ3 is cleared. After the time out, DQ3 is ass
The load/store API eases code review.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch]
Reviewed-by: Alistair Francis
Signed-off-by: Philip
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