Markus Armbruster writes:
> There are just two HMP commands related to QOM: qom-list and qom-set.
> Move their handlers from monitor/hmp-cmds.c to new qom/qom-hmp-cmds.c,
> where they are covered by MAINTAINERS section QOM.
Actually three: hmp_info_qom_tree(). I'm squashing the obvious
Le 25/06/2019 à 16:27, Aleksandar Markovic a écrit :
From: Aleksandar Markovic
The size is one byte less than it should be:
address-space: rc4030-dma
-fffe (prio 0, i/o): rc4030.dma
rc4030 is used in MIPS Jazz board context.
Signed-off-by: Aleksandar Markovic
Le 25/06/2019 à 16:27, Aleksandar Markovic a écrit :
From: Aleksandar Markovic
Fix some simple checkpatch.pl warnings in rc4030.c.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Hervé Poussineau
---
hw/dma/rc4030.c | 18 +++---
1 file changed, 11 insertions(+), 7
On Wed, Jun 26, 2019 at 10:43:33AM +0530, Aravinda Prasad wrote:
>
>
> On Tuesday 25 June 2019 12:30 PM, Greg Kurz wrote:
> > On Tue, 25 Jun 2019 11:46:06 +0530
> > Aravinda Prasad wrote:
> >
> >> On Monday 24 June 2019 07:59 PM, Greg Kurz wrote:
> >>> On Wed, 12 Jun 2019 14:51:38 +0530
> >>>
On Wed, Jun 12, 2019 at 02:51:13PM +0530, Aravinda Prasad wrote:
> Memory error such as bit flips that cannot be corrected
> by hardware are passed on to the kernel for handling.
> If the memory address in error belongs to guest then
> the guest kernel is responsible for taking suitable action.
>
On 7/1/19 8:12 PM, Philippe Mathieu-Daudé wrote:
> When the state machine is ready to accept command, the bit 7 of
> the status register (SR) is set to 1.
> The guest polls the status register and check this bit before
> writting command to the internal 'Write State Machine' (WSM).
writing
>
On 7/1/19 8:12 PM, Philippe Mathieu-Daudé wrote:
> The same pattern is used when setting the flash in READ_ARRAY mode:
> - Set the state machine command to READ_ARRAY
> - Reset the write_cycle counter
> - Reset the memory region in ROMD
>
> Refactor the current code by extracting this pattern.
Peter Maydell writes:
> On Mon, 1 Jul 2019 at 18:50, Alistair Francis
> wrote:
>>
>> On Mon, 2019-07-01 at 17:54 +0100, Peter Maydell wrote:
>> > On Thu, 27 Jun 2019 at 16:24, Palmer Dabbelt
>> > wrote:
>> > > From: Alistair Francis
>> > >
>> > > Add OpenSBI version 0.3 as a git submodule
On 7/1/19 8:12 PM, Philippe Mathieu-Daudé wrote:
> In the "Read Array Flowchart" the command has a value of 0xFF.
>
> In the document [*] the "Read Array Flowchart", the READ_ARRAY
> command has a value of 0xff.
>
> Use the correct value in the pflash model.
>
> There is no change of
The following changes since commit 7d0e02405fc02a181319b1ab8681d2f72246b7c6:
Merge remote-tracking branch
'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2019-07-01
17:40:32 +0100)
are available in the Git repository at:
https://github.com/XanClic/qemu.git
On Wed, Jun 12, 2019 at 02:51:21PM +0530, Aravinda Prasad wrote:
> Upon a machine check exception (MCE) in a guest address space,
> KVM causes a guest exit to enable QEMU to build and pass the
> error to the guest in the PAPR defined rtas error log format.
>
> This patch builds the rtas error
On Wed, Jun 12, 2019 at 02:51:04PM +0530, Aravinda Prasad wrote:
> Introduce the KVM capability KVM_CAP_PPC_FWNMI so that
> the KVM causes guest exit with NMI as exit reason
> when it encounters a machine check exception on the
> address belonging to a guest. Without this capability
> enabled, KVM
From: Andrey Shinkevich
The bottom node is the intermediate block device that has the base as its
backing image. It is used instead of the base node while a block stream
job is running to avoid dependency on the base that may change due to the
parallel jobs. The change may take place due to a
From: Zhang Chen
Add chardev handler to send notification to remote(current from Xen) colo-frame.
Signed-off-by: Zhang Chen
Signed-off-by: Jason Wang
---
net/colo-compare.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/net/colo-compare.c
On Wed, Jun 12, 2019 at 02:51:38PM +0530, Aravinda Prasad wrote:
> This patch adds support in QEMU to handle "ibm,nmi-register"
> and "ibm,nmi-interlock" RTAS calls and sets the default
> value of SPAPR_CAP_FWNMI_MCE to SPAPR_CAP_ON for machine
> type 4.0.
>
> The machine check notification
On Mon, 1 Jul 2019 at 22:54, Peter Maydell wrote:
>
> On Sun, 30 Jun 2019 at 11:21, Hongbo Zhang wrote:
> >
> > For the Aarch64, there is one machine 'virt', it is primarily meant to
> > run on KVM and execute virtualization workloads, but we need an
> > environment as faithful as possible to
From: Zhang Chen
We need to notify net filter to do checkpoint for Xen COLO, like KVM side.
Signed-off-by: Zhang Chen
Signed-off-by: Jason Wang
---
migration/colo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/migration/colo.c b/migration/colo.c
index 8c16440..9f84b1f 100644
---
From: "Dr. David Alan Gilbert"
Expand self-announce test to check we can stop an announce timer.
We set it up to send 300 packets, but after we receive
the first one we tell it to stop.
We error if:
a) We receive more than 30 of the packets
b) We're still receiving packets after a lot
From: Zhang Chen
This patch make colo-compare can send message to remote COLO frame(Xen) when
occur checkpoint.
Signed-off-by: Zhang Chen
Signed-off-by: Jason Wang
---
net/colo-compare.c | 54 --
1 file changed, 44 insertions(+), 10
On Tue, 2 Jul 2019 at 00:08, Leif Lindholm wrote:
>
> Hi Peter,
>
> On Mon, Jul 01, 2019 at 03:54:24PM +0100, Peter Maydell wrote:
> > I've pointed out a number of issues with these patches, but they
> > all turn out to be very minor (mostly fixable by moving code between
> > patch 1 and 2). The
On 7/1/19 8:12 PM, Philippe Mathieu-Daudé wrote:
> A "system reset" sets the device state machine in READ_ARRAY mode
> and, after some delay, set the SR.7 READY bit.
>
> We do not model timings, so we set the SR.7 bit directly.
>
> This pflash device is a child of TYPE_DEVICE.
> The
From: "Dr. David Alan Gilbert"
Add the optional interface list to the HMP command.
i.e.
All interfaces
announce_self
Just the named interfaces:
announce_self vn1,vn2
Signed-off-by: Dr. David Alan Gilbert
Signed-off-by: Jason Wang
---
hmp-commands.hx| 6 --
From: Zhang Chen
We add the "notify_dev=chardevID" parameter. After that colo-compare can
connect with
remote(currently just for Xen, KVM-COLO didn't need it.) colo-frame through
chardev socket,
it can notify remote(Xen) colo-frame to handle checkpoint event.
Signed-off-by: Zhang Chen
From: Stefano Garzarella
Since the get_str_sep() function is no longer used in
net/net.c, we can remove it.
Signed-off-by: Stefano Garzarella
Reviewed-by: Markus Armbruster
Signed-off-by: Jason Wang
---
net/net.c | 20
1 file changed, 20 deletions(-)
diff --git
From: Andrey Shinkevich
This patch is used in the 'block/stream: introduce a bottom node'
that is following. Instead of the base node, the caller may pass
the node that has the base as its backing image to the function
bdrv_is_allocated_above() with a new parameter include_base = true
and get
From: "Dr. David Alan Gilbert"
Add the optional ID to the HMP command.
e.g.
# start an announce for a long time on eth1
migrate_set_parameter announce-rounds 1000
announce_self "eth1" e1
# start an announce on eth2
announce_self "eth2" e2
# Change e1 to be announcing on eth1
From: Cédric Le Goater
qdev_set_nic_properties() is already used in the Aspeed SoC level to
bind the ftgmac100 device to the netdev.
This is fixing support for multiple net devices.
Signed-off-by: Cédric Le Goater
Signed-off-by: Jason Wang
---
hw/net/ftgmac100.c | 2 --
1 file changed, 2
From: "Dr. David Alan Gilbert"
Previously there was a single instance of the timer used by
monitor triggered announces, that's OK, but when combined with the
previous change that lets you have announces for subsets of interfaces
it's a bit restrictive if you want to do different things to
From: Stefano Garzarella
net_client_init() uses a variable length array to store the prefix
of 'ipv6-net' parameter (e.g. if ipv6-net=fec0::0/64, the prefix
is 'fec0::0').
This patch introduces g_strsplit() to split the 'ipv6-net' parameter,
so we can remove the variable length array.
The following changes since commit 7d0e02405fc02a181319b1ab8681d2f72246b7c6:
Merge remote-tracking branch
'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2019-07-01
17:40:32 +0100)
are available in the git repository at:
https://github.com/jasowang/qemu.git
From: Markus Armbruster
Signed-off-by: Markus Armbruster
Signed-off-by: Jason Wang
---
qemu-bridge-helper.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/qemu-bridge-helper.c b/qemu-bridge-helper.c
index f9940de..95624bc 100644
--- a/qemu-bridge-helper.c
+++
From: Andrey Shinkevich
The goto is unnecessary in the stream_run() since the common exit
code was removed in the commit eb23654dbe43b549ea2a9ebff9d8e:
"jobs: utilize job_exit shim".
Signed-off-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Andrey Shinkevich
Reviewed-by: Alberto Garcia
From: Markus Armbruster
Signed-off-by: Markus Armbruster
Signed-off-by: Jason Wang
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8206fc5..c7b0c2c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1934,6 +1934,7 @@ M: Jason Wang
S:
On 7/1/2019 7:25 PM, Igor Mammedov wrote:
On Fri, 14 Jun 2019 23:56:24 +0800
Tao Xu wrote:
From: Liu Jingqi
HMAT is defined in ACPI 6.2: 5.2.27 Heterogeneous Memory Attribute Table (HMAT).
The specification references below link:
From: Stefano Garzarella
RBD APIs don't allow us to write more than the size set with
rbd_create() or rbd_resize().
In order to support growing images (eg. qcow2), we resize the
image before write operations that exceed the current size.
Signed-off-by: Stefano Garzarella
Message-id:
From: Stefano Garzarella
If 'ipv6-prefixlen' is not a number, the current behaviour
produces an assertion failure:
$ qemu-system-x86_64 -net user,ipv6-net=feca::0/a
qemu-system-x86_64: qemu/util/qemu-option.c:1175: qemu_opts_foreach:
Assertion `!errp || !*errp' failed.
Aborted
On 7/1/2019 6:59 PM, Igor Mammedov wrote:
On Fri, 14 Jun 2019 23:56:23 +0800
Tao Xu wrote:
Add build_mem_ranges callback to AcpiDeviceIfClass and use
it for generating SRAT and HMAT numa memory ranges.
Suggested-by: Igor Mammedov
Co-developed-by: Liu Jingqi
Signed-off-by: Liu Jingqi
On Tue, Jul 2, 2019 at 8:20 AM Alistair Francis wrote:
>
> On Mon, Jul 1, 2019 at 8:56 AM wrote:
> >
> > From: Jonathan Behrens
> >
> > QEMU currently always triggers an illegal instruction exception when
> > code attempts to read the time CSR. This is valid behavor, but only if
> > the TM bit
From: Zhang Chen
We need use this function to send notification message for remote
colo-frame(Xen).
So we add new parameter for this job.
Signed-off-by: Zhang Chen
Signed-off-by: Jason Wang
---
net/colo-compare.c | 41 +
1 file changed, 33
From: Stephen Checkoway
Most AMD commands only examine 11 bits of the address. This masks the
addresses used in the comparison to 11 bits. The exceptions are word or
sector addresses which use offset directly rather than the shifted
offset, boff.
Signed-off-by: Stephen Checkoway
Message-Id:
From: "Dr. David Alan Gilbert"
Allow the caller to restrict the set of interfaces that announces are
sent on. The default is still to send on all interfaces.
e.g.
{ "execute": "announce-self", "arguments": { "initial": 50, "max": 550,
"rounds": 5, "step": 50, "interfaces": ["vn2", "vn1"] }
Reviewed-by: Alistair Francis
Message-Id: <20190627202719.17739-28-phi...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 40 +++-
1 file changed, 19 insertions(+), 21 deletions(-)
diff --git a/hw/block/pflash_cfi02.c
Introduce the FlashConfig structure, to be able to run the same set
of tests on different flash models/configurations.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-6-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD:
On 2019/6/10 上午12:44, Zhang Chen wrote:
From: Zhang Chen
Xen COLO based on KVM COLO architecture, it shared COLO proxy and block
replication with KVM COLO. The only differece is Xen COLO have own
COLO-frame to handle live migration related function, so we need this
series make Xen COLO frame
From: Stephen Checkoway
After a flash device enters CFI mode from autoselect mode, the reset
command returns the device to autoselect mode. An additional reset
command is necessary to return to read array mode.
Signed-off-by: Stephen Checkoway
Message-Id:
From: Stefano Garzarella
Use the glib function to split host address and port in
the parse_host_port() function.
Suggested-by: Markus Armbruster
Signed-off-by: Stefano Garzarella
Reviewed-by: Markus Armbruster
Signed-off-by: Jason Wang
---
net/net.c | 43
Extract the pflash_regions_count() function, the code will be
easier to review.
Reviewed-by: Alistair Francis
Message-Id: <20190627202719.17739-20-phi...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
Extract the code block in a new function, remove a goto statement.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch, remove the XXX tracing
The 'page mode' feature entry was implicitly set as zero
(not supported). Document it exists, so we won't discard
it if we squeeze the CFI table.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-6-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by:
Parallel NOR flashes are limited to 16-bit bus accesses.
Remove the 32-bit dead code.
Reviewed-by: Alistair Francis
Message-Id: <20190627202719.17739-29-phi...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 5 +
1 file changed, 1 insertion(+), 4
From: Stephen Checkoway
When the flash device is performing a chip erase, all commands are
ignored. When it is performing a sector erase, only the erase suspend
command is valid, which is currently not supported.
In particular, the reset command should not cause the device to reset to
read
Manufacturers are allowed to move the PRI table, this is why the
offset is queryable via fixed offsets 0x15/0x16.
Add a variable to hold the offset, so it will be easier to later
move the PRI table.
Reviewed-by: Alistair Francis
Message-Id: <20190627202719.17739-17-phi...@redhat.com>
From: Stephen Checkoway
During a sector erase (but not a chip erase), the embeded erase program
can be suspended. Once suspended, the sectors not selected for erasure
may be read and programmed. Autoselect mode is allowed during erase
suspend mode. Presumably, CFI queries are similarly allowed
The pflash_read()/pflash_write() can check the device endianess
via the pfl->be variable, so remove the 'int be' argument.
Since the big/little MemoryRegionOps are now identical, it is
pointless to declare them both. Unify them.
Signed-off-by: Stephen Checkoway
Message-Id:
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-6-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch]
Acked-by: Alistair Francis
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 11 ++-
1 file
The load/store API eases code review.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch, simplified tracing]
Reviewed-by: Alistair Francis
We can directly use pfl->total_len, remove the local 'chip_len'
variable.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-6-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch]
Reviewed-by:
From: Stephen Checkoway
After two unlock cycles and a sector erase command, the AMD flash chips
start a 50 us erase time out. Any additional sector erase commands add a
sector to be erased and restart the 50 us timeout. During the timeout,
status bit DQ3 is cleared. After the time out, DQ3 is
The load/store API eases code review.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch]
Reviewed-by: Alistair Francis
Signed-off-by:
Split the if() condition check and arrange the indentation to
ease the review of the next patches. No logical change.
Reviewed-by: Alistair Francis
Message-Id: <20190627202719.17739-21-phi...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 6 --
1 file
From: Stephen Checkoway
Some flash chips support sectors of different sizes. For example, the
AMD AM29LV160DT has 31 64 kB sectors, one 32 kB sector, two 8 kB
sectors, and a 16 kB sector, in that order. The AM29LV160DB has those in
the reverse order.
The `num-blocks` and `sector-length`
No change in functionality is intended with this commit.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch]
Reviewed-by: Alistair Francis
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch]
Reviewed-by: Alistair Francis
Signed-off-by: Philippe Mathieu-Daudé
---
From: Stephen Checkoway
When erasing the chip, use the typical time specified in the CFI table
rather than arbitrarily selecting 5 seconds.
Since the currently unconfigurable value set in the table is 12, this
means a chip erase takes 4096 ms so this isn't a big change in behavior.
Manufacturers are allowed to move the PRI table, this is why the
offset is queryable via fixed offsets 0x15/0x16.
Add a variable to hold the offset, so it will be easier to later
move the PRI table.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi01.c | 41
Use a field width format to have a single function to log
the different width accesses.
Reviewed-by: Alistair Francis
Message-Id: <20190627202719.17739-4-phi...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi01.c | 6 ++
hw/block/pflash_cfi02.c | 6 ++
Pull out all of the code to modify the status into simple helper
functions. Status handling becomes more complex once multiple
chips are interleaved to produce a single device.
No change in functionality is intended with this commit.
Signed-off-by: Stephen Checkoway
Message-Id:
Always compile the debug code to prevent format string to bitrot.
Delete dead code.
Signed-off-by: Stephen Checkoway
Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu>
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
[PMD: Extracted from bigger patch, use
On Mon, Jul 01, 2019 at 11:45:23AM +0200, Philippe Mathieu-Daudé wrote:
> On 7/1/19 7:04 AM, David Gibson wrote:
> > On Fri, Jun 28, 2019 at 03:20:32PM +0200, Philippe Mathieu-Daudé wrote:
> >> Hi,
> >>
> >> On 3/12/19 8:58 PM, Cédric Le Goater wrote:
> >>> On 3/12/19 8:30 PM, Cleber Rosa wrote:
>
Call the read() trace function after the value is set, so we can
log the returned value.
Rename the I/O trace functions with '_io_' in their name.
Reviewed-by: Stephen Checkoway
Reviewed-by: Alistair Francis
Message-Id: <20190627202719.17739-3-phi...@redhat.com>
Signed-off-by: Philippe
From: Stephen Checkoway
Test the AMD command set for parallel flash chips. This test uses an
ARM musicpal board with a pflash drive to test the following list of
currently-supported commands.
- Autoselect
- CFI
- Sector erase
- Chip erase
- Program
- Unlock bypass
- Reset
Signed-off-by: Stephen
A "system reset" sets the device state machine in READ_ARRAY mode
and, after some delay, set the SR.7 READY bit.
We do not model timings, so we set the SR.7 bit directly.
This pflash device is a child of TYPE_DEVICE.
The TYPE_DEVICE interface provide a DeviceReset handler which will
be called
-next-20190701
for you to fetch changes up to 3ae0343db69c379beb5750b4ed70794bbed51b85:
hw/block/pflash_cfi02: Reduce I/O accesses to 16-bit (2019-07-02 02:34:55
+0200)
Implement the following AMD command-set parallel flash
On Mon, Jul 01, 2019 at 03:22:36PM +0200, Greg Kurz wrote:
> Make kvmppc_xive_disconnect() able to undo the changes of a partial
> execution of kvmppc_xive_connect() and use it to perform rollback.
>
> Signed-off-by: Greg Kurz
> Reviewed-by: Cédric Le Goater
Applied, thanks.
> ---
>
> David,
The 'CFI02' NOR flash was introduced in commit 29133e9a0fff, with
timing modelled. One year later, the CFI01 model was introduced
(commit 05ee37ebf630) based on the CFI02 model. As noted in the
header, "It does not support timings". 12 years later, we never
had to model the device timings. Time to
On 7/1/2019 9:37 PM, Igor Mammedov wrote:
On Fri, 14 Jun 2019 23:56:18 +0800
Tao Xu wrote:
This series of patches will build Heterogeneous Memory Attribute Table (HMAT)
according to the command line. The ACPI HMAT describes the memory attributes,
such as memory side cache attributes and
The current code does:
if (write_cycle == 0)
if (command == CFI_QUERY)
break
write_cycle += 1
last_command = command
if (write_cycle == 1)
if (last_command == CFI_QUERY)
if (command == READ_ARRAY
write_cycle = 0
last_command = READ_ARRAY
Simplify by not increasing
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi01.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c
index f50d0a9d37..e891112b67 100644
--- a/hw/block/pflash_cfi01.c
+++ b/hw/block/pflash_cfi01.c
@@
-openbios-20190701
for you to fetch changes up to 9f4886430d61a4c452c0f1c6f5efeb1bc256a859:
Update OpenBIOS images to c79e0ec built from submodule. (2019-07-01 18:37:05
+0100)
qemu-openbios queue
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi01.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c
index c1b02219b2..f50d0a9d37 100644
--- a/hw/block/pflash_cfi01.c
+++ b/hw/block/pflash_cfi01.c
In the "Read Array Flowchart" the command has a value of 0xFF.
In the document [*] the "Read Array Flowchart", the READ_ARRAY
command has a value of 0xff.
Use the correct value in the pflash model.
There is no change of behavior in the guest, because:
- when the guest were sending 0xFF, the
From: John Snow
Since we're out in a new module, do a quick cursory pass of some of the
more obvious style issues.
Signed-off-by: John Snow
Message-Id: <20190627212816.27298-3-js...@redhat.com>
Signed-off-by: Eduardo Habkost
---
python/qemu/machine.py | 33 ++---
When the state machine is ready to accept command, the bit 7 of
the status register (SR) is set to 1.
The guest polls the status register and check this bit before
writting command to the internal 'Write State Machine' (WSM).
Set SR.7 bit to 1 when the device is created.
Reference: Read Array
The pflash device lacks a reset() function.
When a machine is resetted, the flash might be in an
inconsistent state, leading to unexpected behavior:
https://bugzilla.redhat.com/show_bug.cgi?id=1678713
Resolve this issue by adding a DeviceReset() handler.
Fix also two minor issues, and clean a bit
From: Igor Mammedov
python3 doesn't have raw_input(), so qmp-shell breaks.
Use input() instead and override it with raw_input()
if running on python2.
Signed-off-by: Igor Mammedov
Message-Id: <20190620154035.30989-1-imamm...@redhat.com>
Signed-off-by: Eduardo Habkost
---
The same pattern is used when setting the flash in READ_ARRAY mode:
- Set the state machine command to READ_ARRAY
- Reset the write_cycle counter
- Reset the memory region in ROMD
Refactor the current code by extracting this pattern.
It is used twice:
- On a write access (on command failure,
From: John Snow
It's not obvious that something named __init__.py actually houses
important code that isn't relevant to python packaging glue. Move the
QEMUMachine and related error classes out into their own module.
Adjust users to the new import location.
Signed-off-by: John Snow
On Mon, Jul 01, 2019 at 07:17:39PM -0400, John Snow wrote:
>
>
> On 7/1/19 5:27 PM, Eduardo Habkost wrote:
> > On Thu, Jun 27, 2019 at 05:32:17PM -0400, John Snow wrote:
> >> I didn't actually mean to retain the RFC tag, but oh well.
> >
> > I'm queueing patch 1-2 for QEMU 4.1.
> >
> > Patch 3
On 7/1/19 5:27 PM, Eduardo Habkost wrote:
> On Thu, Jun 27, 2019 at 05:32:17PM -0400, John Snow wrote:
>> I didn't actually mean to retain the RFC tag, but oh well.
>
> I'm queueing patch 1-2 for QEMU 4.1.
>
> Patch 3 will require more careful review. If you can demonstrate
> it fixes a
From: Philippe Mathieu-Daudé
Group SOFTMMU objects together.
Since PSCI is TCG specific, keep it separate.
Reviewed-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20190701132516.26392-5-phi...@redhat.com
Signed-off-by: Peter Maydell
---
target/arm/Makefile.objs | 5 -
Patchew URL: https://patchew.org/QEMU/20190701144705.102615-1-...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190701144705.102615-1-...@redhat.com
Subject: [Qemu-devel] [PATCH v2 0/4] Introduce the
On 6/28/19 12:05 PM, Wainer dos Santos Moschetta wrote:
>
> On 06/27/2019 06:28 PM, John Snow wrote:
>> It's not obvious that something named __init__.py actually houses
>> important code that isn't relevant to python packaging glue. Move the
>> QEMUMachine and related error classes out into
On Mon, 1 Jul 2019 at 17:47, Alex Bennée wrote:
>
> Otherwise the FreeBSD compiler complains about an unused variable.
>
> Signed-off-by: Alex Bennée
> ---
> migration/rdma.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/migration/rdma.c b/migration/rdma.c
> index
From: Cédric Le Goater
This will simplify the definition of new SoCs, like the AST2600 which
should use a slightly different address space and have a different set
of controllers.
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Joel Stanley
Message-id:
Pranith Kumar writes:
> On Fri, Jun 21, 2019 at 1:21 AM Alex Bennée wrote:
>
>> > * Register and memory read/write API
>> >
>> > It would be great to have register and memory read/write API i.e.,
>> > ability
>> > to read/write to registers/memory from within the callback. This gives
>>
On 6/27/19 6:32 PM, Max Reitz wrote:
> unittest-style tests generally do not use the log file, but VM.run_job()
> can still be useful to them. Add a parameter to it that hides its
> output from the log file.
>
> Signed-off-by: Max Reitz
Wondering out loud:
can log() (and by extension
On 01/07/2019 13:34, Philippe Mathieu-Daudé wrote:
> Avoid another QOM orphean, link it back to its parent.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/misc/macio/macio.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/misc/macio/macio.c
Hi All,
You are correct, this would break Go binaries. I was planning on
submitting a PR to the Go runtime if my patch was accepted to QEMU. The Go
PR would ignore the failure to register a handler for SIGRTMAX - 1, just as
it currently ignores the failure on SIGRTMAX (
From: Christian Svensson
If the host decrements the counter register that results in a negative
delta. This is then passed to muldiv64 which only handles unsigned
numbers resulting in bogus results.
This fix ensures the delta being operated on is positive.
Test case: kexec a kernel using
From: Philippe Mathieu-Daudé
The vfp_set_fpscr() helper contains code specific to the host
floating point implementation (here the SoftFloat library).
Extract this code to vfp_set_fpscr_from_host().
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20190701132516.26392-17-phi...@redhat.com
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