On 8/14/19 8:14 AM, luoyi...@cmss.chinamobile.com wrote:
> There is a possible memory leak in get_uuid(). Should free allocated mem
> before
> return NULL.
>
> Signed-off-by: Yifan Luo
> ---
> pc-bios/s390-ccw/netmain.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/pc-bios/s390-ccw/
Patchew URL:
https://patchew.org/QEMU/20190813210539.31164-1-shameerali.kolothum.th...@huawei.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ==
13 авг. 2019 г. 19:32 пользователь Vladimir Sementsov-Ogievskiy
написал:
13.08.2019 19:08, Kevin Wolf wrote:
> Am 13.08.2019 um 17:54 hat Vladimir Sementsov-Ogievskiy geschrieben:
>> 13.08.2019 18:41, Kevin Wolf wrote:
>>> Am 13.08.2019 um 16:43 hat Max Reitz geschrieben:
On 13.08.19 13:0
This patch includes migration support for machine check
handling. Especially this patch blocks VM migration
requests until the machine check error handling is
complete as (i) these errors are specific to the source
hardware and is irrelevant on the target hardware,
(ii) these errors cause data corr
Memory error such as bit flips that cannot be corrected
by hardware are passed on to the kernel for handling.
If the memory address in error belongs to guest then
the guest kernel is responsible for taking suitable action.
Patch [1] enhances KVM to exit guest with exit reason
set to KVM_EXIT_NMI in
Introduce the KVM capability KVM_CAP_PPC_FWNMI so that
the KVM causes guest exit with NMI as exit reason
when it encounters a machine check exception on the
address belonging to a guest. Without this capability
enabled, KVM redirects machine check exceptions to
guest's 0x200 vector.
This patch als
Upon a machine check exception (MCE) in a guest address space,
KVM causes a guest exit to enable QEMU to build and pass the
error to the guest in the PAPR defined rtas error log format.
This patch builds the rtas error log, copies it to the rtas_addr
and then invokes the guest registered machine c
This patch adds support in QEMU to handle "ibm,nmi-register"
and "ibm,nmi-interlock" RTAS calls and sets the default
value of SPAPR_CAP_FWNMI_MCE to SPAPR_CAP_ON for machine
type 4.2.
The machine check notification address is saved when the
OS issues "ibm,nmi-register" RTAS call.
This patch also
This patch set adds support for FWNMI in PowerKVM guests.
System errors such as SLB multihit and memory errors
that cannot be corrected by hardware is passed on to
the kernel for handling by raising machine check
exception (an NMI). Upon such machine check exceptions,
if the address in error belon
Introduce a wrapper function to wait on condition for
the main loop mutex. This function atomically releases
the main loop mutex and causes the calling thread to
block on the condition. This wrapper is required because
qemu_global_mutex is a static variable.
Signed-off-by: Aravinda Prasad
Reviewe
On 8/14/2019 10:39 AM, Dan Williams wrote:
On Tue, Aug 13, 2019 at 8:00 AM Igor Mammedov wrote:
On Fri, 9 Aug 2019 14:57:25 +0800
Tao wrote:
From: Tao Xu
In ACPI 6.3 chapter 5.2.27 Heterogeneous Memory Attribute Table (HMAT),
The initiator represents processor which access to memory. And
On Tuesday 13 August 2019 07:47 PM, David Gibson wrote:
> On Tue, Aug 13, 2019 at 01:00:24PM +0530, Aravinda Prasad wrote:
>>
>>
>> On Monday 12 August 2019 03:38 PM, David Gibson wrote:
>>> On Mon, Aug 05, 2019 at 02:14:39PM +0530, Aravinda Prasad wrote:
Alexey/David,
With the SL
On Tue, Aug 13, 2019 at 05:46:04PM +0100, Peter Maydell wrote:
> On Tue, 13 Aug 2019 at 17:44, Cédric Le Goater wrote:
> >
> > If an IRQ is allocated and not configured, such as a MSI requested by
> > a PCI driver, it can be saved in its default state and possibly later
> > on restored using the s
On 8/13/2019 11:11 PM, Eric Blake wrote:
On 8/9/19 1:57 AM, Tao wrote:
From: Liu Jingqi
Add -numa hmat-lb option to provide System Locality Latency and
Bandwidth Information. These memory attributes help to build
System Locality Latency and Bandwidth Information Structure(s)
in ACPI Heterogene
On Tue, Aug 13, 2019 at 8:00 AM Igor Mammedov wrote:
>
> On Fri, 9 Aug 2019 14:57:25 +0800
> Tao wrote:
>
> > From: Tao Xu
> >
> > In ACPI 6.3 chapter 5.2.27 Heterogeneous Memory Attribute Table (HMAT),
> > The initiator represents processor which access to memory. And in 5.2.27.3
> > Memory Pr
I do not have a test case to reproduce this issue. It is seen rarely. The fix
looks good to me, will confirm if I am able to reproduce the error scenario.
Regards
Shaju
On 8/14/19, 4:21 AM, "John Snow" wrote:
On 7/7/19 10:55 PM, shaju.abra...@nutanix.com wrote:
> From: Shaju
On 8/13/2019 11:00 PM, Igor Mammedov wrote:
On Fri, 9 Aug 2019 14:57:25 +0800
Tao wrote:
From: Tao Xu
In ACPI 6.3 chapter 5.2.27 Heterogeneous Memory Attribute Table (HMAT),
The initiator represents processor which access to memory. And in 5.2.27.3
Memory Proximity Domain Attributes Structu
Signed-off-by: Juan Quintela
---
migration/ram.c| 3 +++
migration/trace-events | 4
2 files changed, 7 insertions(+)
diff --git a/migration/ram.c b/migration/ram.c
index f1aec95f83..25a211c3fb 100644
--- a/migration/ram.c
+++ b/migration/ram.c
@@ -1173,6 +1173,7 @@ static void *mul
When we have lots of channels, sometimes multifd migration fails
with the following error:
(qemu) migrate -d tcp:0:
(qemu) qemu-system-x86_64: multifd_send_pages: channel 17 has already quit!
qemu-system-x86_64: multifd_send_pages: channel 17 has already quit!
qemu-system-x86_64: multifd_send_
This makes it clear that no thread handles any incoming message until
all threads have been created.
Signed-off-by: Juan Quintela
---
migration/ram.c| 24 ++--
migration/trace-events | 1 +
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/migration/ram
If we start the migration before all have been created, we have to
handle the case that one channel still don't exist. This way it is
easier.
Signed-off-by: Juan Quintela
---
migration/ram.c| 14 ++
migration/trace-events | 1 +
2 files changed, 15 insertions(+)
diff --git
Signed-off-by: Juan Quintela
---
migration/ram.c| 4
migration/trace-events | 2 ++
2 files changed, 6 insertions(+)
diff --git a/migration/ram.c b/migration/ram.c
index 889148dd84..ca11d43e30 100644
--- a/migration/ram.c
+++ b/migration/ram.c
@@ -996,6 +996,8 @@ static void multifd
Hi
When we have much more channels than cpus, we end having failures when
writting to sockets. This series:
- add some traces
- fix some of the trouble with serialization of creating the
threads/channels in proper order.
- Ask for help with the last patch. See documentation there.
Please, revi
This makes easy to debug things because when you want for all threads
to arrive at that semaphore, you know which one your are waiting for.
Signed-off-by: Juan Quintela
---
migration/ram.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/migration/ram.c b/migrat
Hi Palmer,
On Tue, Aug 13, 2019 at 11:18 PM Palmer Dabbelt wrote:
>
> On Wed, 31 Jul 2019 05:49:15 PDT (-0700), bmeng...@gmail.com wrote:
> > This adds 'info mem' command for RISC-V, to show virtual memory
> > mappings that aids debugging.
> >
> > Rather than showing every valid PTE, the command
On Wed, 14 Aug 2019, at 07:30, Alistair Francis wrote:
> On Fri, Aug 9, 2019 at 12:01 AM Tao wrote:
> >
> > From: Tao Xu
> >
> > In struct arm_boot_info, kernel_filename, initrd_filename and
> > kernel_cmdline are copied from from MachineState. This patch add
> > MachineState as a parameter in
All current bitmap_set test cases set range across word, while the
handle of a range within one word is different from that.
Add case to set 1 bit as a represent for set range within one word.
Signed-off-by: Wei Yang
---
Thanks for Paolo's finding.
---
tests/test-bitmap.c | 12
1
On 8/13/19 5:44 PM, John Snow wrote:
> This is for the purpose of toggling on/off persistence on a bitmap.
> This enables you to save a bitmap that was not persistent, but may
> have already accumulated valuable data.
>
> This is simply a QOL enhancement:
> - Allows user to "upgrade" an existing b
On Tue, 13 Aug 2019 09:52:13 PDT (-0700), alistai...@gmail.com wrote:
On Tue, Aug 13, 2019 at 6:00 AM Peter Maydell wrote:
On Mon, 12 Aug 2019 at 09:38, Peter Maydell wrote:
>
> On Sun, 11 Aug 2019 at 08:17, Bin Meng wrote:
> >
> > Hi Palmer,
> >
> > On Tue, Aug 6, 2019 at 1:04 AM Alistair F
On Fri, 09 Aug 2019 18:55:42 PDT (-0700), alistai...@gmail.com wrote:
On Fri, Aug 9, 2019 at 2:22 AM Alex Bennée wrote:
We should avoid including the whole of softfloat headers in cpu.h and
explicitly include it only where we will be calling softfloat
functions. We can use the -types.h and -he
Patchew URL: https://patchew.org/QEMU/20190813225307.5792-1-pal...@sifive.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v2] RISC-V: Ignore the S and U letters when
formatting ISA strings
Message-id: 201908132
The ISA strings we're providing from QEMU aren't actually legal RISC-V
ISA strings, as both S and U cannot exist as single-letter extensions
and must instead be multi-letter strings. We're still using the ISA
strings inside QEMU to track the availiable extensions, so this patch
just strips out the
On Wed, 07 Aug 2019 10:54:52 PDT (-0700), alistai...@gmail.com wrote:
On Wed, Aug 7, 2019 at 8:00 AM Palmer Dabbelt wrote:
The ISA strings we're providing from QEMU aren't actually legal RISC-V
ISA strings, as both the S and U extensions cannot exist as
single-letter extensions and must instea
On 7/7/19 10:55 PM, shaju.abra...@nutanix.com wrote:
> From: Shaju Abraham
>
> During the IDE DMA transfer for a ISCSI target,when libiscsi encounters
> a SENSE KEY error, it sets the task->sense to the value "COMMAND ABORTED".
> The function iscsi_translate_sense() later translaters this er
On 8/13/19 6:40 PM, John Snow wrote:
>
>
> On 7/29/19 5:34 PM, Paolo Bonzini wrote:
>> dma_aio_cancel unschedules the BH if there is one, which corresponds
>> to the reschedule_dma case of dma_blk_cb. This can stall the DMA
>> permanently, because dma_complete will never get invoked and there
On 7/29/19 6:36 PM, John Snow wrote:
> This reverts commit 0d910cfeaf2076b116b4517166d5deb0fea76394.
>
> It's not correct to just ignore an error code in a callback; we need to
> handle that error and possible report failure to the guest so that they
> don't wait indefinitely for an operation t
This is for the purpose of toggling on/off persistence on a bitmap.
This enables you to save a bitmap that was not persistent, but may
have already accumulated valuable data.
This is simply a QOL enhancement:
- Allows user to "upgrade" an existing bitmap to persistent
- Allows user to "downgrade"
On Thu, 01 Aug 2019 08:39:17 PDT (-0700), Peter Maydell wrote:
On Wed, 3 Jul 2019 at 09:41, Palmer Dabbelt wrote:
From: Michael Clark
This patch adds support for the riscv_cpu_unassigned_access call
and will raise a load or store access fault.
Signed-off-by: Michael Clark
[Changes by AF:
On 7/29/19 5:34 PM, Paolo Bonzini wrote:
> dma_aio_cancel unschedules the BH if there is one, which corresponds
> to the reschedule_dma case of dma_blk_cb. This can stall the DMA
> permanently, because dma_complete will never get invoked and therefore
> nobody will ever invoke the original AIO
On 8/13/19 10:48 AM, Max Reitz wrote:
> On 12.08.19 23:45, John Snow wrote:
>>
>>
>> On 8/12/19 3:11 PM, Max Reitz wrote:
>>> On 12.08.19 20:39, John Snow wrote:
On 7/25/19 11:55 AM, Max Reitz wrote:
> Hi,
>
> 69f47505ee66afaa513305de0c1895a224e52c45 changed block_stat
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
sixth release candidate for the QEMU 4.1 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu-project.org/qemu-4.1.0-rc5.tar.xz
http://downl
On 8/13/19 10:00 AM, Max Reitz wrote:
> On 12.08.19 23:33, John Snow wrote:
>>
>>
>> On 7/25/19 11:57 AM, Max Reitz wrote:
>>> Several vmdk subformats do not work with iotest 126, so disable them.
>>>
>>> (twoGbMaxExtentSparse actually should work, but fixing that is a bit
>>> difficult. The pr
On Fri, Aug 9, 2019 at 12:01 AM Tao wrote:
>
> From: Tao Xu
>
> In struct arm_boot_info, kernel_filename, initrd_filename and
> kernel_cmdline are copied from from MachineState. This patch add
> MachineState as a parameter into arm_load_dtb() and move the copy chunk
> of kernel_filename, initrd_f
CCing ARM maintainers. I'd like to at least get one Acked-by from
them before queueing this on machine-next.
On Fri, Aug 09, 2019 at 02:57:21PM +0800, Tao wrote:
> From: Tao Xu
>
> In struct arm_boot_info, kernel_filename, initrd_filename and
> kernel_cmdline are copied from from MachineStat
On 30.07.19 16:18, Vladimir Sementsov-Ogievskiy wrote:
> Further patch will run partial requests of iterations of
> qcow2_co_preadv in parallel for performance reasons. To prepare for
> this, separate part which may be parallelized into separate function
> (qcow2_co_preadv_task).
>
> While being h
This patch is in preparation for adding numamem and memhp tests
to arm/virt board so that 'make check' is happy. This may not
be required once the scripts are run and new tables are
generated with ".numamem" and ".memhp" extensions.
Signed-off-by: Shameer Kolothum
---
I am not sure this is the ri
Generate Memory Affinity Structures for PC-DIMM ranges.
Also, Linux and Windows need ACPI SRAT table to make memory hotplug
work properly, however currently QEMU doesn't create SRAT table if
numa options aren't present on CLI. Hence add support(>=4.2) to
create numa node automatically (auto_enable
For machines 4.2 or higher with ACPI boot use GED for system_powerdown
event instead of GPIO. Guest boot with DT still uses GPIO.
Signed-off-by: Shameer Kolothum
---
v8 --> v9
-Re-arranged patches 8 & 9 from v8 based on Igor's comments.
v7 --> v8
-Retained gpio based system_powerdown support f
This adds numamem and memhp tests for arm/virt platform
Signed-off-by: Shameer Kolothum
---
tests/bios-tables-test-allowed-diff.h | 1 +
tests/bios-tables-test.c | 49 +++
2 files changed, 50 insertions(+)
diff --git a/tests/bios-tables-test-allowed-diff.h
This is in preparation to create ACPI GED device as we
need to disable it for <4.2 for migration to work.
Signed-off-by: Shameer Kolothum
Reviewed-by: Igor Mammedov
---
hw/arm/virt.c | 9 -
hw/core/machine.c | 3 +++
include/hw/boards.h | 3 +++
3 files changed, 14 insertions(+)
This series is an attempt to provide device memory hotplug support
on ARM virt platform. This is based on Eric's recent works here[1]
and carries some of the pc-dimm related patches dropped from his
series.
The kernel support for arm64 memory hot add was added recently by
Robin and hence the gues
Documents basic concepts of ACPI Generic Event device(GED)
and interface between QEMU and the ACPI BIOS.
Signed-off-by: Shameer Kolothum
---
docs/specs/acpi_hw_reduced_hotplug.txt | 60 ++
1 file changed, 60 insertions(+)
create mode 100644 docs/specs/acpi_hw_reduced_hot
This is in preparation of using GED device for
system_powerdown event. Make the powerdown notifier
registration independent of create_gpio() fn.
Signed-off-by: Shameer Kolothum
---
hw/arm/virt.c | 12
include/hw/arm/virt.h | 1 +
2 files changed, 5 insertions(+), 8 deletion
From: Samuel Ortiz
The ACPI Generic Event Device (GED) is a hardware-reduced specific
device[ACPI v6.1 Section 5.6.9] that handles all platform events,
including the hotplug ones. This patch generates the AML code that
defines GEDs.
Platforms need to specify their own GED Event bitmap to describ
This initializes the GED device with base memory and irq, configures
ged memory hotplug event and builds the corresponding aml code. With
this, both hot and cold plug of device memory is enabled now for Guest
with ACPI boot.
Memory cold plug support with Guest DT boot is not yet supported.
Signed
From: Eric Auger
This patch adds the memory hot-plug/hot-unplug infrastructure
in machvirt. The device memory is not yet exposed to the Guest
either through DT or ACPI and hence both cold/hot plug of memory
is explicitly disabled for now.
Signed-off-by: Eric Auger
Signed-off-by: Kwangwoo Lee
S
From: Samuel Ortiz
With Hardware-reduced ACPI, the GED device will manage ACPI
hotplug entirely. As a consequence, make the memory specific
events AML generation optional. The code will only be added
when the method name is not NULL.
Signed-off-by: Samuel Ortiz
Signed-off-by: Shameer Kolothum
This is in preparation for adding support for ARM64 platforms
where it doesn't use port mapped IO for ACPI IO space. We are
making changes so that MMIO region can be accommodated
and board can pass the base address into the aml build function.
Also move few MEMORY_* definitions to header so that o
On 30.07.19 16:18, Vladimir Sementsov-Ogievskiy wrote:
> Common interface for aio task loops. To be used for improving
> performance of synchronous io loops in qcow2, block-stream,
> copy-on-read, and may be other places.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
Looks good to me ove
On 26.06.19 14:39, Sam Eiderman wrote:
> v1:
>
> Non-standard logical geometries break under QEMU.
>
> A virtual disk which contains an operating system which depends on
> logical geometries (consistent values being reported from BIOS INT13
> AH=08) will most likely break under QEMU/SeaBIOS if it
On 26.06.19 14:39, Sam Eiderman wrote:
> We will need to add LCHS removal logic to scsi-hd's unrealize() in the
> next commit.
>
> Reviewed-by: Karl Heubaum
> Reviewed-by: Arbel Moshe
> Signed-off-by: Sam Eiderman
> ---
> hw/scsi/scsi-bus.c | 15 +++
> include/hw/scsi/scsi.h |
On 26.06.19 14:39, Sam Eiderman wrote:
> Relevant devices are:
> * ide-hd (and ide-cd, ide-drive)
> * scsi-hd (and scsi-cd, scsi-disk, scsi-block)
> * virtio-blk-pci
>
> We do not call del_boot_device_lchs() for ide-* since we don't need to -
> IDE block devices do not support unpluggi
* Singh, Brijesh (brijesh.si...@amd.com) wrote:
> When memory encryption is enabled, the hypervisor maintains a page
> encryption bitmap which is referred by hypervisor during migratoin to check
> if page is private or shared. The bitmap is built during the VM bootup and
> must be migrated to the t
On Fri, 2019-08-09 at 10:04 +0100, Stefan Hajnoczi wrote:
> On Mon, Aug 05, 2019 at 07:11:05AM +, Oleinik, Alexander wrote:
> > Signed-off-by: Alexander Oleinik
> > ---
> > util/module.c | 7 +++
> > 1 file changed, 7 insertions(+)
>
> Why is this necessary? Existing callers only invoke
On 26.06.19 14:39, Sam Eiderman wrote:
> Add an interface to provide direct logical CHS values for boot devices.
> We will use this interface in the next commits.
>
> Reviewed-by: Karl Heubaum
> Reviewed-by: Arbel Moshe
> Signed-off-by: Sam Eiderman
> ---
> bootdevice.c| 55
>
On Mon, 2019-08-12 at 18:39 -0400, Bandan Das wrote:
> "Oleinik, Alexander" writes:
> ...
> > if test "$supported_cpu" = "no"; then
> > echo
> > @@ -7306,6 +7310,17 @@ fi
> > if test "$sheepdog" = "yes" ; then
> >echo "CONFIG_SHEEPDOG=y" >> $config_host_mak
> > fi
> > +if test "$fuzzin
On 8/13/19 5:07 AM, Gerd Hoffmann wrote:
> Simplifies sending security patches to all people listed in
> https://wiki.qemu.org/SecurityProcess. Should also make it
> harder to send a copy to the mailing list by accident.
>
> Signed-off-by: Gerd Hoffmann
> ---
> .gitpublish | 12
In some cases buf_align or request_alignment cannot be detected:
1. With Gluster, buf_align cannot be detected since the actual I/O is
done on Gluster server, and qemu buffer alignment does not matter.
Since we don't have alignment requirement, buf_align=1 is the best
value.
2. With loca
On 8/13/19 3:30 PM, Stefan Hajnoczi wrote:
> The -usb section of the man page is not very clear on what exactly -usb
> does and fails to mention xHCI as a modern alternative (-device
> nec-usb-xhci).
>
> Signed-off-by: Stefan Hajnoczi
> ---
> qemu-options.hx | 7 +--
> 1 file changed, 5 inse
On 8/13/19 5:20 PM, Eric Blake wrote:
> On 8/13/19 4:30 AM, Thomas Huth wrote:
>> No test is using hmp() anymore, and since this function uses the disliked
>> global_qtest variable, we should also make sure that nobody adds new code
>> with this function again. qtest_hmp() should be used instead.
>
* Singh, Brijesh (brijesh.si...@amd.com) wrote:
> The sev_load_incoming_page() provide the implementation to read the
> incoming guest private pages from the socket and load it into the guest
> memory. The routines uses the RECEIVE_START command to create the
> incoming encryption context on the fi
Patchew URL:
https://patchew.org/QEMU/1565712926-21194-1-git-send-email...@us.ibm.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v2] ppc: Add support for 'mffsl' instruction
Message-id: 1565712926-21194-1-git-
On Mon, Aug 12, 2019 at 4:08 PM Palmer Dabbelt wrote:
>
> On Tue, 30 Jul 2019 16:35:34 PDT (-0700), Alistair Francis wrote:
> > From: Atish Patra
> >
> > As per the RISC-V spec, Floating Point registers are named as f0..f31
> > so lets fix the register names accordingly.
> >
> > Signed-off-by: At
Patchew URL:
https://patchew.org/QEMU/1565710319-1026-1-git-send-email...@us.ibm.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH] ppc: Add support for 'mffsl' instruction
Message-id: 1565710319-1026-1-git-send-
On Tue, Aug 13, 2019 at 6:00 AM Peter Maydell wrote:
>
> On Mon, 12 Aug 2019 at 09:38, Peter Maydell wrote:
> >
> > On Sun, 11 Aug 2019 at 08:17, Bin Meng wrote:
> > >
> > > Hi Palmer,
> > >
> > > On Tue, Aug 6, 2019 at 1:04 AM Alistair Francis
> > > wrote:
> > > >
> > > > On Fri, Aug 2, 2019
On 13.08.19 18:45, Vladimir Sementsov-Ogievskiy wrote:
> 13.08.2019 19:30, Max Reitz wrote:
>> On 13.08.19 17:32, Vladimir Sementsov-Ogievskiy wrote:
>>> 13.08.2019 18:02, Max Reitz wrote:
On 13.08.19 17:00, Vladimir Sementsov-Ogievskiy wrote:
> 13.08.2019 17:57, Max Reitz wrote:
>> On
On 13/08/2019 18:46, Peter Maydell wrote:
> On Tue, 13 Aug 2019 at 17:44, Cédric Le Goater wrote:
>>
>> If an IRQ is allocated and not configured, such as a MSI requested by
>> a PCI driver, it can be saved in its default state and possibly later
>> on restored using the same state. If not initial
On Tue, 13 Aug 2019 at 17:44, Cédric Le Goater wrote:
>
> If an IRQ is allocated and not configured, such as a MSI requested by
> a PCI driver, it can be saved in its default state and possibly later
> on restored using the same state. If not initially MASKED, KVM will
> try to find a matching pri
13.08.2019 19:30, Max Reitz wrote:
> On 13.08.19 17:32, Vladimir Sementsov-Ogievskiy wrote:
>> 13.08.2019 18:02, Max Reitz wrote:
>>> On 13.08.19 17:00, Vladimir Sementsov-Ogievskiy wrote:
13.08.2019 17:57, Max Reitz wrote:
> On 13.08.19 16:39, Vladimir Sementsov-Ogievskiy wrote:
>> 13
If an IRQ is allocated and not configured, such as a MSI requested by
a PCI driver, it can be saved in its default state and possibly later
on restored using the same state. If not initially MASKED, KVM will
try to find a matching priority/target tuple for the interrupt and
fail to restore the VM b
From: "Paul A. Clarke"
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffsl'.
'mffsl' is identical to 'mffs', except it only returns mode, status, and enable
bits from th
From: "Paul A. Clarke"
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffsl'.
'mffsl' is identical to 'mffs', except it only returns mode, status, and enable
bits from th
13.08.2019 19:08, Kevin Wolf wrote:
> Am 13.08.2019 um 17:54 hat Vladimir Sementsov-Ogievskiy geschrieben:
>> 13.08.2019 18:41, Kevin Wolf wrote:
>>> Am 13.08.2019 um 16:43 hat Max Reitz geschrieben:
On 13.08.19 13:04, Kevin Wolf wrote:
> Am 12.08.2019 um 20:11 hat Vladimir Sementsov-Ogiev
On 13.08.19 17:32, Vladimir Sementsov-Ogievskiy wrote:
> 13.08.2019 18:02, Max Reitz wrote:
>> On 13.08.19 17:00, Vladimir Sementsov-Ogievskiy wrote:
>>> 13.08.2019 17:57, Max Reitz wrote:
On 13.08.19 16:39, Vladimir Sementsov-Ogievskiy wrote:
> 13.08.2019 17:23, Max Reitz wrote:
>> On
On 13.08.19 17:41, Kevin Wolf wrote:
> Am 13.08.2019 um 16:43 hat Max Reitz geschrieben:
>> On 13.08.19 13:04, Kevin Wolf wrote:
>>> Am 12.08.2019 um 20:11 hat Vladimir Sementsov-Ogievskiy geschrieben:
BDRV_BLOCK_RAW makes generic bdrv_co_block_status to fallthrough to
returned file. But
On 08/13/19 18:09, Laszlo Ersek wrote:
> On 08/13/19 16:16, Laszlo Ersek wrote:
>> (06) Host CPU: (SMM) Save 38000, Update 38000 -- fill simple SMM
>> rebase code.
>>
>> (07) Host CPU: (SMM) Send message to New CPU to Enable SMI.
>
> Aha, so this is the SMM-only register you mention in step
On 08/13/19 16:16, Laszlo Ersek wrote:
> Yingwen and Jiewen suggested the following process.
>
> Legend:
>
> - "New CPU": CPU being hot-added
> - "Host CPU": existing CPU
> - (Flash):code running from flash
> - (SMM): code running from SMRAM
>
> Steps:
>
> (01) New CPU: (Flash) enter res
Am 13.08.2019 um 17:54 hat Vladimir Sementsov-Ogievskiy geschrieben:
> 13.08.2019 18:41, Kevin Wolf wrote:
> > Am 13.08.2019 um 16:43 hat Max Reitz geschrieben:
> >> On 13.08.19 13:04, Kevin Wolf wrote:
> >>> Am 12.08.2019 um 20:11 hat Vladimir Sementsov-Ogievskiy geschrieben:
> BDRV_BLOCK_RAW
On Mon, 5 Aug 2019 17:29:47 +0200
David Hildenbrand wrote:
> We now implement a bunch of new facilities we can properly indicate.
>
> ESOP-1/ESOP-2 handling is discussed in the PoP Chafter 3-15
> ("Suppression on Protection"). The "Basic suppression-on-protection (SOP)
> facility" is a core par
On 13.08.19 17:22, Vladimir Sementsov-Ogievskiy wrote:
> 13.08.2019 18:03, Max Reitz wrote:
>> On 13.08.19 16:56, Vladimir Sementsov-Ogievskiy wrote:
>>> 13.08.2019 17:43, Max Reitz wrote:
On 13.08.19 13:04, Kevin Wolf wrote:
> Am 12.08.2019 um 20:11 hat Vladimir Sementsov-Ogievskiy geschr
On Mon, 5 Aug 2019 17:29:46 +0200
David Hildenbrand wrote:
> Setup the 4.1 compatibility model so we can add new features to the
> LATEST model.
Basically a nop for now from an outside view.
>
> Signed-off-by: David Hildenbrand
> ---
> hw/s390x/s390-virtio-ccw.c | 2 ++
> target/s390x/gen-
In my "build everything" tree, changing hw/irq.h triggers a recompile
of some 5400 out of 6600 objects (not counting tests and objects that
don't depend on qemu/osdep.h).
hw/hw.h supposedly includes it for convenience. Several other headers
include it just to get qemu_irq and.or qemu_irq_handler.
In my "build everything" tree, changing sysemu/sysemu.h triggers a
recompile of some 5400 out of 6600 objects (not counting tests and
objects that don't depend on qemu/osdep.h).
hw/qdev-core.h includes sysemu/sysemu.h since recent commit e965ffa70a
"qdev: add qdev_add_vm_change_state_handler()".
According to hw/ide/internal's file comment, only files in hw/ide/ are
supposed to include it. Drag reality slightly closer to supposition.
Three includes outside hw/ide remain: hw/arm/sbsa-ref.c,
include/hw/ide/pci.h, and include/hw/misc/macio/macio.h. Turns out
board code needs ide-internal.h
sysemu/sysemu.h is a rather unfocused dumping ground for stuff related
to the system-emulator. Evidence:
* It's included widely: in my "build everything" tree, changing
sysemu/sysemu.h still triggers a recompile of some 1100 out of 6600
objects (not counting tests and objects that don't depen
13.08.2019 18:41, Kevin Wolf wrote:
> Am 13.08.2019 um 16:43 hat Max Reitz geschrieben:
>> On 13.08.19 13:04, Kevin Wolf wrote:
>>> Am 12.08.2019 um 20:11 hat Vladimir Sementsov-Ogievskiy geschrieben:
BDRV_BLOCK_RAW makes generic bdrv_co_block_status to fallthrough to
returned file. But i
In my "build everything" tree, changing hw/hw.h triggers a recompile
of some 2600 out of 6600 objects (not counting tests and objects that
don't depend on qemu/osdep.h).
The previous commits have left only the declaration of hw_error() in
hw/hw.h. This permits dropping most of its inclusions. To
Move the HostMemoryBackend typedef from sysemu/hostmem.h to
qemu/typedefs.h. This renders a few inclusions of sysemu/hostmem.h
superfluous; drop them.
Cc: Eduardo Habkost
Cc: Igor Mammedov
Signed-off-by: Markus Armbruster
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Eduardo Habkost
Revie
sysemu/numa.h includes hw/boards.h just for the CPUArchId typedef, at
the cost of pulling in more than two dozen extra headers indirectly.
I could move the typedef from hw/boards.h to qemu/typedefs.h. But
it's used in just two headers: boards.h and numa.h.
I could move it to another header both
Commit e35704ba9c "numa: Move NUMA declarations from sysemu.h to
numa.h" left a few NUMA-related macros behind. Move them now.
Cc: Eduardo Habkost
Cc: Marcel Apfelbaum
Signed-off-by: Markus Armbruster
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Eduardo Habkost
Message-Id: <2019081205235
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