[Qemu-devel] [PATCH v5 04/30] riscv: hw: Change create_fdt() to return void

There is no need to return fdt at the end of create_fdt() because it's already saved in s->fdt. Signed-off-by: Bin Meng Reviewed-by: Chih-Min Chao Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- Changes in v5: None Changes in v4: - change create_fdt() to return void in

[Qemu-devel] [PATCH v5 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead

Replace the call to hw_error() with qemu_log_mask(LOG_GUEST_ERROR,...) in various sifive models. Signed-off-by: Bin Meng --- Changes in v5: - new patch to change to use qemu_log_mask(LOG_GUEST_ERROR,...) instead in various sifive models Changes in v4: None Changes in v3: None Changes in v2:

[Qemu-devel] [PATCH v5 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}

Current SiFive PRCI model only works with sifive_e machine, as it only emulates registers or PRCI block in the FE310 SoC. Rename the file name to make it clear that it is for sifive_e. This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables and functions. Signed-off-by: Bin Meng Reviewe

[Qemu-devel] [PATCH v5 19/30] riscv: sifive: Implement PRCI model for FU540

This adds a simple PRCI model for FU540 (sifive_u). It has different register layout from the existing PRCI model for FE310 (sifive_e). Signed-off-by: Bin Meng --- Changes in v5: - change to use defines instead of enums - change to use qemu_log_mask(LOG_GUEST_ERROR,...) in sifive_u_prci - creat

[Qemu-devel] [PATCH v5 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h

The inclusion of "target/riscv/cpu.h" is unnecessary in various sifive model drivers. Signed-off-by: Bin Meng --- Changes in v5: - new patch to remove the unnecessary include of target/riscv/cpu.h Changes in v4: None Changes in v3: None Changes in v2: None hw/riscv/sifive_prci.c | 1 - hw/ri

[Qemu-devel] [PATCH v5 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming

For hfxosccfg register programming, SIFIVE_E_PRCI_HFXOSCCFG_RDY and SIFIVE_E_PRCI_HFXOSCCFG_EN should be used. Signed-off-by: Bin Meng Acked-by: Alistair Francis Reviewed-by: Chih-Min Chao Reviewed-by: Philippe Mathieu-Daudé --- Changes in v5: None Changes in v4: None Changes in v3: None Chan

[Qemu-devel] [PATCH v5 18/30] riscv: sifive_u: Update PLIC hart topology configuration string

With heterogeneous harts config, the PLIC hart topology configuration string are "M,MS,.." because of the monitor hart #0. Suggested-by: Fabien Chouteau Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None h

[Qemu-devel] [PATCH v5 23/30] riscv: sifive_u: Update UART base addresses and IRQs

This updates the UART base address and IRQs to match the hardware. Signed-off-by: Bin Meng Reviewed-by: Jonathan Behrens Acked-by: Alistair Francis Reviewed-by: Chih-Min Chao --- Changes in v5: None Changes in v4: None Changes in v3: - update IRQ numbers of both UARTs to match hardware as we

[Qemu-devel] [PATCH v5 11/30] riscv: sifive_e: prci: Update the PRCI register block size

Currently the PRCI register block size is set to 0x8000, but in fact 0x1000 is enough, which is also what the manual says. Signed-off-by: Bin Meng Reviewed-by: Chih-Min Chao Reviewed-by: Alistair Francis --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None hw/r

[Qemu-devel] [PATCH v5 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array

At present each hart's hartid in a RISC-V hart array is assigned the same value of its index in the hart array. But for a system that has multiple hart arrays, this is not the case any more. Add a new "hartid-base" property so that hartid number can be assigned based on the property value. Signed

[Qemu-devel] [PATCH v5 16/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC

The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54 RISC-V cores. Currently the sifive_u machine only populates 4 U54 cores. Update the max cpu number to 5 to reflect the real hardware, by creating 2 CPU clusters as containers for RISC-V hart arrays to populate heterogeneous harts.

[Qemu-devel] [PATCH v5 28/30] riscv: sifive_u: Fix broken GEM support

At present the GEM support in sifive_u machine is seriously broken. The GEM block register base was set to a weird number (0x100900FC), which for no way could work with the cadence_gem model in QEMU. Not like other GEM variants, the FU540-specific GEM has a management block to control 10/100/1000M

[Qemu-devel] [PATCH v5 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines

Group SiFive E and U cpu type defines into one header file. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None include/hw/riscv/sifive_cpu.h | 31 +++

[Qemu-devel] [PATCH v5 21/30] riscv: sifive_u: Add PRCI block to the SoC

Add PRCI mmio base address and size mappings to sifive_u machine, and generate the corresponding device tree node. Signed-off-by: Bin Meng --- Changes in v5: - create sifive_u_prci block directly in the machine codes, instead of calling sifive_u_prci_create() Changes in v4: None Changes in v

[Qemu-devel] [PATCH v5 14/30] riscv: hart: Extract hart realize to a separate routine

Currently riscv_harts_realize() creates all harts based on the same cpu type given in the hart array property. With current implementation it can only create homogeneous harts. Exact the hart realize to a separate routine in preparation for supporting multiple hart arrays. Note the file header say

[Qemu-devel] [PATCH v5 24/30] riscv: sifive_u: Change UART node name in device tree

OpenSBI for fu540 does DT fix up (see fu540_modify_dt()) by updating chosen "stdout-path" to point to "/soc/serial@...", and U-Boot will use this information to locate the serial node and probe its driver. However currently we generate the UART node name as "/soc/uart@...", causing U-Boot fail to f

[Qemu-devel] [PATCH v5 25/30] riscv: roms: Update default bios for sifive_u machine

With the support of heterogeneous harts and PRCI model, it's now possible to use the OpenSBI image (PLATFORM=sifive/fu540) built for the real hardware. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None pc-

[Qemu-devel] [PATCH v5 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes

Now that we have added a PRCI node, update existing UART and ethernet nodes to reference PRCI as their clock sources, to keep in sync with the Linux kernel device tree. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v5: None Changes in v4: None Changes in v3: None Changes

[Qemu-devel] [PATCH v5 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet

In the past we did not have a model for PRCI, hence two handcrafted clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the purpose of supplying hard-coded clock frequencies. But now since we have added the PRCI support in QEMU, we don't need them any more. Signed-off-by: Bin Meng Rev

[Qemu-devel] [PATCH v5 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes

To keep in sync with Linux kernel device tree, generate hfclk and rtcclk nodes in the device tree, to be referenced by PRCI node. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c

[Qemu-devel] [PATCH v5 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP

This implements a simple model for SiFive FU540 OTP (One-Time Programmable) Memory interface, primarily for reading out the stored serial number from the first 1 KiB of the 16 KiB OTP memory reserved by SiFive for internal use. Signed-off-by: Bin Meng --- Changes in v5: - change to use defines

[Qemu-devel] [PATCH v5 30/30] riscv: sifive_u: Update model and compatible strings in device tree

This updates model and compatible strings to use the same strings as used in the Linux kernel device tree (hifive-unleashed-a00.dts). Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c

Re: [Qemu-devel] [RFC PATCH qemu] qapi: Add query-memory-checksum

Daniel P. Berrangé writes: > On Thu, Aug 22, 2019 at 04:16:53PM +0200, Markus Armbruster wrote: >> Alexey Kardashevskiy writes: >> >> > This returns MD5 checksum of all RAM blocks for migration debugging >> > as this is way faster than saving the entire RAM to a file and checking >> > that. >>

Re: [Qemu-devel] [PATCH v6 38/42] iotests: Let complete_and_wait() work with commit

09.08.2019 19:14, Max Reitz wrote: > complete_and_wait() and wait_ready() currently only work for mirror > jobs. Let them work for active commit jobs, too. > > Signed-off-by: Max Reitz > --- > tests/qemu-iotests/iotests.py | 10 +++--- > 1 file changed, 7 insertions(+), 3 deletions(-) >

Re: [Qemu-devel] [Qemu-ppc] [PULL 1/2] spapr: Reset CAS & IRQ subsystem after devices

On Thu, Aug 22, 2019 at 10:07:09PM +0200, Laurent Vivier wrote: > On 13/08/2019 08:59, David Gibson wrote: > > This fixes a nasty regression in qemu-4.1 for the 'pseries' machine, > > caused by the new "dual" interrupt controller model. Specifically, > > qemu can crash when used with KVM if a 'sys

Re: [Qemu-devel] [PATCH v1 1/1] spapr_pci: remove all child functions in function zero unplug

On Thu, Aug 22, 2019 at 04:11:45PM -0500, Eric Blake wrote: > On 8/22/19 2:59 PM, Daniel Henrique Barboza wrote: > > There is nothing wrong with how sPAPR handles multifunction PCI > > hot unplugs. The problem is that x86 does it simpler. Instead of > > removing each non-zero function and then remo

Re: [Qemu-devel] [PATCH v1 1/1] spapr_pci: remove all child functions in function zero unplug

On Thu, Aug 22, 2019 at 04:59:18PM -0300, Daniel Henrique Barboza wrote: > There is nothing wrong with how sPAPR handles multifunction PCI > hot unplugs. The problem is that x86 does it simpler. Instead of > removing each non-zero function and then removing function zero, > x86 can remove any funct

Re: [Qemu-devel] [PATCH 0/3] mailmap: Clean up

Philippe Mathieu-Daudé writes: > Trivial cleanup of .mailmap to have a nice 'git shortlog' output. > > Philippe Mathieu-Daudé (3): > mailmap: Reorder by sections > mailmap: Update philmd email address > mailmap: Add many entries to improve 'git shortlog' statistics > > .mailmap | 123 +

Re: [Qemu-devel] [PATCH v2 2/3] net/filter.c: Add Options to insert filters anywhere in the filter list

On Fri, 23 Aug 2019 03:24:02 + "Zhang, Chen" wrote: > > -Original Message- > > From: Lukas Straub [mailto:lukasstra...@web.de] > > Sent: Friday, August 16, 2019 2:49 AM > > To: qemu-devel > > Cc: Zhang, Chen ; Jason Wang > > ; Wen Congyang ; Xie > > Changlong > > Subject: [PATCH v2

Re: [Qemu-devel] [PATCH 0/2] block/file-posix: Fix xfs_write_zeroes()

Dne 22. 08. 19 v 19:09 Max Reitz napsal(a): > On 22.08.19 18:53, Paolo Bonzini wrote: >> On 22/08/19 18:26, Max Reitz wrote: >>> Lukàš ran over a nasty regression in our xfs_write_zeroes() function >>> (sorry, my fault) made apparent by a recent patch from Anton that makes >>> qcow2 images heavily

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