From: Helge Deller
The tests of the dino chip with the Online-diagnostics CD
("ODE DINOTEST") now succeeds.
Additionally add some qemu trace events.
Signed-off-by: Helge Deller
Signed-off-by: Sven Schnelle
---
MAINTAINERS | 2 +-
hw/hppa/dino.c | 94
From: Helge Deller
LASI is a built-in multi-I/O chip which supports serial, parallel,
network (Intel i82596 Apricot), sound and other functionalities.
LASI has been used in many HP PARISC machines.
This patch adds the necessary parts to allow Linux and HP-UX to detect
LASI and the network card.
This adds emulation of Artist graphics good enough
to get a Text console on both Linux and HP-UX. The
X11 server from HP-UX also works.
Signed-off-by: Sven Schnelle
---
hw/display/Kconfig |3 +
hw/display/Makefile.objs |1 +
hw/display/artist.c | 1336
Hi,
these series adds quite a lot to the HPPA emulation in QEMU:
i82596 emulation from Helge, PS/2 and Artist graphics emulation.
See https://parisc.wiki.kernel.org/index.php/Qemu for a few screenshots
of QEMU running a X11/CDE session in HP-UX.
Changes in v2:
- dropped 'hppa: remove ISA
HP-UX sends both the 'Set key make and break (0xfc) and
'Set all key typematic make and break' (0xfa). QEMU response
with 'Resend' as it doesn't handle these commands. HP-UX than
reports an PS/2 max retransmission exceeded error. Add these
commands and just reply with ACK.
Signed-off-by: Sven
(uses Alex's working email address)
On Mon, 21 Oct 2019 at 21:52, Ard Biesheuvel wrote:
>
> On Mon, 21 Oct 2019 at 19:57, Laszlo Ersek wrote:
> >
> > (+Ard, Alex)
> >
> > On 10/21/19 17:52, Richard Henderson wrote:
> > > On 10/21/19 7:58 AM, Peter Maydell wrote:
> > >> Since 2008 the
Patchew URL:
https://patchew.org/QEMU/1571685097-15175-1-git-send-email-aleksandar.marko...@rt-rk.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019
Type: series
I tested this again on the latest Qemu and Linux kernel and cannot
reproduce it anymore, so this can be closed now..
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https://bugs.launchpad.net/bugs/1792523
Title:
usb passthrough
Provides a blocking call to read a character from the console by hooking
into the console input chain. This happens *after* any uart has hooked in,
so specifying -semihost overrides input to any emulated uarts.
Signed-off-by: Keith Packard
---
hw/semihosting/console.c | 92
Dear Qemu list members,
I'm attempting to enable KVM in a Qemu-based project that is running on a
T4240RDB board. After compiling my code with the -enable-kvm option I ran
the qemu executable with the -enable-kvm option. The application exited
with the following error message: "kvm error:
https://patchwork.ozlabs.org/patch/1180363/ should fix it, a SLOF update for
QEMU is also posted
https://github.com/aik/qemu/tree/qemu-slof-20191022-branch
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The following changes since commit 7cff77c24d8f5e558cef3538a44044d66aa225a5:
spapr: Move SpaprIrq::nr_xirqs to SpaprMachineClass (2019-10-16 12:01:41
+1100)
are available in the Git repository at:
g...@github.com:aik/qemu.git tags/qemu-slof-20191022
for you to fetch changes up to
On 10/21/19 4:24 PM, Stefan Hajnoczi wrote:
> On Fri, Oct 18, 2019 at 02:55:47PM +0300, Denis Plotnikov wrote:
>> From: "Denis V. Lunev"
>>
>> Linux guests submit IO requests no longer than PAGE_SIZE * max_seg
>> field reported by SCSI controler. Thus typical sequential read with
>> 1 MB size
On 2019/10/20 上午1:38, Sven Schnelle wrote:
This adds the basic functionality to emulate a Tulip NIC.
Implemented are:
- RX and TX functionality
- Perfect Frame Filtering
- Big/Little Endian descriptor support
- 93C46 EEPROM support
- LXT970 PHY
Not implemented, mostly because i had no OS
Public bug reported:
When I want to boot anything with qemu it just stops responding.
** Affects: qemu
Importance: Undecided
Status: New
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On Tue, Oct 22, 2019 at 12:40:32PM +1100, David Gibson wrote:
> On Mon, Oct 21, 2019 at 07:32:09PM -0500, Marty E. Plummer wrote:
> > On that note, is qemu-ppc64 currently capable of running LE
> > firmware?
>
> Well.. "qemu-ppc64" as such isn't capable of running either LE or
> firmware, since
On Mon, Oct 21, 2019 at 07:32:09PM -0500, Marty E. Plummer wrote:
> On Mon, Oct 21, 2019 at 02:46:59PM +0200, Cédric Le Goater wrote:
> > On 21/10/2019 07:34, David Gibson wrote:
> > > On Sun, Oct 20, 2019 at 08:51:47AM +0200, Cédric Le Goater wrote:
> > >> On 20/10/2019 08:28, David Gibson wrote:
On 10/21/2019 8:29 PM, Igor Mammedov wrote:
On Sun, 20 Oct 2019 19:11:18 +0800
Tao Xu wrote:
In ACPI 6.3 chapter 5.2.27 Heterogeneous Memory Attribute Table (HMAT),
The initiator represents processor which access to memory. And in 5.2.27.3
Memory Proximity Domain Attributes Structure, the
On Mon, Oct 21, 2019 at 02:46:59PM +0200, Cédric Le Goater wrote:
> On 21/10/2019 07:34, David Gibson wrote:
> > On Sun, Oct 20, 2019 at 08:51:47AM +0200, Cédric Le Goater wrote:
> >> On 20/10/2019 08:28, David Gibson wrote:
> >>>
> >>> Ok. Note that the qemu emulated machine doesn't model the
On Sat, Oct 19, 2019 at 4:54 PM Philippe Mathieu-Daudé wrote:
>
> write_secondary_boot() is used in SMP configurations where the
> CPU address space might not be the main System Bus.
> The rom_add_blob_fixed_as() function allow us to specify an
> address space. Use it to write each boot blob in
On Sat, Oct 19, 2019 at 4:56 PM Philippe Mathieu-Daudé wrote:
>
> write_secondary_boot() is used in SMP configurations where the
> CPU address space might not be the main System Bus.
> The rom_add_blob_fixed_as() function allow us to specify an
> address space. Use it to write each boot blob in
On Sun, Oct 20, 2019 at 4:07 PM Philippe Mathieu-Daudé
wrote:
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/core/null-machine.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/core/null-machine.c
On Sun, Oct 20, 2019 at 4:12 PM Philippe Mathieu-Daudé
wrote:
>
> All the codebase calls memory_region_allocate_system_memory() with
> a NULL 'owner' from the board_init() function.
> Let pass a MachineState argument, and enforce the QOM ownership of
> the system memory.
>
> Signed-off-by:
On Sun, Oct 20, 2019 at 4:10 PM Philippe Mathieu-Daudé
wrote:
>
> All the memory_region_allocate_system_memory() calls are in the
> board_init() code. From the 58 calls in the repository, only
> 4 set the 'owner' parameter. It is obvious we want the Machine
> to be the owner of the RAM, so we
On Sat, Oct 19, 2019 at 4:53 PM Philippe Mathieu-Daudé wrote:
>
> The VideoCore GPU is indenpendant from the Peripheral block. In
> the next commit, we will move its instantiation to the SoC block.
> The "gpu-bus" object will not be accessible in init() but later
> in realize(). As a preliminary
On Sat, Oct 19, 2019 at 4:52 PM Philippe Mathieu-Daudé wrote:
>
> Currently all CPUs access the main system bus. Let each CPU have
> his own address space.
>
> Before:
>
> (qemu) info mtree
> address-space: memory
> - (prio 0, i/o): system
>
From: Sarah Harris
These were designed to facilitate testing but should provide enough function to
be useful in other contexts.
Only a subset of the functions of each peripheral is implemented, mainly due to
the lack of a standard way to handle electrical connections (like GPIO pins).
A simple board setup that configures an AVR CPU to run a given firmware image.
This is all that's useful to implement without peripheral emulation as AVR CPUs
include a lot of on-board peripherals.
NOTE: this is not a real board
NOTE: it's used for CPU testing
Signed-off-by: Michael
This includes:
- LSR, ROR
- ASR
- SWAP
- SBI, CBI
- BST, BLD
- BSET, BCLR
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 1123
1 file changed, 1123 insertions(+)
diff --git a/target/avr/translate.c
Signed-off-by: Michael Rolnik
---
MAINTAINERS | 9 +
arch_init.c | 2 ++
configure | 7 +++
default-configs/avr-softmmu.mak | 5 +
include/disas/dis-asm.h | 6 ++
include/sysemu/arch_init.h | 1 +
This includes:
- ADD, ADC, ADIW
- SBIW, SUB, SUBI, SBC, SBCI
- AND, ANDI
- OR, ORI, EOR
- COM, NEG
- INC, DEC
- MUL, MULS, MULSU
- FMUL, FMULS, FMULSU
- DES
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 811 +
1 file changed, 811
This includes:
- RJMP, IJMP, EIJMP, JMP
- RCALL, ICALL, EICALL, CALL
- RET, RETI
- CPSE, CP, CPC, CPI
- SBRC, SBRS, SBIC, SBIS
- BRBC, BRBS
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 542 +
1 file changed, 542
1. Avocado test
The test is based on
https://github.com/seharris/qemu-avr-tests/tree/master/free-rtos/Demo
demo which. If working correctly, prints 'ABCDEFGHIJKLMNOPQRSTUVWX' out.
it also demostrates that timer and IRQ are working
2. Boot serial test
Print out 'T' through
Co-developed-by: Richard Henderson
Co-developed-by: Michael Rolnik
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 234 +
1 file changed, 234 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index
Signed-off-by: Michael Rolnik
---
target/avr/cpu.h | 2 +-
target/avr/translate.c | 132 +
2 files changed, 133 insertions(+), 1 deletion(-)
create mode 100644 target/avr/translate.c
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index
Stubs for unimplemented instructions and helpers for instructions that need to
interact with QEMU.
SPM and WDR are unimplemented because they require emulation of complex
peripherals.
The implementation of SLEEP is very limited due to the lack of peripherals to
generate wake interrupts.
Memory
This includes:
- BREAK
- NOP
- SLEEP
- WDR
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 174 +
1 file changed, 174 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 19540634df..21ba6004ee
This includes:
- CPU data structures
- object model classes and functions
- migration functions
- GDB hooks
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
Signed-off-by: Michael Rolnik
Signed-off-by: Sarah Harris
Signed-off-by: Michael Rolnik
Acked-by: Igor Mammedov
---
This includes:
- encoding of all 16 bit instructions
- encoding of all 32 bit instructions
Signed-off-by: Michael Rolnik
---
target/avr/insn.decode | 175 +
1 file changed, 175 insertions(+)
create mode 100644 target/avr/insn.decode
diff --git
This series of patches adds 8bit AVR cores to QEMU.
All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested
yet.
However I was able to execute simple code with functions. e.g fibonacci
calculation.
This series of patches include a non real, sample board.
No fuses support
> After reading some related code, I have more questions than before, but
> let's see... As more qcow2 code was merged since, I would suggest that
> we debug the problem on commit 69f4750 (the bisection result) rather
> than on anything newer.
Okay, for all of the following I did a fresh compile
OSError can't be used like a tuple on Python 3, so change the
code to use `e.sterror` instead of `e[1]`.
Reported-by: John Snow
Signed-off-by: Eduardo Habkost
---
tests/image-fuzzer/runner.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/image-fuzzer/runner.py
Hi
On Fri, Oct 18, 2019 at 5:43 PM Marc-André Lureau
wrote:
>
> Instead, set the initial data field directly. Since it is only 256
> bytes, let's simply copy it to avoid invalid pointers issues.
Actually, the commit message is wrong. The patch used to introduce a
init_data[256] array, and copy
Patchew URL: https://patchew.org/QEMU/20191021131215.3693-1-...@kaod.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH 0/5] ppc/pnv: Add PNOR support
Type: series
Message-id: 20191021131215.3693-1-...@kaod.org
=== TEST
On Sun, Oct 20, 2019 at 4:22 PM Philippe Mathieu-Daudé
wrote:
>
> All the memory_region_allocate_system_memory() pass a MachineState
> argument. Add an assertion to ensure the new boards/machines added
> set this argument, so all system memory object have the machine as
> its QOM owner.
>
>
On Sun, Oct 20, 2019 at 4:10 PM Philippe Mathieu-Daudé
wrote:
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/lm32/lm32_boards.c | 4 ++--
> hw/lm32/milkymist.c | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git
On Sun, Oct 20, 2019 at 4:20 PM Philippe Mathieu-Daudé
wrote:
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/i386/pc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index
On Sun, Oct 20, 2019 at 4:17 PM Philippe Mathieu-Daudé
wrote:
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/hppa/machine.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
> index
On Sun, Oct 20, 2019 at 4:20 PM Philippe Mathieu-Daudé
wrote:
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/m68k/an5206.c| 2 +-
> hw/m68k/mcf5208.c | 2 +-
> hw/m68k/next-cube.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
On 10/16/19 12:41 PM, Sam Eiderman wrote:
>
> v1:
>
> Non-standard logical geometries break under QEMU.
>
> A virtual disk which contains an operating system which depends on
> logical geometries (consistent values being reported from BIOS INT13
> AH=08) will most likely break under
On Sun, Oct 20, 2019 at 4:14 PM Philippe Mathieu-Daudé
wrote:
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/cris/axis_dev88.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/cris/axis_dev88.c b/hw/cris/axis_dev88.c
>
On Mon, Oct 21, 2019 at 12:07 PM Philippe Mathieu-Daudé
wrote:
>
> Hi Peter,
>
> This series contains the ARM patches extracted from the
> "Let the machine be the owner of the system memory" series [1]
> reviewed by Richard.
>
> These are cleanups moving the creation of the system ram at
> the
Hi Richard,
On Mon, Oct 21, 2019 at 11:17:24AM -0700, Richard Henderson wrote:
> On 10/20/19 1:47 PM, Sven Schnelle wrote:
> > B160L doesn't have an ISA bus, and we no longer need it to
> > workaround missing hardware, so remove it.
> >
> > Signed-off-by: Sven Schnelle
> > ---
> >
On Sun, Oct 20, 2019 at 4:07 PM Philippe Mathieu-Daudé
wrote:
>
> Having the RAM creation code in a separate function is not
> very helpful. Move this code directly inside the board_init()
> function, this will later allow the board to have the QOM
> ownership of the RAM.
>
> Signed-off-by:
On Sun, Oct 20, 2019 at 3:59 PM Philippe Mathieu-Daudé
wrote:
>
> The SDRAM is incorrectly created in the SA1110 SoC.
> Move its creation in the board code, this will later allow the
> board to have the QOM ownership of the RAM.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair
On Sun, Oct 20, 2019 at 3:58 PM Philippe Mathieu-Daudé
wrote:
>
> IEC binary prefixes ease code review: the unit is explicit.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/arm/xilinx_zynq.c | 3 ++-
> 1 file changed, 2 insertions(+), 1
On Sun, Oct 20, 2019 at 4:02 PM Philippe Mathieu-Daudé
wrote:
>
> IEC binary prefixes ease code review: the unit is explicit.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/arm/mps2-tz.c | 3 ++-
> hw/arm/mps2.c| 3 ++-
> 2 files changed, 4
On Sat, Oct 19, 2019 at 4:49 PM Philippe Mathieu-Daudé wrote:
>
> As we are going to add more core-specific fields, add a 'cpu'
> structure and move the ARMCPU field there as 'core'.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/arm/bcm2836.c
On Mon, 21 Oct 2019 22:28:57 +0200
Jens Freimann wrote:
> On Mon, Oct 21, 2019 at 01:01:22PM -0600, Alex Williamson wrote:
> >On Mon, 21 Oct 2019 20:45:46 +0200
> >Jens Freimann wrote:
> >
> >> On Mon, Oct 21, 2019 at 08:58:23AM -0600, Alex Williamson wrote:
> >> >On Fri, 18 Oct 2019
On Sat, Oct 19, 2019 at 4:50 PM Philippe Mathieu-Daudé wrote:
>
> This file creates the BCM2836/BCM2837 blocks.
> The biggest differences with the BCM2838 we are going to add, are
> the base addresses of the interrupt controller and the peripherals.
> Add these addresses in the BCM283XInfo
On Sat, Oct 19, 2019 at 4:47 PM Philippe Mathieu-Daudé wrote:
>
> Add the 64-bit free running timer. Do not model the COMPARE register
> (no IRQ generated).
> This timer is used by Linux kernel and recently U-Boot:
>
On Sat, Oct 19, 2019 at 4:47 PM Philippe Mathieu-Daudé wrote:
>
> We will soon implement the SYS_timer. This timer is used by Linux
> in the thermal subsystem, so once available, the subsystem will be
> enabled and poll the temperature sensors. We need to provide the
> minimum required to keep
On Mon, Oct 21, 2019 at 01:01:22PM -0600, Alex Williamson wrote:
On Mon, 21 Oct 2019 20:45:46 +0200
Jens Freimann wrote:
On Mon, Oct 21, 2019 at 08:58:23AM -0600, Alex Williamson wrote:
>On Fri, 18 Oct 2019 22:20:31 +0200
>Jens Freimann wrote:
>
>> This patch adds a net_failover_pair_id
On Mon, 21 Oct 2019 at 19:57, Laszlo Ersek wrote:
>
> (+Ard, Alex)
>
> On 10/21/19 17:52, Richard Henderson wrote:
> > On 10/21/19 7:58 AM, Peter Maydell wrote:
> >> Since 2008 the tcg/LICENSE file has not changed: it claims that
> >> everything under tcg/ is BSD-licensed.
> >>
> >> This is not
From: Aleksandar Markovic
Achieves clearer code and slightly better performance.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 21 +-
target/mips/msa_helper.c | 768 +--
target/mips/translate.c |
From: Aleksandar Markovic
Achieves clearer code and slightly better performance.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 11 +-
target/mips/msa_helper.c | 386 +--
target/mips/translate.c |
From: Aleksandar Markovic
Achieves clearer code and slightly better performance.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 20 ++-
target/mips/msa_helper.c | 320 ++-
target/mips/translate.c
From: Aleksandar Markovic
Mostly fix errors and warnings reported by 'checkpatch.pl -f'.
Cc: Markus Armbruster
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.c | 123 +++
1 file changed, 74
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/mips/boston.c| 2 +-
> hw/mips/mips_fulong2e.c | 3 ++-
> hw/mips/mips_jazz.c | 2 +-
> hw/mips/mips_malta.c| 2 +-
> hw/mips/mips_mipssim.c | 2 +-
> hw/mips/mips_r4k.c | 3 ++-
> 6 files changed, 8 insertions(+), 6
From: Aleksandar Markovic
Achieves clearer code and slightly better performance.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 30 +++-
target/mips/msa_helper.c | 426 +--
target/mips/translate.c
From: Aleksandar Markovic
Achieves clearer code and slightly better performance.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 10 +++-
target/mips/msa_helper.c | 131 ++-
target/mips/translate.c
On Mon, Oct 21, 2019 at 09:19:20AM -0600, Alex Williamson wrote:
On Fri, 18 Oct 2019 22:20:40 +0200
Jens Freimann wrote:
[...]
+if (!pdev->net_failover_pair_id) {
+error_setg(>migration_blocker,
+"VFIO device doesn't support migration");
+ret =
From: Aleksandar Markovic
Mostly cosmetic changes.
v5->v6:
- minor corrections (r-b, t-b marks) in commit messages
- added patches 11 and 12
v4->v5:
- minor correction in patch on helper.c
- added patches 9 and 10
v3->v4:
- added patches 7 and 8
v2->v3:
- removed all patches
From: Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 10 -
target/mips/msa_helper.c | 108 +--
target/mips/translate.c | 32 +++---
3 files
From: Aleksandar Markovic
Mostly fix errors and warnings reported by 'checkpatch.pl -f'.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
---
target/mips/op_helper.c | 1010 +++
1 file changed, 663 insertions(+), 347 deletions(-)
From: Aleksandar Markovic
Achieves clearer code and slightly better performance.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 11 +++-
target/mips/msa_helper.c | 163 ++-
target/mips/translate.c
From: Aleksandar Markovic
Achieves clearer code and slightly better performance.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 30 +++-
target/mips/msa_helper.c | 424 +--
target/mips/translate.c
From: Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic
---
target/mips/helper.h | 12 +++-
target/mips/msa_helper.c | 169 ++-
target/mips/translate.c | 38 +--
3 files
From: Aleksandar Markovic
Aleksandar Rikalo wishes to change his primary mail address for QEMU.
Some minor line order is corrected in .mailmap to be alphabetical,
too.
Reviewed-by: Aleksandar Rikalo
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by:
Having the RAM creation code in a separate function is not
very helpful. Move this code directly inside the board_init()
function, this will later allow the board to have the QOM
ownership of the RAM.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
The SDRAM is incorrectly created in the SA1110 SoC.
Move its creation in the board code, this will later allow the
board to have the QOM ownership of the RAM.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/collie.c| 8 ++--
hw/arm/strongarm.c | 7
The SDRAM is incorrectly created in the OMAP310 SoC.
Move its creation in the board code, this will later allow the
board to have the QOM ownership of the RAM.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/omap1.c| 12 +---
hw/arm/omap_sx1.c
IEC binary prefixes ease code review: the unit is explicit.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/xilinx_zynq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index
The SDRAM is incorrectly created in the OMAP2420 SoC.
Move its creation in the board code, this will later allow the
board to have the QOM ownership of the RAM.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
v2: Move MemoryRegion sdram to struct n800_s (Richard)
---
Hi Peter,
This series contains the ARM patches extracted from the
"Let the machine be the owner of the system memory" series [1]
reviewed by Richard.
These are cleanups moving the creation of the system ram at
the board level. The other series will enforce
memory_region_allocate_system_memory()
IEC binary prefixes ease code review: the unit is explicit.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/mps2-tz.c | 3 ++-
hw/arm/mps2.c| 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index
On Mon, 21 Oct 2019 20:45:46 +0200
Jens Freimann wrote:
> On Mon, Oct 21, 2019 at 08:58:23AM -0600, Alex Williamson wrote:
> >On Fri, 18 Oct 2019 22:20:31 +0200
> >Jens Freimann wrote:
> >
> >> This patch adds a net_failover_pair_id property to PCIDev which is
> >> used to link the primary
On Mon, Oct 21, 2019 at 08:58:23AM -0600, Alex Williamson wrote:
On Fri, 18 Oct 2019 22:20:31 +0200
Jens Freimann wrote:
This patch adds a net_failover_pair_id property to PCIDev which is
used to link the primary device in a failover pair (the PCI dev) to
a standby (a virtio-net-pci) device.
On 10/20/19 1:47 PM, Sven Schnelle wrote:
> #define DINO_PCI_HOST_BRIDGE(obj) \
> OBJECT_CHECK(DinoState, (obj), TYPE_DINO_PCI_HOST_BRIDGE)
>
> +#define DINO800_REGS ((DINO_TLTIM - DINO_GMASK) / 4)
> +static uint8_t reg800_keep_bits[DINO800_REGS]
> += { 1, 7, 7, 8, 7, 9, 32, 8, 30,
In reply to Kevin's comment#13:
> I find Laszlo's case with a preallocated image particularly surprising
> because the behaviour isn't supposed to have changed at all for
> preallocated images, at least if the heuristics still detects them as
> such.
But isn't that "if" at the core of this
On 10/20/19 1:47 PM, Sven Schnelle wrote:
> B160L doesn't have an ISA bus, and we no longer need it to
> workaround missing hardware, so remove it.
>
> Signed-off-by: Sven Schnelle
> ---
> hw/hppa/hppa_hardware.h | 1 -
> hw/hppa/machine.c | 32
> 2 files
(+Ard, Alex)
On 10/21/19 17:52, Richard Henderson wrote:
> On 10/21/19 7:58 AM, Peter Maydell wrote:
>> Since 2008 the tcg/LICENSE file has not changed: it claims that
>> everything under tcg/ is BSD-licensed.
>>
>> This is not true and hasn't been true for years: in 2013 we
>> accepted the
On 10/20/19 3:56 PM, Philippe Mathieu-Daudé wrote:
> All the memory_region_allocate_system_memory() pass a MachineState
> argument. Add an assertion to ensure the new boards/machines added
> set this argument, so all system memory object have the machine as
> its QOM owner.
>
> Signed-off-by:
On 10/20/19 3:56 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/sparc/leon3.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 10/20/19 3:56 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/ppc/e500.c | 3 ++-
> hw/ppc/mac_newworld.c | 3 ++-
> hw/ppc/mac_oldworld.c | 2 +-
> hw/ppc/pnv.c | 2 +-
> hw/ppc/ppc405_boards.c | 6 +++---
> hw/ppc/prep.c | 3
On 10/21/19 7:27 PM, Richard Henderson wrote:
On 10/20/19 3:56 PM, Philippe Mathieu-Daudé wrote:
@@ -73,8 +74,16 @@ static void clipper_init(MachineState *machine)
cpus[0]->env.trap_arg1 = 0;
cpus[0]->env.trap_arg2 = smp_cpus;
+/*
+ * Main memory region, 0x00...
On 10/20/19 3:56 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/lm32/lm32_boards.c | 4 ++--
> hw/lm32/milkymist.c | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
On 10/20/19 3:56 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/m68k/an5206.c| 2 +-
> hw/m68k/mcf5208.c | 2 +-
> hw/m68k/next-cube.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
On 10/20/19 3:56 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/cris/axis_dev88.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 10/20/19 3:56 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/hppa/machine.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
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