Philippe Mathieu-Daudé writes:
> On 1/7/20 2:53 PM, Alex Bennée wrote:
>> Our python3 requirements now outstrip those of the build.
>> Signed-off-by: Alex Bennée
>> ---
>> .travis.yml | 1 +
>> 1 file changed, 1 insertion(+)
>> diff --git a/.travis.yml b/.travis.yml
>> index 848a2714efe..a8
The Petitboot bootloader is way more advanced than SLOF is ever going to
be as Petitboot comes with the full-featured Linux kernel with all
the drivers, and initramdisk with quite user friendly interface.
The problem with ditching SLOF is that an unmodified pseries kernel can
either start via:
1. k
Add which features are added or removed in this version. Remove the
changed model-id in versioned CPU models.
Signed-off-by: Tao Xu
---
Changes in v2:
- correct the note of Cascadelake v3 (Xiaoyao)
---
target/i386/cpu.c | 50 +++
1 file changed, 2
This series of patches will remove MPX from Denverton, remove Remove
monitor from some CPU models. Add additional information for -cpu help
to indicate the changes in this version of CPU model.
The output is as follows:
./x86_64-softmmu/qemu-system-x86_64 -cpu help | grep "\["
x86 Broadwell-v2
Add additional information for -cpu help to indicate the changes in this
version of CPU model.
Suggested-by: Eduardo Habkost
Signed-off-by: Tao Xu
---
target/i386/cpu.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index a6
Because MPX is being removed from the linux kernel, remove MPX feature
from Denverton.
Signed-off-by: Tao Xu
---
target/i386/cpu.c | 12
1 file changed, 12 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 31556b7ec4..6981aa2a34 100644
--- a/target/i386/cpu.c
+
Add new version of Snowridge, Denverton, Opteron_G3, EPYC, and Dhyana
CPU model to remove MONITOR/MWAIT feature.
After QEMU/KVM use "-overcommit cpu-pm=on" to expose MONITOR/MWAIT
(commit id 6f131f13e68d648a8e4f083c667ab1acd88ce4cd), the MONITOR/MWAIT
feature in these CPU model is unused.
Signed-
On 08/01/2020 15:20, Alexey Kardashevskiy wrote:
>
>
> On 07/01/2020 16:54, David Gibson wrote:
>> On Tue, Jan 07, 2020 at 03:44:35PM +1100, Alexey Kardashevskiy wrote:
>>>
>>>
>>> On 06/01/2020 15:19, David Gibson wrote:
> +
> +static uint32_t client_package_to_path(const void *fdt, u
On Tue, Jan 07, 2020 at 04:58:14PM +0530, Ganesh wrote:
>
> On 1/3/20 7:55 AM, David Gibson wrote:
> > On Thu, Jan 02, 2020 at 01:21:10PM +0530, Ganesh Goudar wrote:
> > > From: Aravinda Prasad
> > >
> > > This patch includes migration support for machine check
> > > handling. Especially this pa
From: Cédric Le Goater
blk_getlength() returns an int64_t but the result is stored in a
uint32_t. Errors (negative values) won't be caught by the check in
pnv_pnor_realize() and blk_blockalign() will allocate a very large
buffer in such cases.
Fixes Coverity issue CID 1412226.
Signed-off-by: Cé
From: Cédric Le Goater
spapr_match_nvt() is a XIVE operation and is used by the machine to
look for a matching target when an event notification is being
delivered. An assert checks that spapr_match_nvt() is called only when
the machine has selected the XIVE interrupt mode but it is redundant
wit
From: Greg Kurz
The proper way to do that would be to use device_class_set_parent_realize(),
but defining a Pnv8PsiClass and a Pnv9PsiClass types with a parent_realize
pointer adds a fair amount of code. Calling pnv_psi_realize() explicitely
is fine for now.
This should probably be achieved with
From: Greg Kurz
In order to get rid of qdev_get_machine(), first add a pointer to the
XIVE fabric under the XIVE router and make it configurable through a
QOM link property.
Configure it in the spapr and pnv machine. In the case of pnv, the XIVE
routers are under the chip, so this is done with a
From: Greg Kurz
This allows to get rid of a call to qdev_get_machine().
Signed-off-by: Greg Kurz
Signed-off-by: Cédric Le Goater
Message-Id: <20200106145645.4539-8-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 2 +-
hw/ppc/pnv_bmc.c | 8 +---
include/hw/ppc/pnv
From: Cédric Le Goater
When updating the PNOR file contents, we should check for a possible
failure of blk_pwrite().
Fixes Coverity issue CID 1412228.
Signed-off-by: Cédric Le Goater
Message-Id: <20200107171809.15556-2-...@kaod.org>
Reviewed-by: Greg Kurz
Reviewed-by: Philippe Mathieu-Daudé
From: Greg Kurz
Now that the spapr and pnv machines do set the "xive-fabric" link, the
use of the XIVE fabric pointer becomes mandatory. This is checked with
an assert() in a new realize hook. Since the XIVE router is realized at
machine init for the all the machine's life time, no risk to abort
From: Greg Kurz
The XIVE router base class currently inherits an empty realize hook
from the sysbus device base class, but it will soon implement one
of its own to perform some sanity checks. Do the preliminary plumbing
to have it called.
Signed-off-by: Greg Kurz
Signed-off-by: Cédric Le Goater
From: Greg Kurz
And call it from a QEMU reset handler. This allows each PNV child class to
override the reset hook if needed, eg. POWER8 doesn't but POWER9 does.
The proper way to do that would be to use device_class_set_parent_reset(),
but defining a Pnv8PsiClass and a Pnv9PsiClass types with a
From: Daniel Henrique Barboza
'out' label can be replaced by 'return -1' in all cases.
CC: David Gibson
CC: qemu-...@nongnu.org
Signed-off-by: Daniel Henrique Barboza
Message-Id: <20200106182425.20312-3-danielhb...@gmail.com>
Signed-off-by: David Gibson
---
hw/ppc/ppc440_bamboo.c | 8 ++-
From: Cédric Le Goater
This will be used in subsequent patches to access the XIVE associated to
a TCTX without reaching out to the machine through qdev_get_machine().
Signed-off-by: Cédric Le Goater
[ groug: - split patch
- write subject and changelog ]
Signed-off-by: Greg Kurz
Signed
From: Greg Kurz
And use it instead of reaching out to the machine. This allows to get rid
of a call to qdev_get_machine() and to reduce the scope of another one so
that it is only used within the argument list of error_append_hint(). This
is an acceptable tradeoff compared to all it would require
From: Laurent Vivier
Register addr 1 is defined as buffer A with handshake (vBufAH),
register addr 15 is also defined as buffer A without handshake (vBufA).
As both addresses access the same register, remove the definition of
'anh' and use only 'a' (with VIA_REG_ANH and VIA_REG_A).
Fixes: 51f23
From: Cédric Le Goater
POWER8 is the only chip using the XICS interface. Add a "xics" link
and a XICSFabric attribute under this chip to remove the use of
qdev_get_machine()
Signed-off-by: Cédric Le Goater
Reviewed-by: Greg Kurz
Reviewed-by: David Gibson
Message-Id: <20200106145645.4539-3-...
From: Greg Kurz
The number of CPU chips of the powernv machine is configurable through a
"num-chips" property. This doesn't fit well with the CPU topology, eg.
some configurations can come up with more CPUs than the maximum of CPUs
set in the toplogy. This causes assertion to be hit with mttcg:
From: Cédric Le Goater
This removes the need of the intermediate link under PSI to pass the
XICS link to the underlying ICSState object.
Signed-off-by: Cédric Le Goater
Reviewed-by: Greg Kurz
Message-Id: <20200106145645.4539-2-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv.c |
From: Bharata B Rao
Update to mainline commit: d1eef1c61974 ("Linux 5.5-rc2")
Signed-off-by: Bharata B Rao
Message-Id: <20191219031445.8949-2-bhar...@linux.ibm.com>
Signed-off-by: David Gibson
---
include/standard-headers/asm-x86/bootparam.h | 7 +-
.../infiniband/hw/vmw_pvrdma/pvrdma_dev_a
From: Bharata B Rao
Invoking KVM_SVM_OFF ioctl for TCG guests will lead to a QEMU crash.
Fix this by ensuring that we don't call KVM_SVM_OFF ioctl on TCG.
Reported-by: Alexey Kardashevskiy
Fixes: 4930c1966249 ("ppc/spapr: Support reboot of secure pseries guest")
Signed-off-by: Bharata B Rao
Me
From: Daniel Henrique Barboza
'out' can be replaced by 'return' with the appropriate
return value.
CC: David Gibson
CC: qemu-...@nongnu.org
Signed-off-by: Daniel Henrique Barboza
Message-Id: <20200106182425.20312-2-danielhb...@gmail.com>
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 9 +++
From: Greg Kurz
And use it instead of reaching out to the machine. This allows to get
rid of pnv_get_chip().
Signed-off-by: Greg Kurz
Signed-off-by: Cédric Le Goater
Message-Id: <20200106145645.4539-11-...@kaod.org>
Signed-off-by: David Gibson
---
hw/intc/pnv_xive.c | 8 ++--
hw/ppc/p
From: Greg Kurz
The XIVE router base class currently inherits an empty realize hook
from the sysbus device base class, but it will soon implement one
of its own to perform some sanity checks. Do the preliminary plumbing
to have it called.
Signed-off-by: Greg Kurz
Signed-off-by: Cédric Le Goater
From: Fabiano Rosas
The exception vector offset calculation was moved into a function but
the case when AIL=0 was not checked.
The reason we got away with this is that the sole caller of
ppc_excp_vector_offset checks the AIL before calling the function:
/* Handle AIL */
if (ail) {
From: Greg Kurz
Set it at chip creation and forward it to the cores. This allows to drop
a call to qdev_get_machine().
Signed-off-by: Greg Kurz
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Message-Id: <20200106145645.4539-7-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/p
From: Cédric Le Goater
Use container_of() instead of qdev_get_machine()
Signed-off-by: Cédric Le Goater
Reviewed-by: Greg Kurz
Signed-off-by: Cédric Le Goater
Message-Id: <20191219181155.32530-2-...@kaod.org>
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 2 +-
1 file changed, 1 insertion(+
From: Fabiano Rosas
They were added in "16415335be Use correct input constant" with a
single use in kvm_arch_pre_run but that function's implementation was
removed by "1e8f51e856 ppc: remove idle_timer logic".
Signed-off-by: Fabiano Rosas
Message-Id: <20191218014616.686124-1-faro...@linux.ibm.c
From: Bharata B Rao
A pseries guest can be run as a secure guest on Ultravisor-enabled
POWER platforms. When such a secure guest is reset, we need to
release/reset a few resources both on ultravisor and hypervisor side.
This is achieved by invoking this new ioctl KVM_PPC_SVM_OFF from the
machine
The following changes since commit 035eed4c0d257c905a556fa0f4865a0c077b4e7f:
Merge remote-tracking branch 'remotes/vivier/tags/q800-for-5.0-pull-request'
into staging (2020-01-07 17:08:21 +)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-5.0-20200
On 08/01/2020 13:30, Alexey Kardashevskiy wrote:
> +
> +uint32_t spapr_of_client_open(SpaprMachineState *spapr, uint32_t phandle)
Ooops, this should have been an address of a path, not a phandle.
> +{
> +g_assert(spapr->of_instance_last != 0x);
> +++spapr->of_instance_last;
>
Capstone assumes any s390x unknown instruction is 2 bytes.
Instead, use the ilen field in the first two bits of
the instruction to stay in sync with the insn stream.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Signed-off-by: Richard Henderson
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1851664
Title:
qemu-system
Update to aaffb38c44fa. Choose this over the "current" 4.0.1 tag
because next now includes the s390x z13 vector opcodes, and also
the insn tables are now read-only.
Fixes: https://bugs.launchpad.net/qemu/+bug/1826175
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
Makefi
Enable s390x, aka SYSZ, in the git submodule build.
Set the capstone parameters for both s390x host and guest.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
Makefile | 1 +
disas.c| 3 +++
target/s390x/cpu.c | 4
The following changes since commit 035eed4c0d257c905a556fa0f4865a0c077b4e7f:
Merge remote-tracking branch 'remotes/vivier/tags/q800-for-5.0-pull-request'
into staging (2020-01-07 17:08:21 +)
are available in the Git repository at:
https://github.com/rth7680/qemu.git tags/pull-cap-202001
On 07/01/2020 16:54, David Gibson wrote:
> On Tue, Jan 07, 2020 at 03:44:35PM +1100, Alexey Kardashevskiy wrote:
>>
>>
>> On 06/01/2020 15:19, David Gibson wrote:
+
+static uint32_t client_package_to_path(const void *fdt, uint32_t phandle,
+ u
Reduce the amount of preprocessor obfuscation by expanding
the text of each of the functions generated. The result is
only slightly smaller than the original.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Aleksandar Markovic
Signed-off-by: Richard Henderson
---
incl
On 07/01/2020 16:26, David Gibson wrote:
>> +static uint32_t client_setprop(SpaprMachineState *sm,
>> + uint32_t nodeph, uint32_t pname,
>> + uint32_t valaddr, uint32_t vallen)
>> +{
>> +char propname[64];
>
The generated functions aside from *_real are unused.
The *_real functions have a couple of users in mem_helper.c;
use *_mmuidx_ra instead, with MMU_REAL_IDX.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: David Hildenbrand
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
v2: Use
From: Philippe Mathieu-Daudé
All tcg includes are relative to the repository root directory,
we can safely remove the tcg/ directory from the include search
path list.
Reviewed-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Reviewed-by: Stefan Weil
Reviewed-by: Richard Henderson
Signed-off-
The functions generated by these macros are unused.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/alpha/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index a530249a5b..3f782c0efe 10064
From: Philippe Mathieu-Daudé
Reviewed-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Reviewed-by: Stefan Weil
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20200101112303.20724-4-phi...@redhat.com>
Signed-off-by: Richard Henderson
---
{tcg => include/tc
With the tracing hooks, the inline functions are no longer
so simple. Reduce the amount of preprocessor obfuscation
by expanding the text of each of the functions generated.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h
Do not use exec/cpu_ldst_{,useronly_}template.h directly,
but instead use the functional interface.
Cc: Eduardo Habkost
Tested-by: Philippe Mathieu-Daudé
Acked-by: Paolo Bonzini
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/i386/seg_helper.c | 56 --
From: Philippe Mathieu-Daudé
We currently search both the root and the tcg/ directories for tcg
files:
$ git grep '#include "tcg/' | wc -l
28
$ git grep '#include "tcg[^/]' | wc -l
94
To simplify the preprocessor search path, unify by expliciting the
tcg/ directory.
Patch created mech
With the tracing hooks, the inline functions are no longer
so simple. Once out-of-line, the current tlb_entry lookup
is redundant with the one in the main load/store_helper.
This also begins the introduction of a new target facing
interface, with suffix *_mmuidx_ra. This is not yet
official beca
> -Original Message-
> From: Igor Mammedov [mailto:imamm...@redhat.com]
> Sent: Tuesday, January 07, 2020 11:50 PM
> To: Zengtao (B)
> Cc: Michael S. Tsirkin; qemu-devel@nongnu.org; qemu-triv...@nongnu.org;
> Shannon Zhao; Peter Maydell; qemu-...@nongnu.org
> Subject: Re: [PATCH] hw/arm/acp
All users have now been converted to cpu_*_mmuidx_ra.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 230
1 file changed, 230 deletions(-)
diff --git a/include/exec/cpu_ldst.h b
Claudio's Huawei address has been defunct for quite a while. In
https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg06872.html
he asked for his personal address to be removed as well.
I will take over officially.
Cc: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathi
The separate suffixed functions were used to construct
some do_##insn function switched on mmu_idx. The interface
is exactly identical to the *_mmuidx_ra functions. Replace
them directly and remove the constructions.
Cc: Aurelien Jarno
Cc: Aleksandar Rikalo
Tested-by: Philippe Mathieu-Daudé
R
From: Philippe Mathieu-Daudé
All the *.inc.c files included by tcg/$TARGET/tcg-target.inc.c
are in tcg/, their parent directory. To simplify the preprocessor
search path, include the relative parent path: '..'.
Patch created mechanically by running:
$ for x in tcg-pool.inc.c tcg-ldst.inc.c; d
Code movement in an upcoming patch will show that this file
was implicitly depending on tcg.h being included indirectly.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
linux-user/syscall.c | 1 +
1 file chang
The generated *_user functions are unused. The *_kernel functions
have a couple of users in op_helper.c; use *_mmuidx_ra instead,
with MMU_KERNEL_IDX.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
v2: Use *_mmuidx_r
Code movement in an upcoming patch will show that this file
was implicitly depending on tcg.h being included indirectly.
Cc: Peter Maydell
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 1 +
1 file changed, 1 insertion
The functions generated by these macros are unused.
Tested-by: Philippe Mathieu-Daudé
Acked-by: Max Filippov
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/xtensa/cpu.h | 4
1 file changed, 4 deletions(-)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index
There are only two uses. Within dcbz_common, the local variable
mmu_idx already contains the epid computation, and we can avoid
repeating it for the store. Within helper_icbiep, the usage is
trivially expanded using PPC_TLB_EPID_LOAD.
Tested-by: Philippe Mathieu-Daudé
Acked-by: David Gibson
Re
The functions generated by these macros are unused.
Cc: Edgar E. Iglesias
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/cris/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index aba0a664
We don't actually need the result of the read, only to probe that the
memory mapping exists. This is exactly what probe_access does.
This is also the only user of any cpu_ld*_code_ra function.
Removing this allows the interface to be removed shortly.
Tested-by: Philippe Mathieu-Daudé
Acked-by:
The functions generated by these macros are unused.
Cc: Guan Xuetao
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/unicore32/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index
The functions generated by these macros are unused.
Cc: Aurelien Jarno
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/sh4/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index ecaa7a18a9..45
The functions generated by these macros are unused.
Cc: Eduardo Habkost
Tested-by: Philippe Mathieu-Daudé
Acked-by: Paolo Bonzini
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/i386/cpu.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target/i386/cpu.h b/target/i
There are no uses of the *_cmmu names other than the bare wrapping
within the *_code inlines. Therefore rename the functions so we
can drop the inlines.
Use abi_ptr instead of target_ulong in preparation for user-only;
the two types are identical for softmmu.
Tested-by: Philippe Mathieu-Daudé
R
There is nothing about these options that is related to PIE.
Use them unconditionally.
Reviewed-by: Alex Bennée
Reviewed-by: Fangrui Song
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
v2: Do not split into two tests.
---
configure | 9 ++---
1 file changed, 6 in
The functions generated by these macros are unused.
Cc: Edgar E. Iglesias
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/microblaze/cpu.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/c
The functions generated by these macros are unused.
Cc: Chris Wulff
Cc: Marek Vasut
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
The CFLAGS_NOPIE and LDFLAGS_NOPIE variables are used
in pc-bios/optionrom/Makefile, which has nothing to do
with the PIE setting of the main qemu executables.
This overrides any operating system default to build
all executables as PIE, which is important for ROMs.
Reviewed-by: Philippe Mathieu-D
Code movement in an upcoming patch will show that this file
was implicitly depending on trace/mem.h being included beforehand.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reported-by: Alex Bennée
Signed-off-by: Richard Henderson
---
plugins/api.c | 1 +
1 file change
This finishes the new interface began with the previous patch.
Document the interface and deprecate MMU_MODE_SUFFIX.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 80 +
The DO_LOAD macros replicate the distinction already performed
by the cpu_ldst.h functions. Use them.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 11 -
include/exec/translator.h | 48 +++---
Code movement in an upcoming patch will show that this file
was implicitly depending on trace-root.h being included beforehand.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/user/syscall-trace.h | 2
Code movement in an upcoming patch will show that this file
was implicitly depending on tcg.h being included indirectly.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: David Hildenbrand
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/s390x/mem_helper.c | 1 +
1 file chang
PIE is supported on many other hosts besides x86.
The default for non-x86 is now the same as x86: pie is used
if supported, and may be forced via --enable/--disable-pie.
The original commit (40d6444e91c) said:
"Non-x86 are not changed, as they require TCG changes"
but I think that's wrong --
Code movement in an upcoming patch will show that this file
was implicitly depending on tcg.h being included indirectly.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/a
In the cpu_ldst templates, we already require a MemOp, and it
is cleaner and clearer to pass that instead of 3 separate
arguments describing the memory operation.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
It is easy for the atomic helpers to use trace_mem_build_info
directly, without resorting to symbol pasting. For this usage,
we cannot use trace_mem_get_info, because the MemOp does not
support 16-byte accesses.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard H
This adjustment was random and unnecessary. The user mode
startup code in probe_guest_base() will choose a value for
guest_base that allows the host qemu binary to not conflict
with the guest binary.
With modern distributions, this isn't even used, as the default
is PIE, which does the same job i
Some distributions, e.g. Ubuntu 19.10, enable PIE by default.
If for some reason one wishes to build a non-pie binary, we
must provide additional options to override.
At the same time, reorg the code to an elif chain.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Tho
The commentary talks about "in concert with the addresses
assigned in the relevant linker script", except there is no
linker script for softmmu, nor has there been for some time.
(Do not confuse the user-only linker script editing that was
removed in the previous patch, because user-only does not
Recent toolchains support static and pie at the same time.
As with normal dynamic builds, allow --static to default to PIE
if supported by the toolchain. Allow --enable/--disable-pie to
override the default.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
v2: Fix --disable-pie --
The following changes since commit 035eed4c0d257c905a556fa0f4865a0c077b4e7f:
Merge remote-tracking branch 'remotes/vivier/tags/q800-for-5.0-pull-request'
into staging (2020-01-07 17:08:21 +)
are available in the Git repository at:
https://github.com/rth7680/qemu.git tags/pull-tcg-202001
On 1/8/20 12:51 PM, pannengy...@huawei.com wrote:
> From: Pan Nengyuan
>
> Fixes:
> /mnt/sdb/qemu/nbd/server.c: In function 'nbd_handle_request':
> /mnt/sdb/qemu/nbd/server.c:2313:9: error: 'ret' may be used uninitialized in
> this function [-Werror=maybe-uninitialized]
> int ret;
>
> Repo
On 1/8/20 12:39 PM, pannengy...@huawei.com wrote:
> From: Pan Nengyuan
>
> Fixes:
> target/arm/translate-a64.c: In function 'disas_crypto_three_reg_sha512':
> target/arm/translate-a64.c:13625:9: error: 'genfn' may be used uninitialized
> in this function [-Werror=maybe-uninitialized]
> genfn
From: Pan Nengyuan
Fixes:
/mnt/sdb/qemu/nbd/server.c: In function 'nbd_handle_request':
/mnt/sdb/qemu/nbd/server.c:2313:9: error: 'ret' may be used uninitialized in
this function [-Werror=maybe-uninitialized]
int ret;
Reported-by: Euler Robot
Signed-off-by: Pan Nengyuan
---
Changes v2 to
From: Pan Nengyuan
Fixes:
target/arm/translate-a64.c: In function 'disas_crypto_three_reg_sha512':
target/arm/translate-a64.c:13625:9: error: 'genfn' may be used uninitialized in
this function [-Werror=maybe-uninitialized]
genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr);
^~
On 07/01/2020 20:39, Andrea Bolognani wrote:
> On Tue, 2020-01-07 at 12:55 +1100, Alexey Kardashevskiy wrote:
>> On 07/01/2020 01:15, Daniel Henrique Barboza wrote:
>>> Question: does Petitboot already replaces SLOF in every possible
>>> scenario for all
>>> the spapr machine features?
>>
>> Pet
The Petitboot bootloader is way more advanced than SLOF is ever going to
be as Petitboot comes with the full-featured Linux kernel with all
the drivers, and initramdisk with quite user friendly interface.
The problem with ditching SLOF is that an unmodified pseries kernel can
either start via:
1. k
On Tue, Jan 07, 2020 at 06:36:38PM +0100, Greg Kurz wrote:
> On Tue, 7 Jan 2020 18:32:15 +0100
> Greg Kurz wrote:
>
> > On Tue, 7 Jan 2020 15:48:19 +1100
> > David Gibson wrote:
> >
> > > The PowerPC 970 CPU was a cut-down POWER4, which had hypervisor
> > > capability.
> > > However, it can b
On Mon, 09 Dec 2019 10:11:22 PST (-0800), Alistair Francis wrote:
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h| 10 +++
target/riscv/cpu_bits.h | 7 +
target/riscv/cpu_helper.c | 63 +++
3 files changed, 80 insertions(+)
diff --g
On Mon, 09 Dec 2019 10:11:24 PST (-0800), Alistair Francis wrote:
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a4b598d49a..fc38c45a7e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv
On 1/8/20 11:32 AM, LIU Zhiwei wrote:
>>> +switch (width) {
>>> +case 8:
>>> +if (vector_elem_mask(env, vm, width, lmul, i)) {
>>> +while (k >= 0) {
>>> +read = i * (nf + 1) + k;
>>> +env->v
On 1/8/2020 6:24 AM, Eric Blake wrote:
> On 1/5/20 7:54 PM, pannengy...@huawei.com wrote:
>> From: Pan Nengyuan
>>
>> Fixes:
>> /mnt/sdb/qemu/nbd/server.c: In function 'nbd_handle_request':
>> /mnt/sdb/qemu/nbd/server.c:2313:9: error: 'ret' may be used uninitialized in
>> this function [-Werro
On Tue, Jan 07, 2020 at 11:57:08AM +0530, Ganesh wrote:
>
> On 1/3/20 7:49 AM, David Gibson wrote:
> > On Thu, Jan 02, 2020 at 01:21:09PM +0530, Ganesh Goudar wrote:
> > > From: Aravinda Prasad
> > >
> > > This patch adds support in QEMU to handle "ibm,nmi-register"
> > > and "ibm,nmi-interlock"
On Tue, Jan 07, 2020 at 06:36:38PM +0100, Greg Kurz wrote:
> On Tue, 7 Jan 2020 18:32:15 +0100
> Greg Kurz wrote:
>
> > On Tue, 7 Jan 2020 15:48:19 +1100
> > David Gibson wrote:
> >
> > > The PowerPC 970 CPU was a cut-down POWER4, which had hypervisor
> > > capability.
> > > However, it can b
1 - 100 of 564 matches
Mail list logo
