Re: [PATCH v5 1/8] multifd: Add multifd-method parameter

Juan Quintela writes: > This will store the compression method to use. We start with none. > > Signed-off-by: Juan Quintela > Reviewed-by: Markus Armbruster I don't remember giving my R-by. I gave my Acked-by for [PATCH v2 06/10] migration: Add multifd-compress parameter Message-ID: <87d0cku

Re: [PATCH v3 2/4] qapi: Create module 'control'

Kevin Wolf writes: > Am 29.01.2020 um 17:35 hat Markus Armbruster geschrieben: >> Kevin Wolf writes: >> >> > misc.json contains definitions that are related to the system emulator, >> > so it can't be used for other tools like the storage daemon. This patch >> > moves basic functionality that i

Re: [PATCH 0/4] target/ppc: Use probe_access

On Thu, Jan 30, 2020 at 12:50 AM Richard Henderson < richard.hender...@linaro.org> wrote: > The first two address the performance regression noticed > by Howard Spoelstra. The last two are just something I > noticed at the same time. > > > r~ > > > Richard Henderson (4): > target/ppc: Use probe

Re: [PATCH qemu v5] spapr: Kill SLOF

On 28/01/2020 22:31, Andrea Bolognani wrote: > On Thu, 2020-01-23 at 16:11 +1100, David Gibson wrote: >> On Wed, Jan 22, 2020 at 06:14:37PM +1100, Alexey Kardashevskiy wrote: >>> On 22/01/2020 17:32, David Gibson wrote: I'm not thinking of "grub" as a separate option - that would be the >>>

Re: [PATCH 001/142] minikconf: accept alnum identifiers

On 29/01/20 15:04, Marc-André Lureau wrote: >> Sure, but with a proper patch description, this patch here could even be >> merged today already, shrinking this huge patch series by one at least... > > Paolo has been merging many preliminary patches already. I am not sure > why that one wasn't. I'

Re: [PATCH] target/ppc/cpu.h: Put macro parameter in parentheses

On Thu, Jan 30, 2020 at 03:06:18AM +0100, BALATON Zoltan wrote: > Fix PPC_INPUT macro to work with more complex expressions by > protecting its argument with parentheses. > > Signed-off-by: BALATON Zoltan Pretty unlikely to break anything in practice, but applied nonetheless. > --- > target/pp

[PATCH] target/ppc/cpu.h: Put macro parameter in parentheses

Fix PPC_INPUT macro to work with more complex expressions by protecting its argument with parentheses. Signed-off-by: BALATON Zoltan --- target/ppc/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 8ebeaba649..e3a937e163 100644 --

Re: [PATCH 0/4] target/ppc: Use probe_access

00:51 Čet, 30.01.2020. Richard Henderson је написао/ла: > > The first two address the performance regression noticed > by Howard Spoelstra. The last two are just something I > noticed at the same time. > But, performance regression, according to Howard bisect analysis, happened because of the ch

[PATCH] spapr: Enable DD2.3 accelerated count cache flush in pseries-5.0 machine

For POWER9 DD2.2 cpus, the best current Spectre v2 indirect branch mitigation is "count cache disabled", which is configured with: -machine cap-ibs=fixed-ccd However, this option isn't available on DD2.3 CPUs with KVM, because they don't have the count cache disabled. For POWER9 DD2.3 cpus, it

Re: [PATCH v2 2/4] virtio-scsi: default num_queues to -smp N

On 29/01/20 16:44, Stefan Hajnoczi wrote: > On Mon, Jan 27, 2020 at 02:10:31PM +0100, Cornelia Huck wrote: >> On Fri, 24 Jan 2020 10:01:57 + >> Stefan Hajnoczi wrote: >>> @@ -47,10 +48,15 @@ static void vhost_scsi_pci_realize(VirtIOPCIProxy >>> *vpci_dev, Error **errp) >>> { >>> VHostSC

Re: [PATCH] seqlock: fix seqlock_write_unlock_impl function

On 29/01/20 15:49, Luc Michel wrote: > The seqlock write unlock function was incorrectly calling > seqlock_write_begin() instead of seqlock_write_end(), and was releasing > the lock before incrementing the sequence. This could lead to a race > condition and a corrupted sequence number becoming odd

[PATCH v5 34/41] target/arm: check TGE and E2H flags for EL0 pauth traps

From: Alex Bennée According to ARM ARM we should only trap from the EL1&0 regime. Reviewed-by: Peter Maydell Signed-off-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/pauth_helper.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/pauth_help

Re: [PATCH] xen-bus/block: explicitly assign event channels to an AioContext

Hi Anthony, On 19/12/2019 17:11, Anthony PERARD wrote: On Mon, Dec 16, 2019 at 02:34:51PM +, Paul Durrant wrote: It is not safe to close an event channel from the QEMU main thread when that channel's poller is running in IOThread context. This patch adds a new xen_device_set_event_channel_

[PATCH v5 24/41] target/arm: Update ctr_el0_access for EL2

Update to include checks against HCR_EL2.TID2. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 26 +- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 33f4cbbc64..e79237ea12

[PATCH v5 41/41] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt

The fall through organization of this function meant that we would raise an interrupt, then might overwrite that with another. Since interrupt prioritization is IMPLEMENTATION DEFINED, we can recognize these in any order we choose. Unify the code to raise the interrupt in a block at the end. Revi

[PATCH v5 40/41] target/arm: Use bool for unmasked in arm_excp_unmasked

The value computed is fully boolean; using int8_t is odd. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d9cf625073..06d72ac9d6 100644 -

[PATCH v5 39/41] target/arm: Pass more cpu state to arm_excp_unmasked

Avoid redundant computation of cpu state by passing it in from the caller, which has already computed it for itself. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/cpu.c | 22 -- 1 file changed, 12 insertions(+), 10 deletions(-) diff --g

[PATCH v5 25/41] target/arm: Add the hypervisor virtual counter

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu-qom.h | 1 + target/arm/cpu.h | 11 + target/arm/cpu.c | 3 ++- target/arm/helper.c | 57 4 files changed, 66 insertions(+), 6 deletions(-) diff --git a/t

[PATCH v5 19/41] target/arm: Reorganize ARMMMUIdx

Prepare for, but do not yet implement, the EL2&0 regime. This involves adding the new MMUIdx enumerators and adjusting some of the MMUIdx related predicates to match. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 134

[PATCH v5 33/41] target/arm: Update {fp,sve}_exception_el for VHE

When TGE+E2H are both set, CPACR_EL1 is ignored. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 53 - 1 file changed, 28 insertions(+), 25 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c inde

[PATCH v5 38/41] target/arm: Move arm_excp_unmasked to cpu.c

This inline function has one user in cpu.c, and need not be exposed otherwise. Code movement only, with fixups for checkpatch. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/cpu.h | 111 --- target/arm/cpu.c | 119 +++

[PATCH v5 28/41] target/arm: Add VHE system register redirection and aliasing

Several of the EL1/0 registers are redirected to the EL2 version when in EL2 and HCR_EL2.E2H is set. Many of these registers have side effects. Link together the two ARMCPRegInfo structures after they have been properly instantiated. Install common dispatch routines to all of the relevant registe

[PATCH v5 32/41] target/arm: Update arm_phys_excp_target_el for TGE

The TGE bit routes all asynchronous exceptions to EL2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9b12ff0ef0..0c1414acae 100644 --- a/target/arm/hel

[PATCH v5 18/41] target/arm: Tidy ARMMMUIdx m-profile definitions

Replace the magic numbers with the relevant ARM_MMU_IDX_M_* constants. Keep the definitions short by referencing previous symbols. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/cpu.h | 16 1 file changed, 8 insertions(+), 8 deletions(-) di

[PATCH v5 36/41] target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE

When VHE is enabled, the exception level below EL2 is not EL1, but EL0, and so to identify the entry vector offset for exceptions targeting EL2 we need to look at the width of EL0, not of EL1. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 9 +++-- 1 f

[PATCH v5 26/41] target/arm: Update timer access for VHE

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 102 +++- 1 file changed, 81 insertions(+), 21 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f633554678..37e8bf4949 100644 --- a/target/arm/hel

[PATCH v5 12/41] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01]

This is part of a reorganization to the set of mmu_idx. This emphasizes that they apply to the Secure EL1&0 regime. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 8 target/arm/internals.h | 4 ++-- target/arm/translate.h | 2 +- t

[PATCH v5 31/41] target/arm: Flush tlbs for E2&0 translation regime

Signed-off-by: Richard Henderson --- v5: Flush all EL2 regimes with TLBI ALLE2 (pmm). --- target/arm/helper.c | 34 +++--- 1 file changed, 27 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 708a2ecf91..9b12ff0ef0 100644 --- a

[PATCH v5 21/41] target/arm: Update arm_mmu_idx for VHE

Return the indexes for the EL2&0 regime when the appropriate bits are set within HCR_EL2. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v4: Consistently check E2H & TGE & ELUsingAArch32(EL2). Do not apply TGE at EL2. --- target/arm/helper.c | 11 +-- 1 file changed,

[PATCH v5 07/41] target/arm: Split out alle1_tlbmask

No functional change, but unify code sequences. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v5: Do not confuse things by prefixing "vm". --- target/arm/helper.c | 86 + 1 file changed, 24 insertio

[PATCH v5 20/41] target/arm: Add regime_has_2_ranges

Create a predicate to indicate whether the regime has both positive and negative addresses. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/internals.h | 18 ++ target/arm/helper.c| 23 ++- target/arm/translate-a64.c | 3

[PATCH v5 35/41] target/arm: Update get_a64_user_mem_index for VHE

The EL2&0 translation regime is affected by Load Register (unpriv). The code structure used here will facilitate later changes in this area for implementing UAO and NV. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 9 target/arm/translat

[PATCH v5 29/41] target/arm: Add VHE timer register redirection and aliasing

Apart from the wholesale redirection that HCR_EL2.E2H performs for EL2, there's a separate redirection specific to the timers that happens for EL0 when running in the EL2&0 regime. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 191

[PATCH v5 06/41] target/arm: Split out vae1_tlbmask

No functional change, but unify code sequences. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 32 +--- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/target/arm/helper.c b/tar

[PATCH v5 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime

Since we only support a single ASID, flush the tlb when it changes. Note that TCR_EL2, like TCR_EL1, has the A1 bit that chooses between the two TTBR* registers for the location of the ASID. Signed-off-by: Richard Henderson --- target/arm/helper.c | 22 +++--- 1 file changed, 15

[PATCH v5 15/41] target/arm: Recover 4 bits from TBFLAGs

We had completely run out of TBFLAG bits. Split A- and M-profile bits into two overlapping buckets. This results in 4 free bits. We used to initialize all of the a32 and m32 fields in DisasContext by assignment, in arm_tr_init_disas_context. Now we only initialize either the a32 or m32 by assignm

[PATCH v5 37/41] target/arm: Enable ARMv8.1-VHE in -cpu max

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 61fd0ade29..d771e867fa 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -671,6 +671,7 @@ static void aar

[PATCH v5 23/41] target/arm: Update aa64_zva_access for EL2

The comment that we don't support EL2 is somewhat out of date. Update to include checks against HCR_EL2.TDZ. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 26 +- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/target/a

[PATCH v5 10/41] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2

The EL1&0 regime is the only one that uses 2-stage translation. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 +-- target/arm/internals.h | 2 +- target/arm/helper.c| 57 -- target/arm/translate-a64

[PATCH v5 05/41] target/arm: Update CNTVCT_EL0 for VHE

The virtual offset may be 0 depending on EL, E2H and TGE. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 40 +--- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c ind

[PATCH v5 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE

For ARMv8.1, op1 == 5 is reserved for EL2 aliases of EL1 and EL0 registers. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 37e8bf4949..64c

[PATCH v5 03/41] target/arm: Add CONTEXTIDR_EL2

Not all of the breakpoint types are supported, but those that only examine contextidr are extended to support the new register. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/debug_helper.c | 50 +-- target/arm/helper.c | 11 ++

[PATCH v5 22/41] target/arm: Update arm_sctlr for VHE

Use the correct sctlr for EL2&0 regime. Due to header ordering, and where arm_mmu_idx_el is declared, we need to move the function out of line. Use the function in many more places in order to select the correct control. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v3: Use arm

[PATCH v5 02/41] target/arm: Enable HCR_E2H for VHE

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h| 7 --- target/arm/helper.c | 6 +- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0477cef1ea..239c9eb783 100644 --- a/target/arm/cpu.h +++ b/targe

[PATCH v5 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits

We are about to expand the number of mmuidx to 10, and so need 4 bits. For the benefit of reading the number out of -d exec, align it to the penultimate nibble. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 16 1 file changed, 8 insertions(+),

[PATCH v5 09/41] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_*

This is part of a reorganization to the set of mmu_idx. This emphasizes that they apply to the EL1&0 regime. The ultimate goal is -- Non-secure regimes: ARMMMUIdx_E10_0, ARMMMUIdx_E20_0, ARMMMUIdx_E10_1, ARMMMUIdx_E2, ARMMMUIdx_E20_2, -- Secure regimes: ARMMMUIdx_SE10_0

[PATCH v5 08/41] target/arm: Simplify tlb_force_broadcast alternatives

Rather than call to a separate function and re-compute any parameters for the flush, simply use the correct flush function directly. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 52 + 1 file changed, 24 insertion

[PATCH v5 13/41] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3

This is part of a reorganization to the set of mmu_idx. The EL3 regime only has a single stage translation, and is always secure. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 2 +- target/arm/helper.c| 14 +++--

[PATCH v5 00/41] target/arm: Implement ARMv8.1-VHE

Version 5 applies the feedback given vs version 4, back in December. There was quite a bit (thanks) and I believe I've gotten it all. FWIW, the patches without review are: 0028-target-arm-Add-VHE-system-register-redirection-an.patch 0030-target-arm-Flush-tlb-for-ASID-changes-in-EL2-0-tr.patc

[PATCH v5 17/41] target/arm: Rearrange ARMMMUIdxBit

Define via macro expansion, so that renumbering of the base ARMMMUIdx symbols is automatically reflected in the bit definitions. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/cpu.h | 39 +++ 1 fi

[PATCH v5 01/41] target/arm: Define isar_feature_aa64_vh

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c1aedbeac0..0477cef1ea 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3678,6 +3678,11 @@ static inline bool

[PATCH v5 04/41] target/arm: Add TTBR1_EL2

At the same time, add writefn to TTBR0_EL2 and TCR_EL2. A later patch will update any ASID therein. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v5: Do not update TCR_EL2 yet; delay that til we handle ASIDs. --- target/arm/helper.c | 13 - 1 file changed, 12 inserti

[PATCH v5 11/41] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E*

This is part of a reorganization to the set of mmu_idx. The EL1&0 regime is the only one that uses 2-stage translation. Spelling out Stage avoids confusion with Secure. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v5: Adjust || indentation (ajb) --- target/arm/cpu.h | 4

[PATCH v5 14/41] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2

This is part of a reorganization to the set of mmu_idx. The non-secure EL2 regime only has a single stage translation; there is no point in pointing out that the idx is for stage1. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- target/arm/interna

[PATCH 3/4] target/ppc: Remove redundant mask in DCBZ

The value of addr has already been masked, just above. Signed-off-by: Richard Henderson --- target/ppc/mem_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index e7d3a79d96..0cb78777e7 100644 --- a/target/ppc/mem_helpe

[PATCH 4/4] target/ppc: Use probe_write for DCBZ

Using probe_write instead of tlb_vaddr_to_host means that we process watchpoints and notdirty pages more efficiently. Signed-off-by: Richard Henderson --- target/ppc/mem_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c

[PATCH 1/4] target/ppc: Use probe_access for LSW, STSW

Use a minimum number of mmu lookups for the contiguous bytes that are accessed. If the lookup succeeds, we can finish the operation with host addresses only. Reported-by: Howard Spoelstra Signed-off-by: Richard Henderson --- target/ppc/mem_helper.c | 148 ++-

[PATCH 0/4] target/ppc: Use probe_access

The first two address the performance regression noticed by Howard Spoelstra. The last two are just something I noticed at the same time. r~ Richard Henderson (4): target/ppc: Use probe_access for LSW, STSW target/ppc: Use probe_access for LMW, STMW target/ppc: Remove redundant mask in D

[PATCH 2/4] target/ppc: Use probe_access for LMW, STMW

Use a minimum number of mmu lookups for the contiguous bytes that are accessed. If the lookup succeeds, we can finish the operation with host addresses only. Reported-by: Howard Spoelstra Signed-off-by: Richard Henderson --- target/ppc/mem_helper.c | 45 +---

Re: [PATCH] qemu-deprecated: Remove text about Python 2

On 1/30/20 12:18 AM, Aleksandar Markovic wrote: 23:14 Sre, 29.01.2020. Philippe Mathieu-Daudé > је написао/ла: > > Hi Aleksandar, > > On 1/9/20 1:49 PM, Aleksandar Markovic wrote: > > > > > > On Thursday, January 9, 2020, Thomas Huth >

[PATCH 09/10] scripts: Explicit usage of Python 3

Use the program search path to find the Python 3 interpreter. Patch created mechanically by running: $ sed -i "s,^#\!/usr/bin/\(env\ \)\?python$,#\!/usr/bin/env python3," \ $(git grep -lF '#!/usr/bin/env python' | xargs grep -L 'if __name__.*__main__') Reported-by: Vladimir Sementsov-Og

Re: [PATCH] qemu-deprecated: Remove text about Python 2

23:14 Sre, 29.01.2020. Philippe Mathieu-Daudé је написао/ла: > > Hi Aleksandar, > > On 1/9/20 1:49 PM, Aleksandar Markovic wrote: > > > > > > On Thursday, January 9, 2020, Thomas Huth > > wrote: > > > > Python 2 support has been removed, so we should now also remove >

[PATCH 08/10] tests/qemu-iotests: Explicit usage of Python 3

Use the program search path to find the Python 3 interpreter. Patch created mechanically by running: $ sed -i "s,^#\!/usr/bin/\(env\ \)\?python$,#\!/usr/bin/env python3," \ $(git grep -lF '#!/usr/bin/env python' | xargs grep -L 'if __name__.*__main__') Reported-by: Vladimir Sementsov-Og

[PATCH 04/10] scripts/minikconf: Explicit usage of Python 3

Use the program search path to find the Python 3 interpreter. Patch created manually after running: $ git grep -l 'if __name__.*__main__' | xargs grep -LF '#!/usr/bin/env python3' Reported-by: Vladimir Sementsov-Ogievskiy Suggested-by: Daniel P. Berrangé Suggested-by: Stefan Hajnoczi Signe

[PATCH 06/10] scripts/tracetool: Remove shebang header

Patch created mechanically by running: $ chmod 644 $(git grep -lF '#!/usr/bin/env python' | xargs grep -L 'if __name__.*__main__') $ sed -i "/^#\!\/usr\/bin\/\(env\ \)\?python.\?$/d" $(git grep -lF '#!/usr/bin/env python' | xargs grep -L 'if __name__.*__main__') Reported-by: Vladimir Sement

[PATCH 10/10] tests/qemu-iotests/check: Update to match Python 3 interpreter

All the iotests Python scripts have been converted to search for the Python 3 interpreter. Update the ./check script accordingly. Signed-off-by: Philippe Mathieu-Daudé --- tests/qemu-iotests/check | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/qemu-iotests/check b/test

[PATCH 02/10] tests/qemu-iotests: Explicit usage of Python 3

Use the program search path to find the Python 3 interpreter. Patch created mechanically by running: $ sed -i "s,^#\!/usr/bin/\(env\ \)\?python$,#\!/usr/bin/env python3," \ $(git grep -l 'if __name__.*__main__') Reported-by: Vladimir Sementsov-Ogievskiy Suggested-by: Daniel P. Berrangé

[PATCH 03/10] tests: Explicit usage of Python 3

Use the program search path to find the Python 3 interpreter. Patch created mechanically by running: $ sed -i "s,^#\!/usr/bin/\(env\ \)\?python$,#\!/usr/bin/env python3," \ $(git grep -l 'if __name__.*__main__') Reported-by: Vladimir Sementsov-Ogievskiy Suggested-by: Daniel P. Berrangé

[PATCH 07/10] tests/vm: Remove shebang header

Patch created mechanically by running: $ chmod 644 $(git grep -lF '#!/usr/bin/env python' | xargs grep -L 'if __name__.*__main__') $ sed -i "/^#\!\/usr\/bin\/\(env\ \)\?python.\?$/d" $(git grep -lF '#!/usr/bin/env python' | xargs grep -L 'if __name__.*__main__') Reported-by: Vladimir Sement

[PATCH 05/10] tests/acceptance: Remove shebang header

Patch created mechanically by running: $ chmod 644 $(git grep -lF '#!/usr/bin/env python' | xargs grep -L 'if __name__.*__main__') $ sed -i "/^#\!\/usr\/bin\/\(env\ \)\?python.\?$/d" $(git grep -lF '#!/usr/bin/env python' | xargs grep -L 'if __name__.*__main__') Reported-by: Vladimir Sement

[PATCH 01/10] scripts: Explicit usage of Python 3

Use the program search path to find the Python 3 interpreter. Patch created mechanically by running: $ sed -i "s,^#\!/usr/bin/\(env\ \)\?python$,#\!/usr/bin/env python3," \ $(git grep -l 'if __name__.*__main__') Reported-by: Vladimir Sementsov-Ogievskiy Suggested-by: Daniel P. Berrangé

[PATCH 00/10] python: Explicit usage of Python 3

Hello, These are mechanical sed patches used to convert the code base to Python 3, as suggested on this thread: https://www.mail-archive.com/qemu-devel@nongnu.org/msg675024.html Regards, Phil. Philippe Mathieu-Daudé (10): scripts: Explicit usage of Python 3 tests/qemu-iotests: Explicit usag

Re: [PATCH qemu] spapr_pci: Create assigned properties for bridges

On 29/01/2020 14:37, David Gibson wrote: > On Wed, Jan 29, 2020 at 01:31:11PM +1100, Alexey Kardashevskiy wrote: >> QEMU assigns bus numbers so tell the guest about assigned values. >> >> This also adds an empty "ranges" to let the existing linux kernels proceed >> far enough to trigger resource

Re: [PATCH 0/2] ppc/pnv: Add models for PHB4 and PHB3 PCIe Host bridges

On Wed, Jan 29, 2020 at 02:15:35PM +0100, Cédric Le Goater wrote: > On 1/29/20 7:31 AM, David Gibson wrote: > > On Mon, Jan 27, 2020 at 03:45:04PM +0100, Cédric Le Goater wrote: > >> Hello, > >> > >> These are models for the PCIe Host Bridges, PHB3 and PHB4, as found on > >> POWER8 and POWER9 proce

Re: [PATCH] ppc/pnv: change the PowerNV machine devices to be non user creatable

On Wed, Jan 29, 2020 at 12:37:20PM +0100, Cédric Le Goater wrote: > The PowerNV machine emulates an OpenPOWER system and the PowerNV chip > devices are models of the internal logic of the POWER processor. They > can not be instantiated by the user on the QEMU command line. > > The PHB3/PHB4 device

Re: [PATCH] qemu-deprecated: Remove text about Python 2

Hi Aleksandar, On 1/9/20 1:49 PM, Aleksandar Markovic wrote: On Thursday, January 9, 2020, Thomas Huth > wrote: Python 2 support has been removed, so we should now also remove the announcement text for the deprecation. Signed-off-by: Thomas Huth mailto:t

Re: [RFC PATCH] hw/arm/virt: Support NMI injection

On 1/29/20 6:57 PM, Julien Thierry wrote: On 1/29/20 3:46 AM, Gavin Shan wrote: On 1/28/20 7:29 PM, Julien Thierry wrote: .../... Julien, thanks for the explanation. The question we're not sure if NMI should be injected on receiving HMP/QMP "nmi" command. It means it's not clear what behavi

[Bug 1861341] [NEW] ARM QEMU: Unknown syscall 397

Public bug reported: QEMU is reporting ``` Unknown syscall 397 ``` (statx if I read tables right) when used via flatpak for ARM images on x86_64. This has been reproduced on Fedora and Gentoo. To reproduce: - get flatpak KDE 5.12 for arm: flatpak install --user org.kde.Sdk/arm/5.12 org.kde.Pl

Re: [PATCH] MAINTAINERS: Cover hppa-softmmu.mak in the HP-PARISC Machines section

On 29.01.20 20:03, Philippe Mathieu-Daudé wrote: > Modifications to default-configs/hppa-softmmu.mak should be > reviewed by the hppa-softmmu users (currently a single machine). > > Signed-off-by: Philippe Mathieu-Daudé Acked-by: Helge Deller > --- > MAINTAINERS | 1 + > 1 file changed, 1 inse

Re: [PATCH] hw/hppa/Kconfig: LASI chipset requires PARALLEL port

On 29.01.20 20:23, Philippe Mathieu-Daudé wrote: > The PARISC Lasi chipset emulation requires some of the common parallel > support and fails to build on a --without-default-devices: > > LINKhppa-softmmu/qemu-system-hppa > /usr/bin/ld: hw/hppa/lasi.o: in function `lasi_init': > hw/hppa/

Re: [PATCH v2 02/29] accel/accel: Make TYPE_ACCEL abstract

Since this file isn't covered in MAINTAINERS, manually Cc'ing Paolo. On 1/29/20 10:23 PM, Philippe Mathieu-Daudé wrote: There is no generic acceleration, we have to use specific implementations. Make the base class abstract. Fixes: b14a0b7469f Signed-off-by: Philippe Mathieu-Daudé --- accel/

[PATCH v2 29/29] MAINTAINERS: Add Acceptance tests reviewers

Acceptance tests can test any piece of the QEMU codebase. As such, the directory holding them does not belong to a specific subsystem with designated maintainers. Each subsystem covered by a test is welcomed to add the test path to its section. See for example commits 71b290e70, b11785ca2 or 5d480

[PATCH v2 27/29] tests/acceptance/migration: Default to -nodefaults

We don't need the default options to run this test. This fixes errors when running a binary built with --without-default-devices such: ERROR: qemu-system-arm: Unsupported NIC model: virtio-net-pci Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/migration.py | 4 +++- 1 file change

[PATCH v2 26/29] tests/acceptance/boot_linux_console: Do not use VGA on Clipper machine

As we only read the serial console, we don't need to force a VGA display. This fixes when running a binary built with --without-default-devices: ERROR: qemu-system-alpha: standard VGA not available We also need the '-nodefaults' argument to avoid: ERROR: qemu-system-alpha: Unsupported NIC mo

[PATCH] ui/gtk: Respect -show-cursor option

If the user specifies the -show-cursor option, force the cursor to be shown even if it would not otherwise. Signed-off-by: Joshua Watt --- ui/gtk.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/ui/gtk.c b/ui/gtk.c index d18892d1de..bdd1b53236 100644 --- a/ui/gtk.c +++ b/u

[PATCH v2 28/29] tests/acceptance/version: Default to -nodefaults

We don't need the default options to run this test. This fixes errors when running a binary built with --without-default-devices such: ERROR: qemu-system-arm: Unsupported NIC model: virtio-net-pci Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/version.py | 1 + 1 file changed, 1

[PATCH v2 25/29] tests/acceptance/virtio_check_params: Require a virtio-scsi-pci device

When running this test with QEMU configured using --without-default-devices, we get: ERROR: qemu-system-s390x: -device virtio-scsi-pci,id=scsi0: 'virtio-scsi-pci' is not a valid device model name To be able to run the acceptance tests with a binary built using --without-default-devices, add a

[PATCH v2 17/29] tests/acceptance/virtio_check_params: Improve exception logging

Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/virtio_check_params.py | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/tests/acceptance/virtio_check_params.py b/tests/acceptance/virtio_check_params.py index 4a417b8ef5..51a2dd76e8 100755 --- a/tests/acceptan

Re: [PATCH v2 00/29] tests/acceptance/virtio_seg_max_adjust: Restrict it to Linux/X86

Wrong subject... should be: "Improve multi-arch/OS support of acceptance tests" On 1/29/20 10:23 PM, Philippe Mathieu-Daudé wrote: Currently our CI is mostly restricted to Linux/X86. We want to have more, but until there we have to run these tests manually, which is why we didn't noticed earl

[PATCH v2 24/29] tests/acceptance/virtio_check_params: Default to -nodefaults

We don't need the default options to run this test. This fixes errors when running a binary built with --without-default-devices such: ERROR: qemu-system-s390x: Unknown device 'virtio-net-ccw' for bus 'virtual-css-bus' Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/virtio_check_

[PATCH v2 16/29] tests/acceptance/virtio_check_params: Only remove listed machines

Do not remove unavailable machines, this fixes: VirtioMaxSegSettingsCheck.test_machine_types: ERROR: list.remove(x): x not in list (0.12 s) Reviewed-by: Cornelia Huck Signed-off-by: Philippe Mathieu-Daudé --- TODO check how to use attribute (Wainer) --- tests/acceptance/virtio_check_params.

[PATCH v2 23/29] tests/acceptance/virtio_check_params: Support the ppc architecture

We can run these tests on the pSeries machines too, we were just missing to properly parse the machine names. Note: we have to exclude the versioned machines from QEMU 2.8 to 2.11 which fail, such: TestFail: machine type pseries-2.8: No Transactional Memory support in TCG, try appending -machi

[RFC PATCH v2 21/29] tests/acceptance/virtio_check_params: Kludge to skip tests on MIPS

The MIPS default machine expects a BIOS. To be able to run QMP queries on the machine, we have to use the '-bios' command line option. Signed-off-by: Philippe Mathieu-Daudé --- RFC: This is not the correct place, this should be generic, or the MIPS machine need some rework. --- tests/accept

[PATCH v2 20/29] tests/acceptance/virtio_check_params: Skip test if arch is not supported

Refactor the X86 specific code. If we run this test on an architecture which is not explicitly supported, the test will be cancelled (skipped). Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/virtio_check_params.py | 37 +++-- 1 file changed, 23 insertions(+), 14 d

[PATCH v2 22/29] tests/acceptance/virtio_check_params: Support the s390x architecture

We can run these tests on the s390x architecture too, we were just missing to properly parse the machine names. Suggested-by: Cornelia Huck Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/virtio_check_params.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/acceptance/vi

[PATCH v2 19/29] tests/acceptance/virtio_check_params: Only test Xen as superuser

When running the test unprivileged, we get: $ avocado --show=app,machine run tests/acceptance/virtio_check_params.py JOB ID : b631d5d692e49b791b211d33b80730315d561d45 JOB LOG: job-results/job-2020-01-22T17.56-b631d5d/job.log (1/1) tests/acceptance/virtio_check_params.py:VirtioMax

[RFC PATCH v2 14/29] tests/acceptance: Use 'device' tags to check availability in QEMU binary

We already use the 'device' tag in Avocado tests. If any of the requested device is not available in the QEMU binary, the tests will be cancelled (skipped). Signed-off-by: Philippe Mathieu-Daudé --- RFC because I'm not certain, we might want to find bugs where a device is missing in the built

[PATCH v2 18/29] tests/acceptance/virtio_check_params: List machine being tested

Add logging for easier debugging of failures: $ avocado --show=machine run tests/acceptance/virtio_check_params.py (1/1) tests/acceptance/virtio_check_params.py:VirtioMaxSegSettingsCheck.test_machine_types: machine: {'name': 'pc-i440fx-2.12', 'seg_max_adjust': 'false', 'device': 'virtio-s

[PATCH v2 13/29] python/qemu: Add binutils::binary_get_devices()

Since QEMU binaries can be built with various configurations, the list of devices linked in can vary. Add a helper to query the list of devices built into a QEMU binary. Signed-off-by: Philippe Mathieu-Daudé --- python/qemu/binutils.py | 9 + tests/acceptance/core_scripts.py | 8

[PATCH v2 15/29] tests: rename virtio_seg_max_adjust to virtio_check_params

From: Denis Plotnikov Since, virtio_seg_max_adjust checks not only seg_max, but also virtqueue_size parameter, let's make the test more general and add new parameters to be checked there in the future. Signed-off-by: Denis Plotnikov Message-Id: <20200129140702.5411-5-dplotni...@virtuozzo.com> S

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