On Tue, 3 Mar 2020 00:59:26 +0100
Philippe Mathieu-Daudé wrote:
> On 3/2/20 10:22 PM, Aleksandar Markovic wrote:
> > Forwarding this to Igor. Can you please give us your opinion, Igor, on this
> > proposal?
>
> I'm not sure it is Igor area.
true,
as far as board consumes all machine->ram and
On Tue, 3 Mar 2020 14:43:42 +1100
David Gibson wrote:
> Currently we use a big switch statement in ppc_hash64_update_rmls() to work
> out what the right RMA limit is based on the LPCR[RMLS] field. There's no
> formula for this - it's just an arbitrary mapping defined by the existing
> CPU imple
Le 02/03/2020 à 20:31, Lirong Yuan a écrit :
> This change adds the support for AT_EXECFN auxval.
>
> Signed-off-by: Lirong Yuan
> ---
> Changelog since v1:
> - remove implementation for AT_EXECFD auxval.
>
> linux-user/elfload.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> di
02.03.2020 18:39, Kevin Wolf wrote:
Am 02.03.2020 um 14:55 hat Denis Plotnikov geschrieben:
On 02.03.2020 16:38, Kevin Wolf wrote:
Am 10.11.2019 um 20:03 hat Denis Plotnikov geschrieben:
This allows to replace the file on a block device and is useful
to workaround the cases (migration) when
Kevin Wolf writes:
> Am 02.03.2020 um 15:22 hat Markus Armbruster geschrieben:
>> Marc-André Lureau writes:
>>
>> > Hi
>> >
>> > On Fri, Feb 21, 2020 at 5:50 PM Markus Armbruster
>> > wrote:
>> >>
>> >> Kevin Wolf writes:
>> >>
>> >> > Am 20.02.2020 um 17:01 hat Markus Armbruster geschrieben
The bochs-display mmio bar has some sub-regions with the actual hardware
registers. What happens when the guest access something outside those
regions depends on the archirecture. On x86 those reads succeed (and
return 0xff I think). On risc-v qemu aborts.
This patch adds handlers for the paren
Hi Peter,
> -Original Message-
> From: Peter Maydell
> Sent: Friday, February 28, 2020 3:56 PM
> To: Sai Pavan Boddu
> Cc: pbonz...@redhat.com; QEMU Developers ;
> Edgar Iglesias
> Subject: Re: Implementing IOMMU support for SDHCI
>
> On Fri, 28 Feb 2020 at 10:08, Sai Pavan Boddu wrot
Volker Rümelin writes:
> The review for patch ed2a4a7941 "audio: proper support for
> float samples in mixeng" suggested this would be a good idea.
>
> Signed-off-by: Volker Rümelin
> ---
> qapi/audio.json | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/qapi/audio.json
On Tue, Mar 03, 2020 at 01:22:26PM +0800, Yi Sun wrote:
> On 20-03-02 22:36:39, Yan Zhao wrote:
> > On Tue, Mar 03, 2020 at 11:11:14AM +0800, Yi Sun wrote:
> > > It is too strict to use assert to make qemu coredump if
> > > the notification does not overlap with registered range.
> > > Skip it is f
On 20-03-02 22:36:39, Yan Zhao wrote:
> On Tue, Mar 03, 2020 at 11:11:14AM +0800, Yi Sun wrote:
> > It is too strict to use assert to make qemu coredump if
> > the notification does not overlap with registered range.
> > Skip it is fine enough.
> >
> > During test, we found such a case for vhost n
From: Peter Feiner [mailto:pfei...@google.com]
Sent: Tuesday, March 3, 2020 12:29 AM
To: Zhoujian (jay)
Cc: Ben Gardon ; Peter Xu ;
k...@vger.kernel.org; qemu-devel@nongnu.org; pbonz...@redhat.com;
dgilb...@redhat.com; quint...@redhat.com; Liujinsong (Paul)
; linfeng (M) ; wangxin (U)
; Hua
Move the calculation of the Real Mode Area (RMA) size into a helper
function. While we're there clean it up and correct it in a few ways:
* Add comments making it clearer where the various constraints come from
* Remove a pointless check that the RMA fits within Node 0 (we've just
clamped
On Tue, Mar 03, 2020 at 11:11:14AM +0800, Yi Sun wrote:
> It is too strict to use assert to make qemu coredump if
> the notification does not overlap with registered range.
> Skip it is fine enough.
>
> During test, we found such a case for vhost net device:
> memory_region_notify_one: entry->
In spapr_machine_init() we clamp the size of the RMA to 16GiB and the
comment saying why doesn't make a whole lot of sense. In fact, this was
done because the real mode handling code elsewhere limited the RMA in TCG
mode to the maximum value configurable in LPCR[RMLS], 16GiB.
But,
* Actually LPC
The Real Mode Area (RMA) needs to fit within the NUMA node owning memory
at address 0. That's usually node 0, but can be a later one if there are
some nodes which have no memory (only CPUs).
This is currently handled by the spapr_node0_size() helper. It has only
one caller, so there's not a lot
When the LPCR is written, we update the env->rmls field with the RMA limit
it implies. Simplify things by just calculating the value directly from
the LPCR value when we need it.
It's possible this is a little slower, but it's unlikely to be significant,
since this is only for real mode accesses
Currently we use a big switch statement in ppc_hash64_update_rmls() to work
out what the right RMA limit is based on the LPCR[RMLS] field. There's no
formula for this - it's just an arbitrary mapping defined by the existing
CPU implementations - but we can make it a bit more readable by using a
lo
MIN_RMA_SLOF records the minimum about of RMA that the SLOF firmware
requires. It lets us give a meaningful error if the RMA ends up too small,
rather than just letting SLOF crash.
It's currently stored as a number of megabytes, which is strange for global
constants. Move that megabyte scaling i
POWER "book S" (server class) cpus have a concept of "real mode" where
MMU translation is disabled... sort of. In fact this can mean a bunch
of slightly different things when hypervisor mode and other
considerations are present.
We had some errors in edge cases here, so clean some things up and
c
The Real Mode Area (RMA) is the part of memory which a guest can access
when in real (MMU off) mode. Of course, for a guest under KVM, the MMU
isn't really turned off, it's just in a special translation mode - Virtual
Real Mode Area (VRMA) - which looks like real mode in guest mode.
The mechanics
The table of RMA limits based on the LPCR[RMLS] field is slightly wrong.
We're missing the RMLS == 0 => 256 GiB RMA option, which is available on
POWER8, so add that.
The comment that goes with the table is much more wrong. We *don't* filter
invalid RMLS values when writing the LPCR, and there's
Currently, we construct the SLBE used for VRMA translations when the LPCR
is written (which controls some bits in the SLBE), then use it later for
translations.
This is a bit complex and confusing - simplify it by simply constructing
the SLBE directly from the LPCR when we need it.
Signed-off-by:
For the "pseries" machine, we use "virtual hypervisor" mode where we
only model the CPU in non-hypervisor privileged mode. This means that
we need guest physical addresses within the modelled cpu to be treated
as absolute physical addresses.
We used to do that by clearing LPCR[VPM0] and setting L
When running guests under a hypervisor, the hypervisor obviously needs to
be protected from guest accesses even if those are in what the guest
considers real mode (translation off). The POWER hardware provides two
ways of doing that: The old way has guest real mode accesses simply offset
and bound
When we store the Logical Partitioning Control Register (LPCR) we have a
big switch statement to work out which are valid bits for the cpu model
we're emulating.
As well as being ugly, this isn't really conceptually correct, since it is
based on the mmu_model variable, whereas the LPCR isn't (only
Currently we create the Real Mode Offset Register (RMOR) on all Book3S cpus
from POWER7 onwards. However the translation mode which the RMOR controls
is no longer supported in POWER9, and so the register has been removed from
the architecture.
Remove it from our model on POWER9 and POWER10.
Sign
a4f30719a8cd, way back in 2007 noted that "PowerPC hypervisor mode is not
fundamentally available only for PowerPC 64" and added a 32-bit version
of the MSR[HV] bit.
But nothing was ever really done with that; there is no meaningful support
for 32-bit hypervisor mode 13 years later. Let's stop pr
On ppc we have the concept of virtual hypervisor ("vhyp") mode, where we
only model the non-hypervisor-privileged parts of the cpu. Essentially we
model the hypervisor's behaviour from the point of view of a guest OS, but
we don't model the hypervisor's execution.
In particular, in this mode, qem
This function calculates the maximum size of the RMA as implied by the
host's page size of structure of the VRMA (there are a number of other
constraints on the RMA size which will supersede this one in many
circumstances).
The current interface takes the current RMA size estimate, and clamps it
t
The PowerPC 970 CPU was a cut-down POWER4, which had hypervisor capability.
However, it can be (and often was) strapped into "Apple mode", where the
hypervisor capabilities were disabled (essentially putting it always in
hypervisor mode).
That's actually the only mode of the 970 we support in qemu
Hi Eric
On Thu, Feb 27, 2020 at 9:50 PM Auger Eric wrote:
>
> Hi Daniel,
>
> On 2/27/20 12:17 PM, Daniel P. Berrangé wrote:
> > On Fri, Feb 14, 2020 at 02:27:35PM +0100, Eric Auger wrote:
> >> This series implements the QEMU virtio-iommu device.
> >>
> >> This matches the v0.12 spec (voted) and t
One comment from myself after going through the code...
On 2020/3/3 9:01, Heyi Guo wrote:
Common VM users sometimes care about CPU speed, so we add two new
options to allow VM vendors to present CPU speed to their users.
Normally these information can be fetched from host smbios.
Strictly speak
It is too strict to use assert to make qemu coredump if
the notification does not overlap with registered range.
Skip it is fine enough.
During test, we found such a case for vhost net device:
memory_region_notify_one: entry->iova=0xfee0, entry_end=0xfeff,
notifier->start=0xfef0,
On Tue, Feb 25, 2020 at 04:16:43PM +, Peter Maydell wrote:
> On Tue, 25 Feb 2020 at 16:10, Wayne Li wrote:
> > So what could be causing this problem? I’m guessing it has something
> > to do with the translation lookaside buffers (TLBs)? But the
> > translation between virtual and physical me
On 3/2/2020 10:34 PM, Stefan Hajnoczi wrote:
> On Thu, Feb 27, 2020 at 2:42 AM Pan Nengyuan wrote:
>>
>> This patch fix memleaks when we call tests/qtest/cpu-plug-test on s390x. The
>> leak stack is as follow:
>>
>> Direct leak of 48 byte(s) in 1 object(s) allocated from:
>> #0 0x7fb43c7cd
On 3/3/2020 3:17 AM, Mark Cave-Ayland wrote:
> On 02/03/2020 13:21, Peter Maydell wrote:
>
>> On Thu, 27 Feb 2020 at 02:35, Pan Nengyuan wrote:
>>>
>>> There are some memleaks when we call 'device_list_properties'. This patch
>>> move timer_new from init into realize to fix it.
>>> Meanwhile,
On 3/2/2020 9:21 PM, Peter Maydell wrote:
> On Thu, 27 Feb 2020 at 02:35, Pan Nengyuan wrote:
>>
>> This series delay timer_new from init into realize to avoid memleaks when we
>> call 'device_list_properties'.
>> And do timer_free only in s390x_cpu_finalize because it's hotplugable.
>> Howev
On 2020/3/2 21:52, Igor Mammedov wrote:
On Mon, 2 Mar 2020 17:29:10 +0800
Heyi Guo wrote:
Common VM users sometimes care about CPU speed, so we add two new
options to allow VM vendors to present CPU speed to their users.
Normally these information can be fetched from host smbios.
Strictly s
Common VM users sometimes care about CPU speed, so we add two new
options to allow VM vendors to present CPU speed to their users.
Normally these information can be fetched from host smbios.
Strictly speaking, the "max speed" and "current speed" in type 4
are not really for the max speed and curre
From: Anup Patel
Currently, TIME CSRs are emulated only for user-only mode. This
patch add TIME CSRs emulation for privileged mode.
For privileged mode, the TIME CSRs will return value provided
by rdtime callback which is registered by QEMU machine/platform
emulation (i.e. CLINT emulation). If r
From: Alistair Francis
Add a helper macro MSTATUS_MPV_ISSET() which will determine if the
MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 11 +++
target
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c| 3 +++
target/riscv/cpu.h| 10 ++
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 17 +
target/risc
From: Anup Patel
This patch extends CLINT emulation to provide rdtime callback for
TCG. This rdtime callback will be called wheneven TIME CSRs are
read in privileged modes.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_clint.c
From: Alistair Francis
mark_fs_dirty() is the only place in translate.c that uses the
virt_enabled bool. Let's respect the contents of MSTATUS.MPRV and
HSTATUS.SPRV when setting the bool as this is used for performing
floating point operations when V=0.
Signed-off-by: Alistair Francis
Reviewed-
From: Bin Meng
When testing e1000 with the virt machine, e1000's I/O space cannot
be accessed. Debugging shows that the I/O BAR (BAR1) is correctly
written with address 0 plus I/O enable bit, but QEMU's "info pci"
shows that:
Bus 0, device 1, function 0:
Ethernet controller: PCI device
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 5 +
target/riscv/cpu.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b27066f6a7..c47d10b739 1006
From: Alistair Francis
The hret instruction does not exist in the new spec versions, so remove
it from QEMU.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 1 -
target/riscv/insn_trans/trans_privi
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9e28b19c29..d3b764e694 100
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
in
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 193 ++
2 files changed, 175 insertions(+), 19 deletions(-)
diff --git a/tar
From: Alistair Francis
Mark both sstatus and vsstatus as dirty (3).
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/riscv/translate.c b/target/risc
From: Alistair Francis
When the Hypervisor extension is in use we only enable floating point
support when both status and vsstatus have enabled floating point
support.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 3
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 24
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index c0e942684d..91867
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode| 23 ++-
.../riscv/insn_trans/trans_privileged.inc.c | 40 +++
2 files changed, 54 insertions(+), 9 del
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 37 -
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cp
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 69 +--
1 file changed, 59 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/op_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index e87c9115bc..455eb289
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5b889a0065..aa04e5cca7 100644
--- a/tar
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 33 -
1 file changed, 28 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_he
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/op_helper.c | 62 +---
1 file changed, 52 insertions(+), 10 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f7333286bd..c0e942684d 100644
--- a/target/riscv/csr.c
+
From: Alistair Francis
To ensure our TLB isn't out-of-date we flush it on all virt mode
changes. Unlike priv mode this isn't saved in the mmu_idx as all
guests share V=1. The easiest option is just to flush on all changes.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h| 11 +++
target/riscv/cpu_bits.h | 7 +
target/riscv/cpu_helper.c | 61 +++
3 files changed, 79 insert
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 918678789a..2e6700bbeb 100644
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 6 +++---
target/riscv/cpu_bits.h | 12 ++--
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 116 +
1 file changed, 116 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index bee639e92e
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 3fa8d2cfda..f7333286bd 100644
From: Alistair Francis
Dump the Hypervisor registers and the current Hypervisor state.
While we are editing this code let's also dump stvec and scause.
Signed-off-by: Alistair Francis
Signed-off-by: Atish Patra
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.
From: Alistair Francis
Add a FORCE_HS_EXCEP mode to the RISC-V virtulisation status. This bit
specifies if an exeption should be taken to HS mode no matter the
current delegation status. This is used when an exeption must be taken
to HS mode, such as when handling interrupts.
Signed-off-by: Alis
From: Alistair Francis
Add the Hypervisor CSRs to CPUState and at the same time (to avoid
bisect issues) update the CSR macros for the v0.5 Hyp spec.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 21 +++
From: Alistair Francis
Update the CSR permission checking to work correctly when we are in
HS-mode.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h| 4
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 18 ++
3 files changed, 25 insertions(+)
diff --git a/targ
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 136 -
1 file changed, 134 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Chih-Min Chao
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 95de9e58a2..010125efd6 100644
-
From: Alistair Francis
The v0.5 Hypervisor spec add new execption numbers, let's add support
for those.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c| 8
target/riscv/cpu_bits.h | 35 +++---
From: Alistair Francis
The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access.
Now that we don't use atomics for MIP we can change this back to a xlen
CSR.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 2 +-
The following changes since commit 8b6b68e05b43f976714ca1d2afe01a64e1d82cba:
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
(2020-02-27 19:15:15 +)
are available in the Git repository at:
g...@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf3
f
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d5de7f468a..eff064dc44 100644
---
When malta is coupled with MIPS64 cpu which have 64bit
address space, it is possible to have more than 2G RAM.
So we removed ram_size check and overwrite memory
layout for these targets.
Signed-off-by: Jiaxun Yang
Suggested-by: Yunqiang Su
--
v1: Do not overwrite cmdline when we don't have high
On 3/3/2020 1:19 AM, Eduardo Habkost wrote:
On Mon, Mar 02, 2020 at 07:47:28PM +0800, Tao Xu wrote:
On 2/29/2020 5:39 AM, Eduardo Habkost wrote:
On Wed, Feb 12, 2020 at 04:13:26PM +0800, Tao Xu wrote:
Add new version of Snowridge, Denverton, Opteron_G3, EPYC, and Dhyana
CPU model to uremove MO
On 3/2/20 3:16 PM, BALATON Zoltan wrote:
>> (2) IEEE has a number of implementation choices for corner cases, and we need
>> to implement the target's choices, not the host's choices.
>
> But how is that related to inexact flag and float_round_nearest_even rounding
> mode which are the only two th
On Mon, Feb 24, 2020 at 9:02 PM Bin Meng wrote:
>
> Hi Alistair,
>
> On Tue, Feb 25, 2020 at 5:14 AM Alistair Francis wrote:
> >
> > On Sun, Feb 16, 2020 at 5:56 AM Bin Meng wrote:
> > >
> > > At present the board serial number is hard-coded to 1, and passed
> > > to OTP model during initializat
s390zp12:~ # cat test.sh
/root/qemu/s390x-softmmu/qemu-system-s390x \
-machine s390-ccw-virtio,accel=kvm \
-nographic \
-bios /root/qemu/pc-bios/s390-ccw/s390-ccw.img \
-device
vfio-ccw,id=hostdev0,sysfsdev=/sys/bus/mdev/devices/08e8c006-146d-48d3-b21a-c005f9d3a04b,devno=fe.0.1234,bootindex=1
\
-
Public bug reported:
qemu latest
kernel 5.3.18
I am using a passthrough dasd as boot device, the installment looks fine
and gets into reboot process. However VM could not boot and just hang as
below after that. I have been checking on "s390: vfio-ccw dasd ipl
support" series right now but no clue
On 3/2/20 10:22 PM, Aleksandar Markovic wrote:
Forwarding this to Igor. Can you please give us your opinion, Igor, on this
proposal?
I'm not sure it is Igor area.
What need to be reviewed here is the GT64120 north bridge, which works
very well with the default config, but is fragile when mod
On 3/2/20 6:58 PM, Richard Henderson wrote:
The function does not write registers, and only reads them by
implication via the exception path.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff -
On 3/2/20 6:58 PM, Richard Henderson wrote:
This is an aarch64-only function. Move it out of the shared file.
This patch is code movement only.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.h | 1 +
target/arm/helper.h | 1 -
target/arm/helper
On 3/2/20 6:58 PM, Richard Henderson wrote:
If by context we know that we're in AArch64 mode, we need not
test for M-profile when reconstructing the full ARMMMUIdx.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 6 ++
target/arm/translate-a64.c | 2 +-
2 files changed
On 3/2/20 6:58 PM, Richard Henderson wrote:
Replicate the single TBI bit from TCR_EL2 and TCR_EL3 so that
we can unconditionally use pointer bit 55 to index into our
composite TBI1:TBI0 field.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 6 --
1
On 3/2/20 9:58 PM, Aleksandar Markovic wrote:
From: Peter Maydell
Sent: Monday, March 2, 2020 9:26 PM
To: Aleksandar Markovic
Cc: QEMU Developers; Aleksandar Markovic; Philippe Mathieu-Daudé
Subject: [EXTERNAL]Re: [PULL 5/5] tests/acceptance: Count multiple Tux logos
displayed on framebuffer
O
On Mon, Mar 2, 2020 at 8:08 PM Volker Rümelin wrote:
> Patch "audio: change naming scheme of FLOAT_CONV macros" and
> patch "audio: consistency changes" should have been a review
> for ed2a4a7941 "audio: proper support for float samples in
> mixeng", but I was too slow.
>
> Patch "audio: change m
On Mon, 2 Mar 2020, Mark Cave-Ayland wrote:
On 02/03/2020 08:10, Markus Armbruster wrote:
BALATON Zoltan writes:
On Sun, 1 Mar 2020, Mark Cave-Ayland wrote:
On 29/02/2020 23:02, BALATON Zoltan wrote:
We'll need a flag for implementing some device specific behaviour in
via-ide but we already
On 3/2/20 8:14 PM, Helge Deller wrote:
Reduce the default emulated screen size to 800x600 pixel instead of
1280x1024 pixel. With the bigger screen size the emulated graphic card
isn't fully visible on my laptop display, and if people want bigger
sizes it's possible to define it on the command lin
On 3/2/20 9:34 PM, Helge Deller wrote:
* Peter Maydell :
On Mon, 2 Mar 2020 at 19:23, Helge Deller wrote:
On 17.02.20 18:56, Peter Maydell wrote:
On Fri, 24 Jan 2020 at 23:20, Richard Henderson
wrote:
From: Helge Deller
LASI is a built-in multi-I/O chip which supports serial, parallel,
From: Alex Bennée
It appears ignore the decoration if just applied to the class.
Fixes: 0484d9d4fbe9beacd
Signed-off-by: Alex Bennée
[PMD: Move decorations to each test function]
Signed-off-by: Philippe Mathieu-Daudé
---
tests/acceptance/machine_mips_malta.py | 8 ++--
1 file changed, 6 i
On Mon, 2 Mar 2020, Richard Henderson wrote:
On 3/2/20 3:42 AM, BALATON Zoltan wrote:
The "hardfloat" option works (with other targets) only with ieee745
accumulative exceptions, when the most common of those exceptions, inexact, has
already been raised. And thus need not be raised a second tim
On Mon, 2 Mar 2020, Alex Bennée wrote:
BALATON Zoltan writes:
On Sun, 1 Mar 2020, Richard Henderson wrote:
On 3/1/20 4:13 PM, Programmingkid wrote:
Ok, I was just looking at Intel's x87 chip documentation. It
supports IEEE 754 floating point operations and exception flags.
This leads me to th
Il lun 2 mar 2020, 22:11 Kamil Rytarowski ha scritto:
> > The difference is that KVM for example does not need external includes
> > or libraries.
>
We don't support this scenario
What scenario?
and after a year there might be no
> supported release without NVMM.
>
> The only concern is about
On Mon, Mar 02, 2020 at 05:47:45PM +, Daniel P. Berrangé wrote:
> On Mon, Mar 02, 2020 at 06:36:13PM +0100, Philippe Mathieu-Daudé wrote:
> > typo "multi" in patch subject.
> >
Thank Philippe, will fix.
> > On 2/24/20 9:55 PM, Jagannathan Raman wrote:
> > > From: Elena Ufimtseva
> > >
> > >
Hi Philippe,
On Mon, Mar 2, 2020 at 7:04 PM Philippe Mathieu-Daudé
wrote:
> On 3/2/20 4:44 PM, Peter Maydell wrote:
> > On Thu, 27 Feb 2020 at 22:02, Niek Linnenbank
> wrote:
> >>
> >> The Cubieboard machine does not support the -bios argument.
> >> Report an error when -bios is used and exit i
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