On 2020/3/14 17:10, Richard Henderson wrote:
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
+/* Vector Floating-Point Classify Instruction */
+static uint16_t fclass_f16(uint16_t frs1, float_status *s)
+{
+float16 f = frs1;
+bool sign = float16_is_neg(f);
+
+if (float16_is_infinity(f)) {
+
On 2020/3/14 17:08, Richard Henderson wrote:
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
+static uint8_t float16_eq_quiet(uint16_t a, uint16_t b, float_status *s)
+{
+int compare = float16_compare_quiet(a, b, s);
+if (compare == float_relation_equal) {
+return 1;
+} else {
+
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +/* Vector Floating-Point Classify Instruction */
> +static uint16_t fclass_f16(uint16_t frs1, float_status *s)
> +{
> +float16 f = frs1;
> +bool sign = float16_is_neg(f);
> +
> +if (float16_is_infinity(f)) {
> +return sign ? 1 << 0 : 1 <<
Hi Aleksandar,
(+Aurelien for Debian)
(+Peter regarding changing default)
On 3/14/20 4:25 AM, Aleksandar Markovic wrote:
On Thu, Mar 5, 2020 at 11:18 AM Philippe Mathieu-Daudé
wrote:
Please post new patches as v2, and do not post them as reply to v1.
On 3/3/20 1:41 AM, Jiaxun Yang wrote:
W
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +static uint8_t float16_eq_quiet(uint16_t a, uint16_t b, float_status *s)
> +{
> +int compare = float16_compare_quiet(a, b, s);
> +if (compare == float_relation_equal) {
> +return 1;
> +} else {
> +return 0;
> +}
> +}
You real
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/helper.h | 19 +++
> target/riscv/insn32.decode | 6 ++
> target/riscv/insn_trans/trans_rvv.inc.c | 8 +++
> target/riscv/vector_helper.c| 76 +++
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_max)
> +RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_max)
> +RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_max)
> +GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2, clearh)
> +GEN_VEXT_VV_ENV
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/helper.h | 17 +
> target/riscv/insn32.decode | 8 +++
> target/riscv/insn_trans/trans_rvv.inc.c | 10 +++
> target/riscv/vector_helper.c| 84
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/helper.h | 49 +
> target/riscv/insn32.decode | 16 ++
> target/riscv/insn_trans/trans_rvv.inc.c | 18 ++
> target/riscv/vector_helper.c| 228 ++
Patchew URL:
https://patchew.org/QEMU/20200314084730.25876-1-pannengy...@huawei.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v5 0/4] delay timer_new from init to realize to fix memleaks.
Message-id: 20200314084730.25876-
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/helper.h | 5 +
> target/riscv/insn32.decode | 2 ++
> target/riscv/insn_trans/trans_rvv.inc.c | 4
> target/riscv/vector_helper.c| 22
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/helper.h | 16 +
> target/riscv/insn32.decode | 5 +++
> target/riscv/insn_trans/trans_rvv.inc.c | 7
> target/riscv/vector_helper.c| 48 +++
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/helper.h | 17 +++
> target/riscv/insn32.decode | 8 ++
> target/riscv/insn_trans/trans_rvv.inc.c | 131
> target/riscv/vector_helper.c| 7
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/helper.h | 16
> target/riscv/insn32.decode | 5 ++
> target/riscv/insn_trans/trans_rvv.inc.c | 107
> target/riscv/vector_helper.c|
This patch fix a bug in mac_via where it failed to actually realize devices it
was using.
And move the init codes which inits the mos6522 objects and properties on them
from realize()
into init(). However, we keep qdev_set_parent_bus in realize(), otherwise it
will cause
device-introspect-test t
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +static int8_t vnclip8(CPURISCVState *env, int16_t a, int8_t b)
> +{
> +uint8_t round, shift = b & 0xf;
> +int16_t res;
> +
> +round = get_round(env, a, shift);
> +res = (a >> shift) + round;
> +if (res > INT8_MAX) {
> +env->vxs
There are two other places where we create mos6522's subclasses but forgot to
realize
it. This patch do the realize in these places to fix that.
Signed-off-by: Pan Nengyuan
---
Cc: Mark Cave-Ayland
Cc: David Gibson
Cc: qemu-...@nongnu.org
---
v5:
- Also fix incorrect creation of mos6522's subc
There are some memleaks when we call 'device_list_properties'.
This patch move timer_new from init into realize to fix it.
Reported-by: Euler Robot
Signed-off-by: Pan Nengyuan
---
Cc: Laurent Vivier
Cc: Mark Cave-Ayland
Cc: David Gibson
Cc: qemu-...@nongnu.org
---
v2->v1:
- no changes in this
This patch fix memleaks when we call tests/qtest/cpu-plug-test on s390x. The
leak stack is as follow:
Direct leak of 48 byte(s) in 1 object(s) allocated from:
#0 0x7fb43c7cd970 in __interceptor_calloc (/lib64/libasan.so.5+0xef970)
#1 0x7fb43be2149d in g_malloc0 (/lib64/libglib-2.0.so.0+0x
This series delay timer_new from init into realize to avoid memleaks when we
call 'device_list_properties'.
And do timer_free only in s390x_cpu_finalize because it's hotplugable. However,
mos6522_realize is never called
at all due to the incorrect creation of it. So we fix the incorrect creation
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +static uint8_t vssrl8(CPURISCVState *env, uint8_t a, uint8_t b)
> +{
> +uint8_t round, shift = b & 0x7;
> +uint8_t res;
> +
> +round = get_round(env, a, shift);
> +res = (a >> shift) + round;
> +return res;
> +}
> +static uint16_t vssr
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +static uint16_t vwsmaccu8(CPURISCVState *env, uint8_t a, uint8_t b,
> +uint16_t c)
> +{
> +uint8_t round;
> +uint16_t res = (uint16_t)a * (uint16_t)b;
> +
> +round = get_round(env, res, 4);
> +res = (res >> 4) + round;
> +return sad
On 3/13/20 11:38 PM, Liran Alon wrote:
On 13/03/2020 21:57, Philippe Mathieu-Daudé wrote:
On 3/12/20 5:54 PM, Liran Alon wrote:
No functional change. This is mere refactoring.
Suggested-by: Michael S. Tsirkin
Signed-off-by: Liran Alon
---
hw/i386/pc.c | 1 +
hw/i386/vmmouse.c
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
> +static inline int8_t vsmul8(CPURISCVState *env, int8_t a, int8_t b)
> +{
> +uint8_t round;
> +int16_t res;
> +
> +res = (int16_t)a * (int16_t)b;
> +round = get_roun
On 3/13/20 11:44 PM, Liran Alon wrote:
On 13/03/2020 22:07, Philippe Mathieu-Daudé wrote:
On 3/12/20 5:54 PM, Liran Alon wrote:
diff --git a/include/hw/i386/vmport.h b/include/hw/i386/vmport.h
index 34cc050b1ffa..aee809521aa0 100644
--- a/include/hw/i386/vmport.h
+++ b/include/hw/i386/vmport.h
On 3/14/20 1:14 AM, Richard Henderson wrote:
> I think you should have 4 versions of aadd8, for each of the rounding modes,
>
>> +RVVCALL(OPIVV2_ENV, vaadd_vv_b, OP_SSS_B, H1, H1, H1, aadd8)
>
> then use this, or something like it, to define 4 functions containing main
> loops, which will get the
On 3/14/20 1:23 AM, Marc-André Lureau wrote:
Hi
On Fri, Mar 13, 2020 at 7:42 PM Philippe Mathieu-Daudé
wrote:
Signed-off-by: Philippe Mathieu-Daudé
Without looking at the rest of the series, I fail to see the
improvement, quite the opposite. A bit of context?
You are right this not need
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +/* Vector Single-Width Averaging Add and Subtract */
> +static inline uint8_t get_round(CPURISCVState *env, uint64_t v, uint8_t
> shift)
> +{
> +uint8_t d = extract64(v, shift, 1);
> +uint8_t d1;
> +uint64_t D1, D2;
> +int mod = env->vxrm;
>
On 2020/3/14 13:25, Richard Henderson wrote:
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
+if (a->vm && s->vl_eq_vlmax) { \
+tcg_gen_gvec_##GVSUF(8 << s->sew, vreg_ofs(s, a->rd), \
+vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1), \
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +/* Vector Single-Width Saturating Add and Subtract */
> +GEN_OPIVV_GVEC_TRANS(vsaddu_vv, usadd)
> +GEN_OPIVV_GVEC_TRANS(vsadd_vv, ssadd)
> +GEN_OPIVV_GVEC_TRANS(vssubu_vv, ussub)
> +GEN_OPIVV_GVEC_TRANS(vssub_vv, sssub)
> +GEN_OPIVX_TRANS(vsaddu_vx, opivx
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/helper.h | 22
> target/riscv/insn32.decode | 7
> target/riscv/insn_trans/trans_rvv.inc.c | 9 +
> target/riscv/vector_helper.c| 45 ++
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +/* Vector Integer Merge and Move Instructions */
> +static bool opivv_vmerge_check(DisasContext *s, arg_rmrr *a)
> +{
> +return (vext_check_isa_ill(s, RVV) &&
> +vext_check_overlap_mask(s, a->rd, a->vm, false) &&
> +vext_check_reg
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +#define OPIVX3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
> +static void do_##NAME(void *vd, target_ulong s1, void *vs2, int i) \
> +{ \
> +TX2 s2 = *((T2 *)vs2 + HS2(i));
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/helper.h | 19 +
> target/riscv/insn32.decode | 6 +++
> target/riscv/insn_trans/trans_rvv.inc.c | 8
> target/riscv/vector_helper.c| 51 +++
On 2020/3/14 14:52, Richard Henderson wrote:
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
+static int64_t do_mulhsu_d(int64_t s2, uint64_t s1)
+{
+uint64_t hi_64, lo_64, abs_s2 = s2;
+
+if (s2 < 0) {
+abs_s2 = -s2;
+}
+mulu64(&lo_64, &hi_64, abs_s2, s1);
+if ((int64_t)(s2
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