The logic of this function remains pretty much the same, except that
it uses count_contiguous_subclusters(), which combines the logic of
count_contiguous_clusters() / count_contiguous_clusters_unallocated()
and checks individual subclusters.
Signed-off-by: Alberto Garcia
---
block/qcow2.h
Two changes are needed in this function:
1) A full discard deallocates a cluster so we can skip the operation if
it is already unallocated. With extended L2 entries however if any
of the subclusters has the 'all zeroes' bit set then we have to
clear it.
2) Setting the QCOW_OFLAG_ZERO
This function will be used by the qcow2 code to check if an image has
subclusters or not.
At the moment this simply returns false. Once all patches needed for
subcluster support are ready then QEMU will be able to create and
read images with subclusters and this function will return the actual
l2meta_cow_start() and l2meta_cow_end() are not necessarily
cluster-aligned if the image has subclusters, so update the
calculation of old_start and old_end to guarantee that no two requests
try to write on the same cluster.
Signed-off-by: Alberto Garcia
Reviewed-by: Max Reitz
---
Extended L2 entries are 128-bit wide: 64 bits for the entry itself and
64 bits for the subcluster allocation bitmap.
In order to support them correctly get/set_l2_entry() need to be
updated so they take the entry width into account in order to
calculate the correct offset.
This patch also adds
When writing to a qcow2 file there are two functions that take a
virtual offset and return a host offset, possibly allocating new
clusters if necessary:
- handle_copied() looks for normal data clusters that are already
allocated and have a reference count of 1. In those clusters we
When dealing with subcluster types there is a new value called
QCOW2_SUBCLUSTER_UNALLOCATED_ALLOC that has no equivalent in
QCow2ClusterType.
This patch handles that value in all places where subcluster types
are processed.
Signed-off-by: Alberto Garcia
Reviewed-by: Max Reitz
---
In order to support extended L2 entries some functions of the qcow2
driver need to start dealing with subclusters instead of clusters.
qcow2_get_host_offset() is modified to return the subcluster type
instead of the cluster type, and all callers are updated to replace
all values of
git shortlog
126c04acbabd7ad32c2b018fe10dfac2a3bc1210..7012a2c62e5b54eab88c119383022ec7ce86e9b2
5eraph (1):
Use specific outbound IP address
Akihiro Suda (8):
remove confusing comment that exists from ancient slirp
add slirp_new(SlirpConfig *, SlirpCb *, void *)
allow
qcow2_get_cluster_offset() takes an (unaligned) guest offset and
returns the (aligned) offset of the corresponding cluster in the qcow2
image.
In practice none of the callers need to know where the cluster starts
so this patch makes the function calculate and return the final host
offset
Extended L2 entries are bigger than normal L2 entries so this has an
impact on the amount of metadata needed for a qcow2 file.
Signed-off-by: Alberto Garcia
Reviewed-by: Max Reitz
---
block/qcow2.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git
For a given offset, return the subcluster number within its cluster
(i.e. with 32 subclusters per cluster it returns a number between 0
and 31).
Signed-off-by: Alberto Garcia
Reviewed-by: Max Reitz
---
block/qcow2.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/block/qcow2.h
On Wed, 11 Mar 2020 09:21:51 -0400
Janosch Frank wrote:
> From: Christian Borntraeger
>
> The unpack facility is an indication that diagnose 308 subcodes 8-10
> are available to the guest. That means, that the guest can put itself
> into protected mode.
>
> Once it is in protected mode, the
On 10/03/20 01:40, Liran Alon wrote:
> Some guests are only familiar with VMware PV interface. Therefore, in
> order for these guests to run properly on KVM, we need to be able to
> expose VMware main CPUID leaf. i.e. leaf 0x4000.
>
> E.g. Without exposing this VMware CPUID leaf, some guests
From: Changbin Du
Recently when debugging an arm32 system on qemu, I found sometimes the
single-step command (stepi) is not working. This can be reproduced by
below steps:
1) start qemu-system-arm -s -S .. and wait for gdb connection.
2) start gdb and connect to qemu. In my case, gdb gets a
On 3/17/20 1:55 PM, Eric Blake wrote:
> glib's G_DEFINE_AUTOPTR_CLEANUP_FUNC() macro defines several static
> inline functions, often with some of them unused, but prior to 2.57.2
> did not mark the functions as such. As a result, clang (but not gcc)
> fails to build with older glib unless
On Tue, 17 Mar 2020 at 17:55, Eric Blake wrote:
>
> glib's G_DEFINE_AUTOPTR_CLEANUP_FUNC() macro defines several static
> inline functions, often with some of them unused, but prior to 2.57.2
> did not mark the functions as such. As a result, clang (but not gcc)
> fails to build with older glib
The Linux kernel chooses the default of 64 bytes for SVE registers on
the basis that it is the largest size on known hardware that won't
grow the signal frame. We still honour the sve-max-vq property and
userspace can expand the number of lanes by calling PR_SVE_SET_VL.
This should not make any
This is useful, especially when testing relatively new gdbstub
features that might not be in distro packages yet.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20200316172155.971-22-alex.ben...@linaro.org>
diff --git a/configure b/configure
index
This is a fairly bare-bones test of setting the various vector sizes
for SVE which will only fail if the PR_SVE_SET_VL can't reduce the
user-space vector length by powers of 2.
However we will also be able to use it in a future test which
exercises the GDB stub.
Signed-off-by: Alex Bennée
From: Damien Hedde
Remove the packet size upper limit by using a GByteArray
instead of a statically allocated array for last_packet.
Thus we can now send big packets.
Also remove the last_packet_len field and use last_packet->len
instead.
Signed-off-by: Damien Hedde
Reviewed-by: Philippe
glib's G_DEFINE_AUTOPTR_CLEANUP_FUNC() macro defines several static
inline functions, often with some of them unused, but prior to 2.57.2
did not mark the functions as such. As a result, clang (but not gcc)
fails to build with older glib unless -Wno-unused-function is enabled.
Reported-by: Peter
We also expose a the helpers to read/write the the registers.
Signed-off-by: Alex Bennée
Acked-by: Richard Henderson
Message-Id: <20200316172155.971-19-alex.ben...@linaro.org>
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index fbfd73a7b5b..8b9f2961ba0 100644
--- a/target/arm/cpu.h
+++
From: Damien Hedde
Since we can now send packets of arbitrary length:
simplify gdb_monitor_write() and send the whole payload
in one packet.
Suggested-by: Luc Michel
Signed-off-by: Damien Hedde
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id:
The test runners job is to start QEMU with guest debug enabled and
then spawn a gdb process running a test script that exercises the
functionality it wants to test.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Message-Id:
This tests a bunch of registers that the kernel allows userspace to
read including the CPUID registers. We need a SVE aware compiler as we
are testing the id_aa64zfr0_el1 register in the set.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id:
This is cleaner than poking memory directly and will make later
clean-ups easier.
Signed-off-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20200316172155.971-14-alex.ben...@linaro.org>
diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c
index 572ead641ca..e4d8cb66c00
For system emulation we need to check the state of the GIC before we
report the value. However this isn't relevant to exporting of the
value to linux-user and indeed breaks the exported value as set by
modify_arm_cp_regs.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Reviewed-by:
On 3/17/20 11:05 AM, BALATON Zoltan wrote:
> Avoid problems from reassigning variable in piix4_create and fix
> compilation problem with mips_r4k
>
> BALATON Zoltan (8):
> hw/ide: Get rid of piix3_init functions
> hw/isa/piix4.c: Introduce variable to store devfn
> hw/ide: Get rid of
We will want to generate similar dynamic XML for gdbstub support of
SVE registers (the upstream doesn't use XML). To that end lightly
rename a few things to make the distinction.
Signed-off-by: Alex Bennée
Acked-by: Richard Henderson
Message-Id: <20200316172155.971-16-alex.ben...@linaro.org>
Instead of passing a pointer to memory now just extend the GByteArray
to all the read register helpers. They can then safely append their
data through the normal way. We don't bother with this abstraction for
write registers as we have already ensured the buffer being copied
from is the correct
A very simple test case which sets and reads SVE registers while
running a test case. We don't really need to compile a SVE binary for
this case but we will later so keep it simple for now.
Signed-off-by: Alex Bennée
Tested-by: Philippe Mathieu-Daudé
Message-Id:
This test exercises the gdbstub while runing the sve-iotcl test. I
haven't plubmed it into make system as we need a way of verifying if
gdb has the right support for SVE.
Signed-off-by: Alex Bennée
Message-Id: <20200316172155.971-26-alex.ben...@linaro.org>
diff --git
This is in preparation for further re-factoring of the register API
with the rest of the code. Theoretically the read register function
could overwrite the MAX_PACKET_LENGTH buffer although currently all
registers are well within the size range.
Signed-off-by: Alex Bennée
Reviewed-by: Richard
This is described as optional but I'm not convinced of the numbering
when multiple target fragments are sent.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20200316172155.971-17-alex.ben...@linaro.org>
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index
Rather than having a static buffer replace str_buf with a GString
which we know can grow on demand. Convert the internal functions to
take a GString instead of a char * and length.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Reviewed-by: Damien Hedde
Tested-by: Damien Hedde
This is cleaner than poking memory directly and will make later
clean-ups easier.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Reviewed-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20200316172155.971-13-alex.ben...@linaro.org>
diff --git
We only have one GDBState which should be allocated at the time we
process any commands. This will make further clean-up a bit easier.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Reviewed-by: Damien Hedde
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
This is cleaner than poking memory directly and will make later
clean-ups easier.
Signed-off-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20200316172155.971-12-alex.ben...@linaro.org>
diff --git a/target/arm/helper.c b/target/arm/helper.c
Instead of allocating make this entirely static. We shall reduce the
size of the structure in later commits and dynamically allocate parts
of it. We introduce an init and reset helper function to keep all the
manipulation in one place.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20200316172155.971-11-alex.ben...@linaro.org>
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index 08363969c14..59e366ba3af 100644
--- a/include/exec/gdbstub.h
+++
From: Philippe Mathieu-Daudé
The GLX configure option has been removed in 71c75f201d [*].
We missed that when updating to v0.7.0 in commit fab3220f97.
This silents:
configure: creating ./config.status
config.status: creating virglrenderer.pc
...
configure: WARNING: unrecognized
From: Philippe Mathieu-Daudé
We often run Linux kernels to test QEMU. We sometimes need
to build them manually to use non-default features. We only
miss the tiny 'bc' tool.
The ncurses library is helpful to run 'make menuconfig'.
Finally, gdb-multiarch allow us to debug a TCG guest when its
From: Philippe Mathieu-Daudé
Building the qemu:debian-amd64 fails when building VirGL:
make[2]: Entering directory '/usr/src/virglrenderer/src/gallium/auxiliary'
CC cso_cache/cso_cache.lo
CC cso_cache/cso_hash.lo
CC os/os_misc.lo
CC util/u_debug.lo
The following changes since commit 6fb1603aa24d9212493e4819d7b685be9c9aad7a:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200317'
into staging (2020-03-17 14:44:50 +)
are available in the Git repository at:
https://github.com/stsquad/qemu.git tags/pull-testing
From: Philippe Mathieu-Daudé
Since commit f5852efa293 we can display GLib errors with the QEMU
error reporting API. Set it to the 'error' level, as this helps
understanding failures from QEMU calls to GLib on Travis-CI.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
From: Philippe Mathieu-Daudé
freedesktop.org is moving to a GitLab instance,
use the new url.
- https://www.fooishbar.org/blog/gitlab-fdo-introduction/
- https://gitlab.freedesktop.org/freedesktop/freedesktop/-/wikis/home
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
Introduce new 'multidevs' option for filesystem.
This option prevents misbheaviours on guest if a 9pfs export
contains multiple devices, due to the potential file ID collisions
this otherwise may cause.
Signed-off-by: Christian Schoenebeck
---
docs/formatdomain.html.in |
QEMU 4.2 added a new option 'multidevs' for 9pfs. The following patch adds
support for this new option to libvirt.
In short, what is this about: to distinguish files uniquely from each other
in general, numeric file IDs are typically used for comparison, which in
practice is the combination of a
Gentle ping (A week have passed since submission).
Thanks,
-Liran
On 10/03/2020 2:40, Liran Alon wrote:
Some guests are only familiar with VMware PV interface. Therefore, in
order for these guests to run properly on KVM, we need to be able to
expose VMware main CPUID leaf. i.e. leaf
Peter Maydell wrote:
> On Fri, 28 Feb 2020 at 09:28, Juan Quintela wrote:
>>
>> Add it to several build systems to make testing good.
>>
>> Signed-off-by: Juan Quintela
>> Reviewed-by: Dr. David Alan Gilbert
>> ---
>> .gitlab-ci.yml| 1 +
>> .travis.yml
On Tue, 17 Mar 2020 at 13:04, Aleksandar Markovic
wrote:
>
> From: Aleksandar Markovic
>
> The following changes since commit a98135f727595382e200d04c2996e868b7925a01:
>
> Merge remote-tracking branch
> 'remotes/kraxel/tags/vga-20200316-pull-request' into staging (2020-03-16
> 14:55:59
Hello,
I'm not sure whether the commit
(https://github.com/qemu/qemu/commit/f51d0b4178738bba87d796eba7444f6cdb3aa0fd)
can patch
to qemu-4.1.0 or qemu-4.2.0 directly.
After going through the COLO flow, the commit seems an individual
patch and to resolve double-allocate colo_cache issue, right?
Do you have the problem with 4.2.0?
Can you identify the commit introducing the problem?
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https://bugs.launchpad.net/bugs/1867786
Title:
Qemu PPC64 freezes with multi-core CPU
Status
It's soft emulation, running Qemu 4.2.50 (from master branch) on MacOS
Mojave.
--
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https://bugs.launchpad.net/bugs/1867786
Title:
Qemu PPC64 freezes with multi-core CPU
Status in QEMU:
On Fri, 28 Feb 2020 at 09:28, Juan Quintela wrote:
>
> Add it to several build systems to make testing good.
>
> Signed-off-by: Juan Quintela
> Reviewed-by: Dr. David Alan Gilbert
> ---
> .gitlab-ci.yml| 1 +
> .travis.yml | 1
Vector extension is default off. The only way to use vector extension is
1. use cpu rv32 or rv64
2. turn on it by command line
"-cpu rv64,x-v=true,vlen=128,elen=64,vext_spec=v0.7.1".
vlen is the vector register length, default value is 128 bit.
elen is the max operator size in bits, default value
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 28 +
target/riscv/vector_helper.c| 28
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9 ++
target/riscv/insn32.decode | 3 +
target/riscv/insn_trans/trans_rvv.inc.c | 127
target/riscv/vector_helper.c| 64
4 files changed, 203 insertions(+)
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_rvv.inc.c | 17
target/riscv/vector_helper.c| 128
4 files changed, 169 insertions(+)
diff
On Thu, 12 Mar 2020 12:25:10 -0400
Janosch Frank wrote:
> Let's bail out of the protected transition if we detect that huge
> pages might be in use.
>
> Signed-off-by: Janosch Frank
> ---
>
> I'd like to squash this into the unpack patch to give a proper error
> message if we try to
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 72 +
target/riscv/vector_helper.c| 15 ++
4 files changed, 93 insertions(+)
diff
Is this with KVM or with TCG?
What is your hardware configuration?
--
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https://bugs.launchpad.net/bugs/1867786
Title:
Qemu PPC64 freezes with multi-core CPU
Status in QEMU:
New
Bug
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 23 +
target/riscv/vector_helper.c| 66 +
4 files
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 26 +
target/riscv/vector_helper.c| 18 +
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 5
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 22 ++
target/riscv/vector_helper.c| 31 +
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 32 +
target/riscv/vector_helper.c| 19 +++
4
Signed-off-by: LIU Zhiwei
---
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 91 +
2 files changed, 92 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1231628cb2..26dd0f1b1b 100644
---
On Tue, 17 Mar 2020 15:02:14 +1000
Nicholas Piggin wrote:
> Try to be tolerant of errors if the machine check had been recovered
> by the host.
>
> Signed-off-by: Nicholas Piggin
> ---
Same comment as previous patch on multi-line error strings and
warn_report() in the !recovered case.
>
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 9 ++
target/riscv/insn32.decode | 8 +
target/riscv/insn_trans/trans_rvv.inc.c | 28 +
target/riscv/vector_helper.c| 41
From: Yoshinori Sato
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
Signed-off-by: Richard Henderson
[PMD: Squashed patches from Richard Henderson modifying
qapi/common.json and tests/machine-none-test.c]
Message-Id:
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 21
target/riscv/vector_helper.c| 26
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 7 +++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 4
target/riscv/vector_helper.c| 11 +++
4 files changed, 24
From: Richard Henderson
There are so many different forms of each RX instruction
that it will be very useful to be able to look at the bytes
to see on which path a bug may lie.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Tested-by: Philippe Mathieu-Daudé
Signed-off-by:
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 17 ++
target/riscv/vector_helper.c| 77 +
4
From: Yoshinori Sato
Reviewed-by: Richard Henderson
Signed-off-by: Yoshinori Sato
Signed-off-by: Richard Henderson
[PMD: Use newer QOM style, split cpu-qom.h, restrict access to
extable array, use rx_cpu_tlb_fill() extracted from patch of
Yoshinori Sato 'Convert to CPUClass::tlb_fill', call
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 32 +
target/riscv/vector_helper.c| 20
4
On Wed, 4 Mar 2020 12:27:48 -0500
Igor Mammedov wrote:
> Migration from QEMU(v4.0) fails when using 3.1 or older machine
> type. For example if one attempts to migrate
> QEMU-2.12 started as
> qemu-system-ppc64 -nodefaults -M pseries-2.12 -m 4096 -mem-path /tmp/
> to current master, it will
On Thu, 12 Mar 2020 17:13:10 +0100
Janosch Frank wrote:
> On 3/12/20 4:51 PM, Christian Borntraeger wrote:
> > On 11.03.20 14:21, Janosch Frank wrote:
> >> For protected VMs status storing is not done by QEMU anymore.
> >>
> >> Signed-off-by: Janosch Frank
> >> Reviewed-by: Thomas Huth
> >>
From: Richard Henderson
We were eliding all zero indexes. It is only ld==0 that does
not have an index in the instruction. This also allows us to
avoid breaking the final print into multiple pieces.
Reviewed-by: Yoshinori Sato
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard
From: Yoshinori Sato
This part only supported RXv1 instructions.
Instruction manual:
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0032ej0120_rxsm.pdf
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
Signed-off-by:
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 10 +++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvv.inc.c | 5
target/riscv/vector_helper.c| 40 +
4 files
From: Yoshinori Sato
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
Signed-off-by: Richard Henderson
Message-Id: <20200224141923.82118-2-ys...@users.sourceforge.jp>
Acked-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
From: Richard Henderson
Many of the multi-part prints have been eliminated by previous
patches. Eliminate the rest of them.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-Id:
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 3 ++
target/riscv/vector_helper.c| 52 +
4 files changed,
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 11 +++
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 42 +
target/riscv/vector_helper.c| 39
From: Richard Henderson
Note that the ld == 3 case handled by prt_ldmi is decoded as
XCHG_rr and cannot appear here.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-Id:
From: Yoshinori Sato
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
Signed-off-by: Richard Henderson
Message-Id: <20200224141923.82118-8-ys...@users.sourceforge.jp>
Acked-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
From: Richard Henderson
This has consistency with prt_ri(). It loads all data before
beginning output. It uses exactly one call to prt() to emit
the full instruction.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 11 +++
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 42 +
target/riscv/vector_helper.c| 42
From: Richard Henderson
Collected, to be used in the next patch.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-Id: <20190531134315.4109-23-richard.hender...@linaro.org>
Acked-by: Richard Henderson
Queued, including Vladimir's PATCH 4/3. Thanks!
-request'
into staging (2020-03-16 14:55:59 +)
are available in the Git repository at:
https://gitlab.com/philmd/qemu.git tags/target_renesas_rx-20200317
for you to fetch changes up to d9ecf331340137dc091bdcf3d3ef60087deac9ac:
Add rx-softmmu (2020-03-17 16:01:58 +0100
From: Vladimir Sementsov-Ogievskiy
It's wrong to use same err object as errp parameter for several
function calls without intermediate checking for error: we'll crash if
try to set err object twice. Fix that.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Message-Id:
From: Yoshinori Sato
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
Signed-off-by: Richard Henderson
[PMD: Removed tlb_fill, extracted from patch of Yoshinori Sato
'Convert to CPUClass::tlb_fill']
Signed-off-by: Philippe Mathieu-Daudé
From: Yoshinori Sato
Some RX peripheral use 8bit and 16bit registers.
Add the 8bit and 16bit APIs.
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Yoshinori Sato
Signed-off-by: Richard
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 13 ++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvv.inc.c | 6 +
target/riscv/vector_helper.c| 33 +
4
Commit fe44dc9180 "migration: disallow migrate_add_blocker during
migration" accidentally added a second Error * variable. Use the
first one instead.
Signed-off-by: Markus Armbruster
Message-Id: <20200313170517.22480-3-arm...@redhat.com>
Reviewed-by: Peter Maydell
Reviewed-by: Eric Blake
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 4 +++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 34 +
target/riscv/vector_helper.c| 30 ++
4 files changed, 70
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 37 +
target/riscv/insn32.decode | 12 ++
target/riscv/insn_trans/trans_rvv.inc.c | 33 +
target/riscv/vector_helper.c| 182
4 files changed, 264 insertions(+)
201 - 300 of 687 matches
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