Re: [PATCH 08/17] s390x/cpumodel: Fix UI to CPU features pcc-cmac-{aes, eaes}-256

David Hildenbrand writes: > On 30.04.20 20:22, Markus Armbruster wrote: >> David Hildenbrand writes: >> >>> On 28.04.20 18:34, Markus Armbruster wrote: Both s390_features[S390_FEAT_PCC_CMAC_AES_256].name and s390_features[S390_FEAT_PCC_CMAC_EAES_256].name is "pcc-cmac-eaes-256".

Re: [RFC PATCH] qom: Implement qom-get HMP command

Cédric Le Goater writes: > From: "Dr. David Alan Gilbert" > > Reimplement it based on qmp_qom_get() to avoid converting QObjects back > to strings. > > Inspired-by: Paolo Bonzini > Signed-off-by: Andreas Färber > > Slight fix for bit-rot: > Signed-off-by: Dr. David Alan Gilbert > [clg: update

Re: [PATCH 4/4] scripts/qmp: Fix QEMU Python scripts path

John Snow writes: > On 4/30/20 1:04 AM, Markus Armbruster wrote: >> John Snow writes: >> >>> On 4/21/20 5:42 AM, Philippe Mathieu-Daudé wrote: QEMU Python scripts have been moved in commit 8f8fd9edba4 ("Introduce Python module structure"). Use the same sys.path modification used

Re: Configuring onboard devices

Mark Cave-Ayland writes: > On 30/04/2020 16:20, Markus Armbruster wrote: > >>> Ah I see now, these aliases are for individual properties rather than >>> objects. What I >>> was trying to ask was if it were possible to have something like this: >>> >>> /machine (SS-5-machine) >>> /builtin >>>

Re: [PATCH 08/17] s390x/cpumodel: Fix UI to CPU features pcc-cmac-{aes, eaes}-256

Christian Borntraeger writes: > On 29.04.20 10:54, Christian Borntraeger wrote: >> >> >> On 28.04.20 19:13, David Hildenbrand wrote: >>> On 28.04.20 18:34, Markus Armbruster wrote: Both s390_features[S390_FEAT_PCC_CMAC_AES_256].name and s390_features[S390_FEAT_PCC_CMAC_EAES_256].name

Re: [PATCH 17/17] qom: Drop @errp parameter of object_property_del()

Eric Blake writes: > On 4/28/20 11:34 AM, Markus Armbruster wrote: >> Same story as for object_property_add(): the only way >> object_property_del() can fail is when the property with this name >> does not exist. Since our property names are all hardcoded, failure >> is a programming error, and

Re: [PATCH 13/17] qom: Drop parameter @errp of object_property_add() & friends

Eric Blake writes: > On 4/28/20 11:34 AM, Markus Armbruster wrote: >> The only way object_property_add() can fail is when a property with >> the same name already exists. Since our property names are all >> hardcoded, failure is a programming error, and the appropriate way to >> handle it is pas

Re: [PATCH 04/17] qom: Change object_property_get_uint16List() to match its doc

Eric Blake writes: > On 4/28/20 11:34 AM, Markus Armbruster wrote: >> Signed-off-by: Markus Armbruster >> --- >> include/qom/object.h | 4 ++-- >> hw/core/machine-qmp-cmds.c | 6 +++--- >> qom/object.c | 9 + >> 3 files changed, 10 insertions(+), 9 deletions(-) >

Re: [PATCH 02/17] qom: Clean up inconsistent use of gchar * vs. char *

Eric Blake writes: > On 4/28/20 11:34 AM, Markus Armbruster wrote: >> Uses of gchar * in qom/object.h: >> > > Nice audit. I don't know if we can blindly assume that 'gchar' is a > (stupid) typedef to 'char', or if they can ever differ, but avoiding > gchar where possible always makes sense to me

[Bug 1876373] Re: segfault mremap 4096

I've submitted a patch, this is my first qemu patch so sorry if I didn't format it correctly: https://lists.gnu.org/archive/html/qemu- trivial/2020-05/msg0.html -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpa

Re: [PATCH] target/m68k: Allow movec only on 68010+

On Fri, 1 May 2020, Laurent Vivier wrote: Le 01/05/2020 à 15:11, BALATON Zoltan a écrit : Ping? I sent a comment: https://lists.gnu.org/archive/html/qemu-devel/2020-01/msg02840.html Thanks, I've somehow missed that, did not show up in my inbox for some reason. I wasn't sure about the FPU f

Re: [PATCH v2 9/9] block/io: expand in_flight inc/dec section: bdrv_make_zero

On 4/27/20 9:39 AM, Vladimir Sementsov-Ogievskiy wrote: It's safer to expand in_flight request to start before enter to coroutine in synchronous wrappers and end after BDRV_POLL_WHILE loop. Note that qemu_coroutine_enter may only schedule the coroutine in some circumstances. See my wording sugg

Re: [PATCH v2 7/9] block/io: add bdrv_do_pwrite_zeroes

On 4/27/20 9:39 AM, Vladimir Sementsov-Ogievskiy wrote: We'll need a bdrv_co_pwrite_zeroes version without inc/dec in_flight to be used in further implementation of bdrv_make_zero. Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Stefan Hajnoczi --- block/io.c | 23 ++

Re: An first try to improve PPC float simulation, not even compiled. Just ask question.

>From b4d6ca1d6376fab1f1be06eb472e10b908887c2b Mon Sep 17 00:00:00 2001 From: Yonggang Luo Date: Sat, 2 May 2020 05:59:25 +0800 Subject: [PATCH] [ppc fp] Step 1. Rearrange the fp helpers to eliminate helper_reset_fpstatus(). I've mentioned this before, that it's possible to leave the steady-stat

Re: [PATCH v2 6/9] block/io: expand in_flight inc/dec section: block-status

On 4/27/20 9:39 AM, Vladimir Sementsov-Ogievskiy wrote: It's safer to expand in_flight request to start before enter to coroutine in synchronous wrappers and end after BDRV_POLL_WHILE loop. Note that qemu_coroutine_enter may only schedule the coroutine in some circumstances. Wording suggestion:

Re: [PATCH v2 5/9] block/io: expand in_flight inc/dec section: simple cases

On 4/27/20 9:39 AM, Vladimir Sementsov-Ogievskiy wrote: It's safer to expand in_flight request to start before enter to coroutine in synchronous wrappers, due to the following (theoretical) problem: Consider write. It's possible, that qemu_coroutine_enter only schedules execution, assume such ca

Re: [PATCH v2 1/9] block/io: refactor bdrv_is_allocated_above to run only one coroutine

On 4/27/20 9:38 AM, Vladimir Sementsov-Ogievskiy wrote: bdrv_is_allocated_above creates new coroutine on each iteration if called from non-coroutine context. To simplify expansion of in_flight inc/dec sections in further patch let's refactor it. Signed-off-by: Vladimir Sementsov-Ogievskiy ---

[PATCH 6/6] target/arm: Wrap vector compare zero GVecGen2 in GVecGen2Fn

Provide a functional interface for the vector expansion. This fits better with the existing set of helpers that we provide for other operations. Macro-ize the 5 nearly identical comparisons. Signed-off-by: Richard Henderson --- target/arm/translate.h | 16 ++- target/arm/translate-a64.c |

[PATCH 2/6] target/arm: Create gen_gvec_{u,s}{rshr,rsra}

Create vectorized versions of handle_shri_with_rndacc for shift+round and shift+round+accumulate. Add out-of-line helpers in preparation for longer vector lengths from SVE. Signed-off-by: Richard Henderson --- target/arm/helper.h| 20 ++ target/arm/translate.h | 9 + target/arm/t

[PATCH 1/6] target/arm: Create gen_gvec_[us]sra

The functions eliminate duplication of the special cases for this operation. They match up with the GVecGen2iFn typedef. Add out-of-line helpers. We got away with only having inline expanders because the neon vector size is only 16 bytes, and we know that the inline expansion will always succeed

[PATCH 3/6] target/arm: Create gen_gvec_{sri,sli}

The functions eliminate duplication of the special cases for this operation. They match up with the GVecGen2iFn typedef. Add out-of-line helpers. We got away with only having inline expanders because the neon vector size is only 16 bytes, and we know that the inline expansion will always succeed

[PATCH 5/6] target/arm: Tidy handle_vec_simd_shri

Now that we've converted all cases to gvec, there is quite a bit of dead code at the end of the function. Remove it. Sink the call to gen_gvec_fn2i to the end, loading a function pointer within the switch statement. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 56 +

[PATCH 4/6] target/arm: Remove unnecessary range check for VSHL

In 1dc8425e551, while converting to gvec, I added an extra range check against the shift count. This was unnecessary because the encoding of the shift count produces 0 to the element size - 1. Signed-off-by: Richard Henderson --- target/arm/translate.c | 12 ++-- 1 file changed, 2 inser

[PATCH 0/6] target/arm: partial vector cleanup

This is not complete, but shows the direction I'd like to go. It may well help what Peter is doing with the neon decodetree conversion. It may be helpful to apply before the conversion in order to reduce the number of special cases. As may continuing with the cleanup; I'll probably work on that

Re: [PATCH 3/4] softfloat: fix floatx80 pseudo-denormal comparisons

On Fri, 1 May 2020, Alex Bennée wrote: > OK - so these only turn up in i386? Patch 1, silencing sNaN, is about generic semantics of IEEE floating-point conversions (which are implemented correctly in various other cases in QEMU), and would be equally applicable to m68k (I believe, without havin

Re: An first try to improve PPC float simulation, not even compiled. Just ask question.

On 5/1/20 1:04 PM, 罗勇刚(Yonggang Luo) wrote: > And  fp_status can not represent all the  Invalid Operation Exception flags. > What I need to do to represent all the  Invalid Operation Exception Ideally, we add them to include/fpu/softfloat-types.h, expand the float_exception_flags field in float_st

Re: About hardfloat in ppc

On 5/1/20 10:49 AM, 罗勇刚(Yonggang Luo) wrote: > > > On Sat, May 2, 2020 at 12:51 AM Richard Henderson > > wrote: > > On 5/1/20 9:29 AM, 罗勇刚(Yonggang Luo) wrote: > > On Fri, May 1, 2020 at 10:18 PM Richard Henderson > mailto:richard.hender...@lina

[Bug 1876373] Re: segfault mremap 4096

Thanks to @LemonBoy for finding this: It looks like this issue my be caused by this chunk of code in linux- user/mmap.c if (prot == 0) { host_addr = mremap(g2h(old_addr), old_size, new_size, flags); if (host_addr != MAP_FAILED && reserved_va && old_size > new_size)

[Bug 1876373] [NEW] segfault mremap 4096

Public bug reported: a qemu-hosted process segfaults when the program calls mremap to shrink the size of a buffer to 4096 that was allocated with mmap. See below for a C program to reproduce this issue. I was able to compile this program for both i386 and 32-bit arm, and use qemu-i386 and qemu-ar

An first try to improve PPC float simulation, not even compiled. Just ask question.

/* +---++--+ | Bits | Name | Description | +---++--

Re: About hardfloat in ppc

罗勇刚(Yonggang Luo) writes: > On Fri, May 1, 2020 at 10:18 PM Richard Henderson < > richard.hender...@linaro.org> wrote: > >> On 5/1/20 6:10 AM, Alex Bennée wrote: >> > >> > 罗勇刚(Yonggang Luo) writes: >> > >> >> On Fri, May 1, 2020 at 7:58 PM BALATON Zoltan >> wrote: >> >> >> >>> On Fri, 1 May 2

Re: [PATCH 3/4] softfloat: fix floatx80 pseudo-denormal comparisons

Joseph Myers writes: > On Fri, 1 May 2020, Alex Bennée wrote: > >> >> Joseph Myers writes: >> >> > The softfloat floatx80 comparisons fail to allow for pseudo-denormals, >> > which should compare equal to corresponding values with biased >> > exponent 1 rather than 0. Add an adjustment for

Re: [PULL 0/6] virtiofs queue

lable in the Git repository at: > > https://gitlab.com/dagrh/qemu.git tags/pull-virtiofs-20200501 > > for you to fetch changes up to 66502bbca37ca7a3bfa57e82cfc03b89a7a11eae: > > virtiofsd: drop all capabil

[PULL 5/6] virtiofsd: only retain file system capabilities

From: Stefan Hajnoczi virtiofsd runs as root but only needs a subset of root's Linux capabilities(7). As a file server its purpose is to create and access files on behalf of a client. It needs to be able to access files with arbitrary uid/gid owners. It also needs to be create device nodes. I

[PULL 6/6] virtiofsd: drop all capabilities in the wait parent process

From: Stefan Hajnoczi All this process does is wait for its child. No capabilities are needed. Signed-off-by: Stefan Hajnoczi Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Dr. David Alan Gilbert --- tools/virtiofsd/passthrough_ll.c | 13 + 1 file changed, 13 insertions(+)

[PULL 2/6] virtiofsd: stay below fs.file-max sysctl value (CVE-2020-10717)

From: Stefan Hajnoczi The system-wide fs.file-max sysctl value determines how many files can be open. It defaults to a value calculated based on the machine's RAM size. Previously virtiofsd would try to set RLIMIT_NOFILE to 1,000,000 and this allowed the FUSE client to exhaust the number of ope

[PULL 3/6] virtiofsd: jail lo->proc_self_fd

From: Miklos Szeredi While it's not possible to escape the proc filesystem through lo->proc_self_fd, it is possible to escape to the root of the proc filesystem itself through "../..". Use a temporary mount for opening lo->proc_self_fd, that has it's root at /proc/self/fd/, preventing access to

[PULL 0/6] virtiofs queue

b.com/dagrh/qemu.git tags/pull-virtiofs-20200501 for you to fetch changes up to 66502bbca37ca7a3bfa57e82cfc03b89a7a11eae: virtiofsd: drop all capabilities in the wait parent process (2020-05-01 20:05:37 +0100) virtiofsd: Pull 2020

[PULL 4/6] virtiofsd: Show submounts

From: Max Reitz Currently, setup_mounts() bind-mounts the shared directory without MS_REC. This makes all submounts disappear. Pass MS_REC so that the guest can see submounts again. Fixes: 5baa3b8e95064c2434bd9e2f312edd5e9ae275dc Signed-off-by: Max Reitz Message-Id: <20200424133516.73077-1-mr

Re: [PATCH] target/riscv: fix check of guest pa top bits

Yeah, I've run into the same issue. Even if you ask Gmail to treat the email as plain text it still takes the liberty of hard wrapping lines without asking you. It really is a shame that there isn't a good way to submit patches via a web UI, the art of git send-email + manual SMTP isn't as widespre

[PULL 1/6] virtiofsd: add --rlimit-nofile=NUM option

From: Stefan Hajnoczi Make it possible to specify the RLIMIT_NOFILE on the command-line. Users running multiple virtiofsd processes should allocate a certain number to each process so that the system-wide limit can never be exhausted. When this option is set to 0 the rlimit is left at its curren

Re: [PATCH 3/4] softfloat: fix floatx80 pseudo-denormal comparisons

On Fri, 1 May 2020, Alex Bennée wrote: > > Joseph Myers writes: > > > The softfloat floatx80 comparisons fail to allow for pseudo-denormals, > > which should compare equal to corresponding values with biased > > exponent 1 rather than 0. Add an adjustment for that case when > > comparing numbe

[PATCH 0/1] target-ppc: fix rlwimi, rlwinm, rlwnm for Clang-9

Until Clang v8, -Wtype-limits was kept for GCC compatibility but had no effect. With Clang v9, the flag is now implemented ( see https://tinyurl.com/clang8-manual vs https://tinyurl.com/clang9-manual ) Starting with Clang v9, compiling with -Wtype-limits (default for QEMU) triggers the following

[PATCH 1/1] target-ppc: fix rlwimi, rlwinm, rlwnm for Clang-9

Starting with Clang v9, -Wtype-limits is implemented and triggers a few "result of comparison is always true" errors when compiling PPC32 targets. The comparisons seem to be necessary only on PPC64, since the else branch in PPC32 only has a "g_assert_not_reached();" in all cases. This patch restr

Re: [PATCH 3/4] softfloat: fix floatx80 pseudo-denormal comparisons

Joseph Myers writes: > The softfloat floatx80 comparisons fail to allow for pseudo-denormals, > which should compare equal to corresponding values with biased > exponent 1 rather than 0. Add an adjustment for that case when > comparing numbers with the same sign. > > Note that this fix only ch

Re: [PATCH 2/4] softfloat: fix floatx80 pseudo-denormal addition / subtraction

On Fri, 1 May 2020, Alex Bennée wrote: > > Joseph Myers writes: > > > The softfloat function addFloatx80Sigs, used for addition of values > > with the same sign and subtraction of values with opposite sign, fails > > to handle the case where the two values both have biased exponent zero > > and

Re: [PATCH 2/4] softfloat: fix floatx80 pseudo-denormal addition / subtraction

Joseph Myers writes: > The softfloat function addFloatx80Sigs, used for addition of values > with the same sign and subtraction of values with opposite sign, fails > to handle the case where the two values both have biased exponent zero > and there is a carry resulting from adding the significa

Re: [PATCH 1/1] target/riscv: fix VS interrupts forwarding to HS

Reached out to Andrew Waterman. This was his response: "I think the encoding of the privileged modes is a red herring. HS is inherently more privileged than VS, since it controls memory protection and interrupt delegation for VS. Certainly the intent is that HS-mode interrupts are always enabled

Re: [PATCH] target/riscv: fix check of guest pa top bits

Just resubmitted version 2. Sorry. Not really used to this. I actually wasn't using git send-email. I was copying the patch to my email client which was causing the weird wrapping. I think I also fixed the issues raised by checkpatch. Hope everything is correct now. Jose On Thu, 30 Apr 2020 at 22

[PATCH v2] target/riscv: fix check of guest pa top bits

The spec states that on sv39x4 guest physical "address bits 63:41 must all be zeros, or else a guest-page-fault exception occurs.". However, the check performed for these top bits of the virtual address on the second stage is the same as the one performed for virtual addresses on the first stage

Re: [PATCH] qcow2: Avoid integer wraparound in qcow2_co_truncate()

On 5/1/20 12:12 PM, Eric Blake wrote: On 5/1/20 8:15 AM, Alberto Garcia wrote: After commit f01643fb8b47e8a70c04bbf45e0f12a9e5bc54de when an image is extended and BDRV_REQ_ZERO_WRITE is set then the new clusters are zeroized. The code however does not detect correctly situations when the old an

Re: [PATCH 0/2] virtiofsd: drop Linux capabilities(7)

* Stefan Hajnoczi (stefa...@redhat.com) wrote: > virtiofsd doesn't need of all Linux capabilities(7) available to root. Keep a > whitelisted set of capabilities that we require. This improves security in > case virtiofsd is compromised by making it hard for an attacker to gain > further > access

[PATCH] virtiofsd: Use clone() and not unshare(), support non-root

I'd like to make use of virtiofs as part of our tooling in https://github.com/coreos/coreos-assembler Most of the code runs as non-root today; qemu also runs as non-root. We use 9p right now. virtiofsd's builtin sandboxing effectively assumes it runs as root. First, change the code to use `clone(

Re: [PATCH 26/36] target/arm: Convert Neon VQSHL, VRSHL, VQRSHL 3-reg-same insns to decodetree

On Fri, 1 May 2020 at 02:55, Richard Henderson wrote: > I'm not 100% sure how best to handle the swapped operands issue. I don't > think > we want to do it here in gen_gvec_srshl, because we don't have the same > reverse > operand problem in the aarch64 encoding, and I'm looking forward to re-u

Re: [PATCH] virtiofsd: Show submounts

* Max Reitz (mre...@redhat.com) wrote: > Currently, setup_mounts() bind-mounts the shared directory without > MS_REC. This makes all submounts disappear. > > Pass MS_REC so that the guest can see submounts again. > > Fixes: 3ca8a2b1c83eb185c232a4e87abbb65495263756 > Signed-off-by: Max Reitz Qu

Re: About hardfloat in ppc

On Sat, May 2, 2020 at 12:51 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 5/1/20 9:29 AM, 罗勇刚(Yonggang Luo) wrote: > > On Fri, May 1, 2020 at 10:18 PM Richard Henderson < > richard.hender...@linaro.org > > Step 1 is to rearrange the fp helpers to eliminate > helper_reset_fp

Re: [PATCH] virtiofsd: jail lo->proc_self_fd

* Miklos Szeredi (mszer...@redhat.com) wrote: > While it's not possible to escape the proc filesystem through > lo->proc_self_fd, it is possible to escape to the root of the proc > filesystem itself through "../..". > > Use a temporary mount for opening lo->proc_self_fd, that has it's root at > /p

Re: [PATCH] chardev: enable distinct input for -chardev file

Patchew URL: https://patchew.org/QEMU/20200501172559.6470-1-alx...@bu.edu/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN === #!/bin

Re: [PATCH v2 0/2] virtiofsd: stay under fs.file-max sysctl limit (CVE-2020-10717)

* Stefan Hajnoczi (stefa...@redhat.com) wrote: > This patch series introduces the --rlimit-nofile=NUM option for setting the > number of open files on the virtiofsd process. This gives users and > management > tools more control over resource limits. > > Previously it was possible for FUSE clien

Re: [PATCH] chardev: enable distinct input for -chardev file

Hi On Fri, May 1, 2020 at 7:26 PM Alexander Bulekov wrote: > > char-file already supports distinct paths for input/output but it was > only possible to specify a distinct input through QMP. With this change, > we can also specify a distinct input with the -chardev file argument: > qemu -chard

[PATCH] chardev: enable distinct input for -chardev file

char-file already supports distinct paths for input/output but it was only possible to specify a distinct input through QMP. With this change, we can also specify a distinct input with the -chardev file argument: qemu -chardev file,id=char1,path=/out/file,in=/in/file Signed-off-by: Alexander B

Re: [PATCH] qcow2: Avoid integer wraparound in qcow2_co_truncate()

On 5/1/20 8:15 AM, Alberto Garcia wrote: After commit f01643fb8b47e8a70c04bbf45e0f12a9e5bc54de when an image is extended and BDRV_REQ_ZERO_WRITE is set then the new clusters are zeroized. The code however does not detect correctly situations when the old and the new end of the image are within t

Re: [PATCH 1/4] softfloat: silence sNaN for conversions to/from floatx80

On Fri, 1 May 2020, Alex Bennée wrote: > I still see some failures for: > > f64_to_extF80 > f128_to_extF80 Running what I think are those tests, I see e.g. ./fp-test -s -l 1 -r all f64_to_extF80 >> Testing f64_to_extF80 768 tests total. Errors found in f64_to_extF80: -368.800FF

Re: [PATCH 1/4] softfloat: silence sNaN for conversions to/from floatx80

On 5/1/20 9:17 AM, Alex Bennée wrote: > Ideally we want to > convert the extF80 and f128 code to use the newer FloatParts code which > is pretty robustly tested now. However the trick would be finding a way > to do that that doesn't involve break or regressing the performance for > the f16/32/64 ca

Re: [PATCH 02/36] target/arm: Don't allow Thumb Neon insns without FEATURE_NEON

On 4/30/20 8:09 PM, Peter Maydell wrote: We were accidentally permitting decode of Thumb Neon insns even if the CPU didn't have the FEATURE_NEON bit set, because the feature check was being done before the call to disas_neon_data_insn() and disas_neon_ls_insn() in the Arm decoder but was omitted

Re: [PATCH 01/36] target/arm/translate-vfp.inc.c: Remove duplicate simd_r32 check

On 4/30/20 8:09 PM, Peter Maydell wrote: Somewhere along theline we accidentally added a duplicate "the line"? "using D16-D31 when they don't exist" check to do_vfm_dp() (probably an artifact of a patchseries rebase). Remove it. Signed-off-by: Peter Maydell --- target/arm/translate-vfp.

Re: About hardfloat in ppc

On 5/1/20 9:29 AM, 罗勇刚(Yonggang Luo) wrote: > On Fri, May 1, 2020 at 10:18 PM Richard Henderson > Step 1 is to rearrange the fp helpers to eliminate > helper_reset_fpstatus(). > I've mentioned this before, that it's possible to leave the steady-state > of > env->fp_status.exception_

Re: [PATCH v7 0/7] reference implementation of RSS and hash report

On Sun, Mar 29, 2020 at 06:09:46PM +0300, Yuri Benditovich wrote: > Support for VIRTIO_NET_F_RSS and VIRTIO_NET_F_HASH_REPORT > features in QEMU for reference purpose. > Implements Toeplitz hash calculation for incoming > packets according to configuration provided by driver. > Uses calculated hash

Re: [PATCH v7 0/7] reference implementation of RSS and hash report

OK so now 5.0's out, I think it's easier if you just send v8, but it's up to Jason. On Fri, May 01, 2020 at 10:44:06AM -0400, Michael S. Tsirkin wrote: > We are in freeze so nothing's applied right now. > v8 which has all the bits will be a good step so we > are ready for after freeze. > > On Fr

Re: About hardfloat in ppc

On Fri, May 1, 2020 at 10:18 PM Richard Henderson < richard.hender...@linaro.org> wrote: > On 5/1/20 6:10 AM, Alex Bennée wrote: > > > > 罗勇刚(Yonggang Luo) writes: > > > >> On Fri, May 1, 2020 at 7:58 PM BALATON Zoltan > wrote: > >> > >>> On Fri, 1 May 2020, 罗勇刚(Yonggang Luo) wrote: > That's

Re: About hardfloat in ppc

On Fri, May 1, 2020 at 10:18 PM Richard Henderson < richard.hender...@linaro.org> wrote: > On 5/1/20 6:10 AM, Alex Bennée wrote: > > > > 罗勇刚(Yonggang Luo) writes: > > > >> On Fri, May 1, 2020 at 7:58 PM BALATON Zoltan > wrote: > >> > >>> On Fri, 1 May 2020, 罗勇刚(Yonggang Luo) wrote: > That's

Re: [PATCH 1/4] softfloat: silence sNaN for conversions to/from floatx80

Joseph Myers writes: > Conversions between IEEE floating-point formats should convert > signaling NaNs to quiet NaNs. Most of those in QEMU's softfloat code > do so, but those for floatx80 fail to. Fix those conversions to > silence signaling NaNs as well. I realised we hadn't enabled float-

Re: [PATCH 23/36] target/arm: Convert Neon 64-bit element 3-reg-same insns

On 5/1/20 8:57 AM, Peter Maydell wrote: > On Fri, 1 May 2020 at 16:50, Richard Henderson > wrote: >> The original intention of the hook is to expand some inline tcg ops. That it >> can be used to call a helper is a happy accident. For a helper that needs >> env, >> ideally we would use tcg_gen_

Re: [PATCH 23/36] target/arm: Convert Neon 64-bit element 3-reg-same insns

On 5/1/20 8:54 AM, Peter Maydell wrote: > On Thu, 30 Apr 2020 at 21:54, Richard Henderson > wrote: >> >> On 4/30/20 11:09 AM, Peter Maydell wrote: >>> + >>> +rn = tcg_temp_new_i64(); >>> +rm = tcg_temp_new_i64(); >>> +rd = tcg_temp_new_i64(); >>> + >>> +for (pass = 0; pass < (a->q

Re: [PATCH 23/36] target/arm: Convert Neon 64-bit element 3-reg-same insns

On Fri, 1 May 2020 at 16:50, Richard Henderson wrote: > The original intention of the hook is to expand some inline tcg ops. That it > can be used to call a helper is a happy accident. For a helper that needs > env, > ideally we would use tcg_gen_gvec_ptr and handle the vector with one call. T

Re: [PATCH 23/36] target/arm: Convert Neon 64-bit element 3-reg-same insns

On Thu, 30 Apr 2020 at 21:54, Richard Henderson wrote: > > On 4/30/20 11:09 AM, Peter Maydell wrote: > > + > > +rn = tcg_temp_new_i64(); > > +rm = tcg_temp_new_i64(); > > +rd = tcg_temp_new_i64(); > > + > > +for (pass = 0; pass < (a->q ? 2 : 1); pass++) { > > +neon_load_reg

[PATCH 3/5] riscv: Use pre-built bios image of generic platform for virt & sifive_u

From: Bin Meng Update virt and sifive_u machines to use the opensbi bios image built for the generic FDT platform. Remove the out-of-date no longer used bios images. Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 4 ++-- hw/riscv/virt.c

[PATCH 2/5] gitlab-ci/opensbi: Update GitLab CI to build generic platform

From: Bin Meng This updates the GitLab CI opensbi job to build opensbi bios images for the generic platform. Signed-off-by: Bin Meng --- .gitlab-ci-opensbi.yml | 26 -- 1 file changed, 8 insertions(+), 18 deletions(-) diff --git a/.gitlab-ci-opensbi.yml b/.gitlab-ci-o

[PATCH 1/5] roms/opensbi: Update to support building bios images for generic platform

From: Bin Meng The RISC-V generic platform is a flattened device tree (FDT) based platform where all platform specific functionality is provided based on FDT passed by previous booting stage. The support was added in upstream opensbi recently. Bring the QEMU roms/opensbi submodule to the upstrea

[PATCH 5/5] riscv: Suppress the error report for QEMU testing with riscv_find_firmware()

From: Bin Meng We only ship plain binary bios images in the QEMU source. With Spike machine that uses ELF images as the default bios, running QEMU test will complain hence let's suppress the error report for QEMU testing. Signed-off-by: Bin Meng --- hw/riscv/boot.c | 14 +++--- 1 fil

[PATCH 4/5] riscv/spike: Change the default bios to use generic platform image

From: Bin Meng To keep sync with other RISC-V machines, change the default bios to use generic platform image. While we are here, add some comments to mention that keeping ELF files here was intentional. Signed-off-by: Bin Meng --- hw/riscv/spike.c | 9 +++-- 1 file changed, 7 insertions

[PATCH 0/5] riscv: Switch to use generic platform of opensbi bios images

From: Bin Meng The RISC-V generic platform is a flattened device tree (FDT) based platform where all platform specific functionality is provided based on FDT passed by previous booting stage. The support was added in upstream opensbi recently. This series updates QEMU to switch to use generic p

Re: [PATCH 23/36] target/arm: Convert Neon 64-bit element 3-reg-same insns

On 5/1/20 8:36 AM, Peter Maydell wrote: > On Thu, 30 Apr 2020 at 21:54, Richard Henderson > wrote: >> You can morph this into the gvec interface like so: >> >> #define DO_3SAME_64(INSN, FUNC) \ >> static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, >> ui

Re: [PATCH 1/4] softfloat: silence sNaN for conversions to/from floatx80

Joseph Myers writes: > Conversions between IEEE floating-point formats should convert > signaling NaNs to quiet NaNs. Most of those in QEMU's softfloat code > do so, but those for floatx80 fail to. Fix those conversions to > silence signaling NaNs as well. > > Signed-off-by: Joseph Myers Th

Re: [PATCH 1/1] Fix win32 keycode for VK_OEM_102

On Wed, Apr 29, 2020 at 08:42:50PM +0200, Volker Rümelin wrote: > The win32 keycode for VK_OEM_102 is 0xe2. The Microsoft docu- > mentation for virtual-key codes agrees with mingw32/winuser.h. Yes, I concur. I must have made a typo when entering this. > > Signed-off-by: Volker Rümelin > --- >

Re: [PATCH 23/36] target/arm: Convert Neon 64-bit element 3-reg-same insns

On Thu, 30 Apr 2020 at 21:54, Richard Henderson wrote: > You can morph this into the gvec interface like so: > > #define DO_3SAME_64(INSN, FUNC) \ > static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, > uint32_t rn_ofs, uint32_t rm_ofs, >

Re: [PATCH v1 5/7] disas: include an optional note for the start of disassembly

On 5/1/20 4:57 PM, Alex Bennée wrote: This will become useful shortly for providing more information about output assembly inline. While there fix up the indenting and code formatting in disas(). Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- include/disas/disas.h

Re: RFC: use VFIO over a UNIX domain socket to implement device offloading

On Fri, May 01, 2020 at 03:01:01PM +, Felipe Franciosi wrote: > Hi, > > > On Apr 30, 2020, at 4:20 PM, Thanos Makatos > > wrote: > > > More importantly, considering: > a) Marc-André's comments about data alignment etc., and > b) the possibility to run the server on another gu

Re: [PATCH] aspeed: Add support for the sonorapass-bmc board

Patchew URL: https://patchew.org/QEMU/20200501113704.2240698-1-patr...@stwcx.xyz/ Hi, This series seems to have some coding style problems. See output below for more information: Message-id: 20200501113704.2240698-1-patr...@stwcx.xyz Subject: [PATCH] aspeed: Add support for the sonorapass-bmc

Re: [PULL 0/4] Block patches

On Fri, May 01, 2020 at 10:32:02AM +0100, Peter Maydell wrote: > On Fri, 1 May 2020 at 09:28, Stefan Hajnoczi wrote: > > > > The following changes since commit 27c94566379069fb8930bb1433dcffbf7df3203d: > > > > Merge remote-tracking branch > > 'remotes/edgar/tags/edgar/xilinx-next-2020-04-30.for

Re: [PATCH] linux-user/strace.list: fix epoll_create{,1} -strace output

+ Helge & Aleksandar. On 5/1/20 12:59 AM, Sergei Trofimovich wrote: On Thu, 16 Apr 2020 18:59:57 +0100 Sergei Trofimovich wrote: Fix syscall name and parameters priinter. Before the change: ``` $ alpha-linux-user/qemu-alpha -strace -L /usr/alpha-unknown-linux-gnu/ /tmp/a ... 1274697 %s(%d)

Re: RFC: use VFIO over a UNIX domain socket to implement device offloading

Hi, > On Apr 30, 2020, at 4:20 PM, Thanos Makatos > wrote: > More importantly, considering: a) Marc-André's comments about data alignment etc., and b) the possibility to run the server on another guest or host, we won't be able to use native VFIO types. If we do want to supp

Re: [PATCH v1 2/4] .travis.yml: drop MacOSX

Daniel P. Berrangé writes: > On Fri, May 01, 2020 at 12:15:03PM +0100, Alex Bennée wrote: >> This keeps breaking on Travis so lets just fall back to the Cirrus CI >> builds which seem to be better maintained. Fix up the comments while >> we are doing this as we never had a windows build. > > FY

Re: [PATCH v1 7/9] tests/guest-debug: use the unix socket for linux-user tests

Richard Henderson writes: > On 4/30/20 12:01 PM, Alex Bennée wrote: >> +if "system" in args.qemu: >> +gdb_cmd += " -ex 'target remote localhost:1234'" >> +else: >> +gdb_cmd += " -ex 'target remote %s'" % (socket_name) > > Why should not system testing be moved to sockets

[PATCH v1 6/7] disas: add optional note support to cap_disas

Include support for outputting a note at the top of a chunk of disassembly to capstone as well. Signed-off-by: Alex Bennée --- disas.c | 20 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/disas.c b/disas.c index bb74650633..5e7eb65326 100644 --- a/disas.c +++

[PATCH v1 7/7] translate-all: include guest address in out_asm output

We already have information about where each guest instructions representation starts stored in the tcg_ctx->gen_insn_data so we can rectify the PC for faults. We can re-use this information to annotate the out_asm output with guest instruction address which makes it a bit easier to work out where

[PATCH v1 1/7] linux-user: completely re-write init_guest_space

First we ensure all guest space initialisation logic comes through probe_guest_base once we understand the nature of the binary we are loading. The convoluted init_guest_space routine is removed and replaced with a number of pgb_* helpers which are called depending on what requirements we have when

[PATCH v1 4/7] accel/tcg: don't disable exec_tb trace events

I doubt the well predicted trace event check is particularly special in the grand context of TCG code execution. Signed-off-by: Alex Bennée --- accel/tcg/trace-events | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/accel/tcg/trace-events b/accel/tcg/trace-events index

[PATCH v1 3/7] accel/tcg: Relax va restrictions on 64-bit guests

From: Richard Henderson We cannot at present limit a 64-bit guest to a virtual address space smaller than the host. It will mostly work to ignore this limitation, except if the guest uses high bits of the address space for tags. But it will certainly work better, as presently we can wind up fai

[PATCH v1 5/7] disas: include an optional note for the start of disassembly

This will become useful shortly for providing more information about output assembly inline. While there fix up the indenting and code formatting in disas(). Signed-off-by: Alex Bennée --- include/disas/disas.h | 2 +- include/exec/log.h| 4 ++-- accel/tcg/translate-all.c | 4 ++--

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