On 6/4/20 4:01 AM, Kevin Wolf wrote:
Am 14.05.2020 um 05:49 hat John Snow geschrieben:
This job copies the allocation map into a bitmap. It's a job because
there's no guarantee that allocation interrogation will be quick (or
won't hang), so it cannot be retrofit into block-dirty-bitmap-merge.
I
On 4/30/20 12:14 PM, Stephen Long wrote:
> Signed-off-by: Stephen Long
> ---
>
> I made the changes Richard requested. I took out the status field for
> the helper function.
>
> include/fpu/softfloat.h| 5 +++
> target/arm/helper-sve.h| 4 +++
> target/arm/sve.decode | 4 +++
>
Currently, all riscv machines have identical reset vector code
implementations with memory addresses being different for all machines.
They can be easily combined into a single function in common code.
Move it to common function and let all the machines use the common function.
Signed-off-by: Ati
This series adds support OpenSBI dynamic firmware support to Qemu.
Qemu loader passes the information about the DT and next stage (i.e. kernel
or U-boot) via "a2" register. It allows the user to build bigger OS images
without worrying about overwriting DT. It also unifies the reset vector code
in r
Currently, the fdt is copied to the ROM after the reset vector. The firmware
has to copy it to DRAM. Instead of this, directly copy the device tree to a
pre-computed dram address. The device tree load address should be as far as
possible from kernel and initrd images. That's why it is kept at the e
OpenSBI is the default firmware in Qemu and has various firmware loading
options. Currently, qemu loader uses fw_jump which has a compile time
pre-defined address where fdt & kernel image must reside. This puts a
constraint on image size of the Linux kernel depending on the fdt location
and availab
> > increment the revision to '2' so that these larger addresses are
> > addressable. This matters because the DSDT revision represents the
> > maximum capability of all other SSDTs. This is also what arm does.
> it was keept at 1 for compat reasons with WindowsXP.
> by now it is long time EOL, so
On 4/30/20 6:28 AM, Stephen Long wrote:
> Implements FCVTLT, FCVTX, FCVTNT, FCVTXNT
>
> Signed-off-by: Stephen Long
> ---
>
> Fixed a compilation error and collapsed the translation functions with a
> macro.
>
>> Ignore my previous patchset. I missed the insn FCVTX and I ended up
>> squashing t
Hi, this is a followup to my patch which attempted to prefer
'sphinx-build' to 'sphinx-build-3' which intended to prefer a VENV
installation of sphinx over Fedora's system installation.
That got confusing, though, so here's something that's simpler and
better: use python to invoke sphinx so we don
Using an explicit entry path script for sphinx can lead to confusing
results: If the python binary belongs to a virtual environment, our
configure script may still select a sphinx script that belongs to the
system distribution packages.
It is likely best to use python itself (whichever one the use
On 4/28/20 10:43 AM, Stephen Long wrote:
> The only insn left in this category is BFCVTNT. I couldn't find any
> helper functions for bfloats so I'm not sure how to approach this insn.
>
> Also, for insn FCVTXNT, I'm not sure if it is ok to set the status rounding
> mode to odd like that.
>
> Ste
On 4/28/20 10:43 AM, Stephen Long wrote:
> +void HELPER(sve2_fcvtxnt)(void *vd, void *vn, void *vg,
> + void *status, uint32_t desc)
> +{
> +set_float_rounding_mode(float_round_to_odd, status);
> +HELPER(sve2_fcvtnt_ds)(vd, vn, vg, status, desc);
> +}
This is incor
On Tue, Jun 16, 2020 at 2:16 AM Igor Mammedov wrote:
> On Mon, 15 Jun 2020 18:36:54 -0600
> "Jason A. Donenfeld" wrote:
> > SSDTs cannot address 64-bit physical addresses in 32-bit tables, so we
> please clarify what accesses waht within tables (i.e. be more concrete).
If you add an ssdt or a cu
Patchew URL:
https://patchew.org/QEMU/CA+XhMqx6VjRhT6xBzJ-UYs7cPDXVK=PNdfNVdad3Tqhe43P=e...@mail.gmail.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH V4] util/oslib-posix : qemu_init_exec_dir implementation for Mac
Type: s
>From 3025a0ce3fdf7d3559fc35a52c659f635f5c750c Mon Sep 17 00:00:00 2001
From: David Carlier
Date: Tue, 26 May 2020 21:35:27 +0100
Subject: [PATCH] util/oslib-posix : qemu_init_exec_dir implementation for Mac
Using dyld API to get the full path of the current process.
Signed-off-by: David Carlier
On Tue, 16 Jun 2020 at 17:12, David CARLIER wrote:
>
> From 7eef8b803cdb0e7148fdf894d2992052695c1ff8 Mon Sep 17 00:00:00 2001
> From: David Carlier
> Date: Tue, 26 May 2020 21:35:27 +0100
> Subject: [PATCH] util/oslib-posix : qemu_init_exec_dir implementation for Mac
>
> Using dyld API to get the
On 4/27/20 2:40 PM, Stephen Long wrote:
> Modified some of the crypto functions in crypto_helper.c to take in a
> desc parameter.
>
> Didn't add a desc parameter to SM4E and SM4EKEY since it is used in
> translate-a64.c and the functions in there need crypto_sm4e and
> crypto_sm4ekey to stay the s
On 4/28/20 7:43 AM, Stephen Long wrote:
> Signed-off-by: Stephen Long
> ---
> target/arm/helper-sve.h| 10 ++
> target/arm/internals.h | 12 +++
> target/arm/sve.decode | 5 +++
> target/arm/sve_helper.c| 71 ++
> target/arm/translate-
On Mon, Jun 15, 2020 at 8:24 PM Anup Patel wrote:
>
> We extend RISC-V virt machine to allow creating a multi-socket
> machine. Each RISC-V virt machine socket is a NUMA node having
> a set of HARTs, a memory instance, a CLINT instance, and a PLIC
> instance. Other devices are shared between all s
On 6/16/20 7:15 PM, Cédric Le Goater wrote:
> After a closer look,
>
>>> @@ -45,9 +46,15 @@ static void pca9552_update_pin_input(PCA9552State *s)
>>> switch (config) {
>>> case PCA9552_LED_ON:
>>> s->regs[input_reg] |= 1 << input_shift;
>>> +if (input_shi
On 6/16/20 7:52 PM, Alex Bennée wrote:
>
> Claudio Fontana writes:
>
>> Hi Alex,
>>
>> thanks for looking at this,
>>
>> On 6/16/20 4:16 PM, Alex Bennée wrote:
>>>
>>> Claudio Fontana writes:
>>>
each accelerator registers a new "CpusAccel" interface
implementation on initialization,
On Mon, Jun 15, 2020 at 8:23 PM Anup Patel wrote:
>
> We extend RISC-V spike machine to allow creating a multi-socket
> machine. Each RISC-V spike machine socket is a NUMA node having
> a set of HARTs, a memory instance, and a CLINT instance. Other
> devices are shared between all sockets. We also
On 6/9/20 4:58 AM, Markus Armbruster wrote:
> Philippe Mathieu-Daudé writes:
>
>> On 6/8/20 5:33 PM, Kevin Wolf wrote:
>>> Am 08.06.2020 um 17:19 hat John Snow geschrieben:
On 6/5/20 5:26 AM, Kevin Wolf wrote:
> Am 04.06.2020 um 22:22 hat John Snow geschrieben:
>> Based-
Claudio Fontana writes:
> Hi Alex,
>
> thanks for looking at this,
>
> On 6/16/20 4:16 PM, Alex Bennée wrote:
>>
>> Claudio Fontana writes:
>>
>>> each accelerator registers a new "CpusAccel" interface
>>> implementation on initialization, providing functions for
>>> starting a vcpu, kicking
On Mon, Jun 15, 2020 at 8:25 PM Anup Patel wrote:
>
> We add common helper routines which can be shared by RISC-V
> multi-socket NUMA machines.
>
> We have two types of helpers:
> 1. riscv_socket_xyz() - These helper assist managing multiple
>sockets irrespective whether QEMU NUMA is enabled/d
On Tue, Jun 16, 2020 at 6:32 PM Kevin Wolf wrote:
>
> Am 15.06.2020 um 21:32 hat Nir Soffer geschrieben:
> > We can zero 2.3 g/s:
> >
> > # time blkdiscard -z test-lv
> >
> > real 0m43.902s
> > user 0m0.002s
> > sys 0m0.130s
>
> > We can write 445m/s:
> >
> > # dd if=/dev/zero bs=2M count=51200 of
Bastian Koppelmann writes:
> Hi Alex,
>
> I managed to update the series to successfully run make check-tcg. This
> required
> some changes to the makefiles. I tried running the riscv64 and arm tests and
> so
> far I didn't break anything.
You can have a:
Tested-by: Alex Bennée
for patche
> -Original Message-
> From: Igor Mammedov
> Sent: Tuesday, June 16, 2020 5:59 AM
> To: Moger, Babu
> Cc: pbonz...@redhat.com; r...@twiddle.net; ehabk...@redhat.com;
> m...@redhat.com; marcel.apfelb...@gmail.com; qemu-devel@nongnu.org
> Subject: Re: [PATCH 1/2] hw/386: Fix uninitialize
After a closer look,
>> @@ -45,9 +46,15 @@ static void pca9552_update_pin_input(PCA9552State *s)
>> switch (config) {
>> case PCA9552_LED_ON:
>> s->regs[input_reg] |= 1 << input_shift;
>> +if (input_shift < s->nr_leds) {
This seems like a superfluous test
Thanks Gerd, Dave and Eduardo for the prompt responses!
So, I understand that when we use "-host-physical-bits", we are
passing the *real* number for the guest, correct? So, in this case we
can trust that the guest physbits matches the true host physbits.
What if then we have OVMF relying in the
Bastian Koppelmann writes:
> This kind of tests is inspired by the riscv-tests repository. This adds
> macros that makes it easy to create single instruction self containing
> tests.
>
> It is achieved by macros that create a test sequence for an
> instruction and check for a supplied correct v
On Fri, Jun 05, 2020 at 06:56:56PM +0200, Philippe Mathieu-Daudé wrote:
> Add an entry for to allow reviewers to be notified when acceptance /
> integration tests are added or modified.
> The designated reviewers are not maintainers, subsystem maintainers
> are expected to merge their tests.
>
>
Convert the Neon VTRN insn to decodetree. This is the last insn in the
Neon data-processing group, so we can remove all the now-unused old
decoder framework.
It's possible that there's a more efficient implementation of
VTRN, but for this conversion we just copy the existing approach.
Signed-off-
On Mon, Jun 15, 2020 at 5:51 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Per the SiFive manual, all E/U series CPU cores' reset vector is
> at 0x1004. Update our codes to match the hardware.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
>
> ---
>
> Changes in v2:
> - rebas
Convert the Neon VSWP insn to decodetree. Since the new implementation
doesn't have to share a pass-loop with the other 2-reg-misc operations
we can implement the swap with 64-bit accesses rather than 32-bits
(which brings us into line with the pseudocode and is more efficient).
Signed-off-by: Pet
Bastian Koppelmann writes:
> this includes the Makefile and linker script to build all the tests.
>
> Signed-off-by: Bastian Koppelmann
> ---
> tests/tcg/tricore/Makefile.softmmu-target | 17 +++
> tests/tcg/tricore/link.ld | 60 +++
> 2 files changed,
Convert the Neon 2-reg-misc VRINT insns to decodetree.
Giving these insns their own do_vrint() function allows us
to change the rounding mode just once at the start and end
rather than doing it for every element in the vector.
Signed-off-by: Peter Maydell
---
target/arm/neon-dp.decode | 8
On Mon, Jun 15, 2020 at 5:51 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Current IBEX CPU init routine name seems to be too generic.
> Since it uses a different reset vector from the generic one,
> it merits a dedicated name.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
>
Convert the Neon VQABS and VQNEG insns to decodetree.
Since these are the only ones which need cpu_env passing to
the helper, we wrap the helper rather than creating a whole
new do_2misc_env() function.
Signed-off-by: Peter Maydell
---
target/arm/neon-dp.decode | 3 +++
target/arm/transla
* Gerd Hoffmann (kra...@redhat.com) wrote:
> Hi,
>
> > > If we can somehow make a *trustable* physbits value available to the
> > > guest, then yes, we can go that route. But the guest physbits we have
> > > today unfortunately don't cut it.
> >
> > In downstream RH qemu, we run with host-phys
Make gen_swap_half() take a source and destination TCGv_i32 rather
than modifying the input TCGv_i32; we're going to want to be able to
use it with the more flexible function signature, and this also
brings it into line with other functions like gen_rev16() and
gen_revsh().
Signed-off-by: Peter Ma
Patchew URL:
https://patchew.org/QEMU/1592310699-58916-1-git-send-email-ani.si...@nutanix.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!
On Tue, Jun 16, 2020 at 05:57:46PM +0100, Dr. David Alan Gilbert wrote:
> * Gerd Hoffmann (kra...@redhat.com) wrote:
> > Hi,
> >
> > > (a) We could rely in the guest physbits to calculate the PCI64 aperture.
> >
> > I'd love to do that. Move the 64-bit I/O window as high as possible and
> > us
The NeonGenOneOpFn typedef breaks with the pattern of the other
NeonGen*Fn typedefs, because it is a TCGv_i64 -> TCGv_i64 operation
but it does not have '64' in its name. Rename it to NeonGenOne64OpFn,
so that the old name is available for a TCGv_i32 -> TCGv_i32 operation
(which we will need in a s
Convert the VCVT instructions in the 2-reg-misc grouping to
decodetree.
Signed-off-by: Peter Maydell
---
target/arm/neon-dp.decode | 9 +
target/arm/translate-neon.inc.c | 70 +
target/arm/translate.c | 70 -
3 f
Hi,
> > If we can somehow make a *trustable* physbits value available to the
> > guest, then yes, we can go that route. But the guest physbits we have
> > today unfortunately don't cut it.
>
> In downstream RH qemu, we run with host-physbits as default; so it's
> reasonably
> trustworthy;
Ca
The functions neon_element_offset(), neon_load_element(),
neon_load_element64(), neon_store_element() and
neon_store_element64() are used only in the translate-neon.inc.c
file, so move their definitions there.
Since the .inc.c file is #included in translate.c this doesn't make
much difference curr
Convert the VREV32 and VREV16 insns in the Neon 2-reg-misc group
to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate.h | 1 +
target/arm/neon-dp.decode | 2 ++
target/arm/translate-neon.inc.c | 55 +
target/arm/translate.c
Convert the Neon-2-reg misc crypto ops (AESE, AESMC, SHA1H, SHA1SU1)
to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/neon-dp.decode | 12
target/arm/translate-neon.inc.c | 42 ++
target/arm/translate.c | 52 +++---
Convert the fp-compare-with-zero insns in the Neon 2-reg-misc group to
decodetree.
Signed-off-by: Peter Maydell
---
target/arm/neon-dp.decode | 6
target/arm/translate-neon.inc.c | 28 ++
target/arm/translate.c | 50 -
3 files
Convert the remaining ops in the Neon 2-reg-misc group which
can be implemented simply with our do_2misc() helper.
Signed-off-by: Peter Maydell
---
target/arm/neon-dp.decode | 10 +
target/arm/translate-neon.inc.c | 69 +
target/arm/translate.c
All the other typedefs like these spell "Op" with a lowercase 'p';
remane the NeonGenTwoSingleOPFn and NeonGenTwoDoubleOPFn typedefs to
match.
Signed-off-by: Peter Maydell
---
target/arm/translate.h | 4 ++--
target/arm/translate-a64.c | 4 ++--
target/arm/translate-neon.inc.c | 2
Convert the VSHLL insn in the 2-reg-misc Neon group to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/neon-dp.decode | 2 ++
target/arm/translate-neon.inc.c | 52 +
target/arm/translate.c | 35 +-
3 files changed, 55 in
Convert the Neon 2-reg-misc insns which are implemented with
simple calls to functions that take the input, output and
fpstatus pointer.
Signed-off-by: Peter Maydell
---
target/arm/translate.h | 1 +
target/arm/neon-dp.decode | 8 +
target/arm/translate-neon.inc.c | 62 +
Convert the Neon narrowing moves VMQNV, VQMOVN, VQMOVUN in the 2-reg-misc
group to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/neon-dp.decode | 9
target/arm/translate-neon.inc.c | 59
target/arm/translate.c | 81 +
Convert the Neon VREV64 insn from the 2-reg-misc grouping to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/neon-dp.decode | 12
target/arm/translate-neon.inc.c | 50 +
target/arm/translate.c | 24 ++--
3 files changed,
Convert the Neon insns in the 2-reg-misc group which are
VCVT between f32 and f16 to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/neon-dp.decode | 3 ++
target/arm/translate-neon.inc.c | 96 +
target/arm/translate.c | 65 ++--
Convert to decodetree the insns in the Neon 2-reg-misc grouping which
we implement using gvec.
Signed-off-by: Peter Maydell
---
target/arm/neon-dp.decode | 11 +++
target/arm/translate-neon.inc.c | 55 +
target/arm/translate.c | 35 +
Convert the pairwise ops VPADDL and VPADAL in the 2-reg-misc grouping
to decodetree.
At this point we can get rid of the weird CPU_V001 #define that was
used to avoid having to explicitly list all the arguments being
passed to some TCG gen/helper functions.
Signed-off-by: Peter Maydell
---
targ
Convert the Neon VZIP and VUZP insns in the 2-reg-misc group to
decodetree.
Signed-off-by: Peter Maydell
---
target/arm/neon-dp.decode | 3 ++
target/arm/translate-neon.inc.c | 74 ++
target/arm/translate.c | 92 +
3 files c
This patchset completes the conversion of Neon to decodetree
by converting all the instructions in the 2-reg-misc grouping.
There are some potential further cleanups available, which I don't
propose to do (I've spent what feels like too much time on this
refactoring already; I want to move onto im
Bastian Koppelmann writes:
> this device is used to verify the correctness of regression tests by
> allowing guests to write their exit status to this device. This is then
> used by qemu to exit using the written status.
>
> Signed-off-by: Bastian Koppelmann
Reviewed-by: Alex Bennée
--
Ale
On 6/5/20 6:56 PM, Philippe Mathieu-Daudé wrote:
> Add an entry for to allow reviewers to be notified when acceptance /
> integration tests are added or modified.
> The designated reviewers are not maintainers, subsystem maintainers
> are expected to merge their tests.
>
> Signed-off-by: Philippe
Hi Alex,
thanks for looking at this,
On 6/16/20 4:16 PM, Alex Bennée wrote:
>
> Claudio Fontana writes:
>
>> each accelerator registers a new "CpusAccel" interface
>> implementation on initialization, providing functions for
>> starting a vcpu, kicking a vcpu, and sychronizing state.
>>
>> Thi
On Tue, 5 May 2020 14:57:51 +0200
Eric Farman wrote:
> Here is a new pass at the channel-path handling code for vfio-ccw,
> to take advantage of the corresponding kernel patches posted here:
>
> https://lore.kernel.org/kvm/20200505122745.53208-1-far...@linux.ibm.com/
>
> I have all the main co
The Linux TSC calibration procedure is subject to small variations
(its common to see +-1 kHz difference between reboots on a given CPU, for
example).
So migrating a guest between two hosts with identical processor can fail, in
case
of a small variation in calibrated TSC between them.
Allow
* Gerd Hoffmann (kra...@redhat.com) wrote:
> Hi,
>
> > (a) We could rely in the guest physbits to calculate the PCI64 aperture.
>
> I'd love to do that. Move the 64-bit I/O window as high as possible and
> use -- say -- 25% of the physical address space for it.
>
> Problem is we can't.
>
> >
OK the syscall_nr failure is a red hearing - that was affected by a
stray generated file in my source tree (maybe I accidentally ran make in
the top directory?).
However I've just run into the mips64le-linux-user crash again which
didn't go away until I deleted all mips* directories and rebuilt.
Are you able to bisect between 4.2 and 5.0 and identify what introduces
the slow down?
** Tags added: tcg
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1883593
Title:
Windows XP takes much longer
On Tue, 16 Jun 2020 at 14:51, Alex Bennée wrote:
>
> The following changes since commit f5e34624f28f37ec3c8a93bdee348effee966a78:
>
> Merge remote-tracking branch
> 'remotes/amarkovic/tags/mips-queue-jun-15-2020' into staging (2020-06-16
> 11:00:28 +0100)
>
> are available in the Git repositor
On Tue, Jun 16, 2020 at 05:49:47PM +0100, David Edmondson wrote:
> On Monday, 2020-06-15 at 11:36:31 +01, Daniel P. Berrangé wrote:
>
> > +if test "$secret_keyring" != "no"
> > +then
> > +if test "$have_keyring" == "yes"
>
> This generates a complaint when building on Debian testing:
>
> ./c
Hi,
> (a) We could rely in the guest physbits to calculate the PCI64 aperture.
I'd love to do that. Move the 64-bit I/O window as high as possible and
use -- say -- 25% of the physical address space for it.
Problem is we can't.
> failure. Also, if the users are not setting the physbits in th
On Monday, 2020-06-15 at 11:36:31 +01, Daniel P. Berrangé wrote:
> +if test "$secret_keyring" != "no"
> +then
> +if test "$have_keyring" == "yes"
This generates a complaint when building on Debian testing:
./configure: 6319: test: yes: unexpected operator
Perhaps should be a single = ?
> +
On Tue, 16 Jun 2020 18:09:04 +0200
Christian Schoenebeck wrote:
> On Dienstag, 16. Juni 2020 17:14:40 CEST Greg Kurz wrote:
> > Cc'ing co-maintainer Christian Schoenebeck.
> >
> > Christian,
> >
> > If there are some more commits you think are worth being cherry picked
> > for QEMU 4.2.1, pleas
On Mon, Jun 15, 2020 at 12:34:56PM +0200, Philippe Mathieu-Daudé wrote:
> On the host OS, various aspects of TLS operation are configurable.
> In particular it is possible for the sysadmin to control the TLS
> cipher/protocol algorithms that applications are permitted to use.
>
> * Any given crypt
On Tue, 16 Jun 2020 at 17:08, Alex Bennée wrote:
> Apart from "a more perfect emulation" is there a particular use case
> served by the extra functionality? AIUI up until this point we've
> basically supported glibc's use of clone() which has generally been
> enough. I'm assuming you've come acros
Right now bdrv_fclose() is just calling bdrv_flush().
The problem is that migration code is working inefficently from black
layer terms and are frequently called for very small pieces of not
properly aligned data. Block layer is capable to work this way, but
this is very slow.
This patch is a pre
This series do standard basic things:
- it creates intermediate buffer for all writes from QEMU migration code
to QCOW2 image,
- this buffer is sent to disk asynchronously, allowing several writes to
run in parallel.
In general, migration code is fantastically inefficent (by observation),
buff
It is not used outside the module.
Actually there are 2 kind of waiters:
- for a slot and
- for all tasks to finish
This patch limits external API to listed types.
Signed-off-by: Denis V. Lunev
Suggested-by: Vladimir Sementsov-Ogievskiy
CC: Kevin Wolf
CC: Max Reitz
CC: Stefan Hajnoczi
CC: Fa
Bastian Koppelmann writes:
> when trying to run successful short tests from the Makefile timeout would no
> terminate. Rather it would wait until the time runs out. Excerpt from the
> manpage:
Which tests hang without this change?
>
> --foreground
> when not running timeout directly from
qemu_fclose() could return error, f.e. if bdrv_co_flush() will return
the error.
This validation will become more important once we will start waiting of
asynchronous IO operations, started from bdrv_write_vmstate(), which are
coming soon.
Signed-off-by: Denis V. Lunev
Reviewed-by: "Dr. David Al
This patch does 2 standard basic things:
- it creates intermediate buffer for all writes from QEMU migration code
to block driver,
- this buffer is sent to disk asynchronously, allowing several writes to
run in parallel.
Thus bdrv_vmstate_write() is becoming asynchronous. All pending operation
From: Vladimir Sementsov-Ogievskiy
Currently, aio task pool assumes that there is a main coroutine, which
creates tasks and wait for them. Let's remove the restriction by using
CoQueue. Code becomes clearer, interface more obvious.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Deni
In util/Makefile.objs, there is a setting for dbus.o-libs.
Trying to copy-paste that to add a library for module.o that was was
not otherwise linked yields link errors on a number of binaries,
e.g. qemu-ga, with unsatisfied symbols in libqemuutil.a(module.o).
The reason is that library dependencies
On 16/06/2020 17.49, Philippe Mathieu-Daudé wrote:
> Commit 96927c744 replaced qdev_init_nofail() call by
> isa_realize_and_unref() which has a different error
> message. Update the test output accordingly.
>
> Gitlab CI error after merging b77b5b3dc7:
> https://gitlab.com/qemu-project/qemu/-/jobs
Bastian Koppelmann writes:
> At least for the TriCore target no easily available c compiler exists.
> Thus we need to rely on "as" and "ld". This allows us to run them
> through the docker image.
>
> Signed-off-by: Bastian Koppelmann
> ---
> tests/tcg/Makefile.qemu | 11 +++
> tests/t
On 6/16/20 11:45 AM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Cédric Le Goater
Tested-by: Cédric Le Goater
Download an OpenBMC witherspoon flash image :
wget
https://openpower.xyz/job/openbmc-build/lastSuccessfulBuild/distro=ubuntu,label=builder,ta
>From 7eef8b803cdb0e7148fdf894d2992052695c1ff8 Mon Sep 17 00:00:00 2001
From: David Carlier
Date: Tue, 26 May 2020 21:35:27 +0100
Subject: [PATCH] util/oslib-posix : qemu_init_exec_dir implementation for Mac
Using dyld API to get the full path of the current process.
Signed-off-by: David Carlier
On Dienstag, 16. Juni 2020 17:14:40 CEST Greg Kurz wrote:
> Cc'ing co-maintainer Christian Schoenebeck.
>
> Christian,
>
> If there are some more commits you think are worth being cherry picked
> for QEMU 4.2.1, please inform Michael before freeze on 2020-06-22.
Indeed, for that particular stabl
Am 29.05.2020 um 00:55 hat Roman Kagan geschrieben:
> BlockConf includes several properties counted in bytes.
>
> Enhance their handling in some aspects, specifically
>
> - accept common size suffixes (k, m)
> - perform consistency checks on the values
> - lift the upper limit on physical_block_s
Josh Kunz writes:
> The `clone` system call can be used to create new processes that share
> attributes with their parents, such as virtual memory, file
> system location, file descriptor tables, etc. These can be useful to a
> variety of guest programs.
>
> Before this patch, QEMU had support
** Changed in: qemu
Status: Expired => New
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https://bugs.launchpad.net/bugs/697510
Title:
Machine shut off after tons of lsi_scsi: error: MSG IN data too long
Status in QEMU:
Josh Kunz writes:
> This patch series implements extended support for the `clone` system
> call. As best I can tell, any option combination including `CLONE_VM`
> should be supported with the addition of this patch series. The
> implementation is described in greater detail in the patches thems
Public bug reported:
To reproduce run the QEMU with the following command line:
```
qemu-system-x86_64 -cdrom hypertrash.iso -nographic -m 100 -enable-kvm -net
none -drive id=disk,file=hda.img,if=none -device ahci,id=ahci -device
ide-hd,drive=disk,bus=ahci.0
```
QEMU Version:
```
# qemu-5.0.0
$
** Changed in: qemu
Status: Expired => New
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https://bugs.launchpad.net/bugs/1525123
Title:
USB assert failure on hcd-uhci.c
Status in QEMU:
New
Bug description:
When inser
We found a reproducer during fuzzing:
```
qemu-system-x86_64: hw/ide/core.c:724: ide_cancel_dma_sync: Assertion
`s->bus->dma->aiocb == NULL' failed.
```
To reproduce run the QEMU with the following command line:
```
qemu-system-x86_64 -cdrom hypertrash.iso -nographic -m 100 -enable-kvm -net
non
We found a reproducer during fuzzing:
```
qemu-system-x86_64: hw/scsi/lsi53c895a.c:624: lsi_do_dma: Assertion
`s->current' failed.
```
To reproduce run the QEMU with the following command line:
```
qemu-system-x86_64 -cdrom hypertrash.iso -nographic -m 100 -enable-kvm -net
none -device ich9-usb
On 16/06/2020 16.49, Philippe Mathieu-Daudé wrote:
> On 6/16/20 3:34 PM, Thomas Huth wrote:
>> On 11/06/2020 13.43, Philippe Mathieu-Daudé wrote:
>>> Commit 81527b94ad added hw/intc/sh_intc.c, complete by
>>> adding its corresponding header.
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé
>>> ---
>>
We can reproduce this bug in QEMU 5.0.0
```
qemu-system-x86_64: hw/usb/core.c:723: usb_ep_get: Assertion `pid ==
USB_TOKEN_IN || pid == USB_TOKEN_OUT' failed.
```
To reproduce run the QEMU with the following command line:
```
qemu-system-x86_64 -cdrom hypertrash.iso -nographic -m 100 -enable-kvm
Josh Kunz writes:
> This is pre-work for adding full support for the `CLONE_VM` `clone`
> flag. In a follow-up patch, we'll add support to `clone.c` for
> `clone_vm`-type clones beyond threads. CLONE_VM support is more
> complicated, so first we're splitting existing clone mechanisms
> (pthread
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