Re: [PATCH 7/7] hw/misc/mps2-fpgaio: Implement push-buttons

On 6/16/20 12:27 PM, Peter Maydell wrote: > On Tue, 16 Jun 2020 at 07:32, Philippe Mathieu-Daudé wrote: >> >> The FPGA system control block has 2 push-buttons labelled PB0/PB1. >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- > >> @@ -249,6 +258,8 @@ static void mps2_fpgaio_init(Object *obj) >

[PATCH v4 6/6] linux-user: Add strace support for printing arguments of fallocate()

From: Filip Bozuta This patch implements strace argument printing functionality for following syscall: *fallocate - manipulate file space int fallocate(int fd, int mode, off_t offset, off_t len) man page: https://www.man7.org/linux/man-pages/man2/fallocate.2.html Implement

[PATCH v4 5/6] linux-user: Add strace support for printing arguments of chown()/lchown()

From: Filip Bozuta This patch implements strace argument printing functionality for syscalls: *chown, lchown - change ownership of a file int chown(const char *pathname, uid_t owner, gid_t group) int lchown(const char *pathname, uid_t owner, gid_t group) man page: ht

[PATCH v4 4/6] linux-user: Add strace support for printing arguments of lseek()

From: Filip Bozuta This patch implements strace argument printing functionality for syscall: *lseek - reposition read/write file offset off_t lseek(int fd, off_t offset, int whence) man page: https://www.man7.org/linux/man-pages/man2/lseek.2.html Implementation notes:

[PATCH v4 1/6] linux-user: Extend strace support to enable argument printing after syscall execution

From: Filip Bozuta Structure "struct syscallname" in file "strace.c" is used for "-strace" to print arguments and return values of syscalls. The last field of this structure "result" represents the calling function that prints the return values. This field was extended in this pat

[PATCH v4 0/6] Add strace support for printing arguments of selected syscalls

From: Filip Bozuta This series covers strace support for printing arguments of following syscalls: *acct() *lgetxattr() *removexattr() *lchown() *fsync() *fgetxattr() *lremovexattr() *fallocate() *fdatasync() *listxattr() *fremovex

[PATCH v4 2/6] linux-user: Add strace support for a group of syscalls

From: Filip Bozuta This patch implements strace argument printing functionality for following syscalls: *acct - switch process accounting on or off int acct(const char *filename) man page: https://www.man7.org/linux/man-pages/man2/acct.2.html *fsync, fdatasync - synchr

[PATCH v4 3/6] linux-user: Add strace support for printing argument of syscalls used for extended attributes

From: Filip Bozuta This patch implements strace argument printing functionality for following syscalls: *getxattr, lgetxattr, fgetxattr - retrieve an extended attribute value ssize_t getxattr(const char *path, const char *name, void *value, size_t size) ssize_t lgetxattr(c

[PATCH v2 0/2] target/mips: Add two groups of loongson-ext instructions

уторак, 16. јун 2020., Jiaxun Yang је написао/ла: > This is the sucessor of: > "Basic TCG Loongson-3A1000 Support" > > Thanks! > > Hi, Jiaxun. Thanks for providing updated version of the series. I wonder, given so many "#if defined(TARGET_MIPS64)" lines in this series, what would be the 32-bit

Re: [PATCH 6/7] hw/arm/mps2: Map the FPGA I/O block

On 6/16/20 12:26 PM, Peter Maydell wrote: > On Tue, 16 Jun 2020 at 07:32, Philippe Mathieu-Daudé wrote: >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- > >> @@ -337,6 +339,11 @@ static void mps2_common_init(MachineState *machine) >> >> sysbus_create_simple("versatile_i2c", i2cbase[i]

Re: [PATCH 3/7] hw/arm/mps2: Add CMSDK APB watchdog as unimplemented device

On 6/16/20 12:17 PM, Peter Maydell wrote: > On Tue, 16 Jun 2020 at 07:32, Philippe Mathieu-Daudé wrote: >> >> Register the watchdog peripheral as unimplemented to better >> follow its accesses, for example booting Zephyr: > > We have a TYPE_CMSDK_APB_WATCHDOG device; so we could use > that, I thi

Re: [PATCH 00/22] ADB: fix autopoll issues and rework mac_via state machine

Tested-by: Finn Thain Thanks for all your work on this. I've just noticed a discrepancy between the traces from an ADB bus scan on Laurent's Apple Quadra and an ADB bus scan on your patched QEMU machine. Apple Q800: [C1f][s ][Rff-][Rff ][rff-] [C2f][s ][R61 ][R05 ][r00-] [C3f][s ][R79

Re: [PATCH 7/7] hw/misc/mps2-fpgaio: Implement push-buttons

On Tue, 16 Jun 2020 at 07:32, Philippe Mathieu-Daudé wrote: > > The FPGA system control block has 2 push-buttons labelled PB0/PB1. > > Signed-off-by: Philippe Mathieu-Daudé > --- > @@ -249,6 +258,8 @@ static void mps2_fpgaio_init(Object *obj) > memory_region_init_io(&s->iomem, obj, &mps2_fp

Re: [PATCH 6/7] hw/arm/mps2: Map the FPGA I/O block

On Tue, 16 Jun 2020 at 07:32, Philippe Mathieu-Daudé wrote: > > Signed-off-by: Philippe Mathieu-Daudé > --- > @@ -337,6 +339,11 @@ static void mps2_common_init(MachineState *machine) > > sysbus_create_simple("versatile_i2c", i2cbase[i], NULL); > } > +sysbus_init_child_obj(OBJEC

Re: [PATCH 5/7] hw/arm/mps2: Add I2C busses on FPGA APB

On Tue, 16 Jun 2020 at 07:32, Philippe Mathieu-Daudé wrote: > > There are 4 different I2C peripherals on the FPGA APB. > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/arm/mps2.c | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c > index 4a49bfa9b9.

Re: [PATCH 4/7] hw/arm/mps2: Add CMSDK AHB GPIO peripherals as unimplemented devices

On Tue, 16 Jun 2020 at 07:32, Philippe Mathieu-Daudé wrote: > > Register the GPIO peripherals as unimplemented to better > follow their accesses, for example booting Zephyr: > Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH 3/7] hw/arm/mps2: Add CMSDK APB watchdog as unimplemented device

On Tue, 16 Jun 2020 at 07:32, Philippe Mathieu-Daudé wrote: > > Register the watchdog peripheral as unimplemented to better > follow its accesses, for example booting Zephyr: We have a TYPE_CMSDK_APB_WATCHDOG device; so we could use that, I think ? thanks -- PMM

Re: [PATCH 2/7] hw/arm/mps2: Rename dualtimer as apb-dualtimer

On Tue, 16 Jun 2020 at 07:32, Philippe Mathieu-Daudé wrote: > > The dualtimer is connected to AMBA APB. True, but that doesn't mean we need to name it "apb-something". The AN385 TRM just calls it "Dual timer". thanks -- PMM

Re: [PATCH 1/7] hw/arm/mps2: Rename CMSDK AHB peripheral region

On Tue, 16 Jun 2020 at 07:32, Philippe Mathieu-Daudé wrote: > > To differenciate with the CMSDK APB peripheral region, > rename this region 'CMSDK AHB peripheral region'. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell thanks -- PMM

Re: [PULL 0/7] fuzzing and other test-related patches

On Tue, 16 Jun 2020 at 09:58, Thomas Huth wrote: > > Hi Peter, > > the following changes since commit 7d3660e79830a069f1848bb4fa1cdf8f666424fb: > > Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into > staging (2020-06-12 23:06:22 +0100) > > are available in the Git repositor

[PULL 22/23] sd: sdhci: Implement basic vendor specific register support

From: Guenter Roeck The Linux kernel's IMX code now uses vendor specific commands. This results in endless warnings when booting the Linux kernel. sdhci-esdhc-imx 2194000.usdhc: esdhc_wait_for_card_clock_gate_off: card clock still not gate off in 100us!. Implement support for the vendor

Re: [PATCH v2] migration: Count new_dirty instead of real_dirty

* zhukeqian (zhukeqi...@huawei.com) wrote: > Hi Dave, > > On 2020/6/16 17:35, Dr. David Alan Gilbert wrote: > > * Keqian Zhu (zhukeqi...@huawei.com) wrote: > >> real_dirty_pages becomes equal to total ram size after dirty log sync > >> in ram_init_bitmaps, the reason is that the bitmap of ramblock

[PULL 21/23] hw/net/imx_fec: Convert debug fprintf() to trace events

From: Jean-Christophe Dubois Signed-off-by: Jean-Christophe Dubois Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé [PMD: Fixed 32-bit format string using PRIx32/PRIx64] Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- hw/net/imx_fec.c| 106 +++

[PULL 23/23] hw: arm: Set vendor property for IMX SDHCI emulations

From: Guenter Roeck Set vendor property to IMX to enable IMX specific functionality in sdhci code. Tested-by: Philippe Mathieu-Daudé Signed-off-by: Guenter Roeck Reviewed-by: Philippe Mathieu-Daudé Message-id: 20200603145258.195920-3-li...@roeck-us.net Signed-off-by: Peter Maydell --- hw/ar

[PULL 20/23] target/arm/cpu: adjust virtual time for all KVM arm cpus

From: fangying Virtual time adjustment was implemented for virt-5.0 machine type, but the cpu property was enabled only for host-passthrough and max cpu model. Let's add it for any KVM arm cpu which has the generic timer feature enabled. Signed-off-by: Ying Fang Reviewed-by: Andrew Jones Mess

[PULL 19/23] Implement configurable descriptor size in ftgmac100

From: Erik Smit The hardware supports configurable descriptor sizes, configured in the DBLAC register. Most drivers use the default 4 word descriptor, which is currently hardcoded, but Aspeed SDK configures 8 words to store extra data. Signed-off-by: Erik Smit Reviewed-by: Cédric Le Goater [P

[PULL 17/23] target/arm: Convert Neon VDUP (scalar) to decodetree

Convert the Neon VDUP (scalar) insn to decodetree. (Note that we can't call this just "VDUP" as we used that already in vfp.decode for the "VDUP (general purpose register" insn.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 7 +++ targe

[PULL 14/23] target/arm: Convert Neon 2-reg-scalar long multiplies to decodetree

Convert the Neon 2-reg-scalar long multiplies to decodetree. These are the last instructions in the group. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 18 target/arm/translate-neon.inc.c | 163 target/arm/t

[PULL 11/23] target/arm: Convert Neon 2-reg-scalar float multiplies to decodetree

Convert the float versions of VMLA, VMLS and VMUL in the Neon 2-reg-scalar group to decodetree. Signed-off-by: Peter Maydell --- As noted in the comment on the WRAP_FP_FN macro, we could have had a do_2scalar_fp() function, but for 3 insns it seemed simpler to just do the wrapping to get hold of

[PULL 18/23] hw/misc/imx6ul_ccm: Implement non writable bits in CCM registers

From: Jean-Christophe Dubois Some bits of the CCM registers are non writable. This was left undone in the initial commit (all bits of registers were writable). This patch adds the required code to protect the non writable bits. Signed-off-by: Jean-Christophe Dubois Message-id: 20200608133508.

[PULL 16/23] target/arm: Convert Neon VTBL, VTBX to decodetree

Convert the Neon VTBL, VTBX instructions to decodetree. The actual implementation of the insn is copied across to the new trans function unchanged except for renaming 'tmp5' to 'tmp4'. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 3 ++ targ

[PULL 07/23] target/arm: Convert Neon 3-reg-diff polynomial VMULL

Convert the Neon 3-reg-diff insn polynomial VMULL. This is the last insn in this group to be converted. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 2 ++ target/arm/translate-neon.inc.c | 43 +++ target/arm/translate.c

[PULL 06/23] target/arm: Convert Neon 3-reg-diff saturating doubling multiplies

Convert the Neon 3-reg-diff insns VQDMULL, VQDMLAL and VQDMLSL: these are all saturating doubling long multiplies with a possible accumulate step. These are the last insns in the group which use the pass-over-each elements loop, so we can delete that code. Signed-off-by: Peter Maydell Reviewed-b

[PULL 13/23] target/arm: Convert Neon 2-reg-scalar VQRDMLAH, VQRDMLSH to decodetree

Convert the VQRDMLAH and VQRDMLSH insns in the 2-reg-scalar group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 3 ++ target/arm/translate-neon.inc.c | 74 + target/arm/translate.c | 38

[PULL 02/23] target/arm: Convert Neon 3-reg-diff prewidening ops to decodetree

Convert the "pre-widening" insns VADDL, VSUBL, VADDW and VSUBW in the Neon 3-registers-different-lengths group to decodetree. These insns work by widening one or both inputs to double their size, performing an add or subtract at the doubled size and then storing the double-size result. As usual, r

[PULL 05/23] target/arm: Convert Neon 3-reg-diff long multiplies

Convert the Neon 3-reg-diff insns VMULL, VMLAL and VMLSL; these perform a 32x32->64 multiply with possible accumulate. Note that for VMLSL we do the accumulate directly with a subtraction rather than doing a negate-then-add as the old code did. Signed-off-by: Peter Maydell Reviewed-by: Richard H

[PULL 15/23] target/arm: Convert Neon VEXT to decodetree

Convert the Neon VEXT insn to decodetree. Rather than keeping the old implementation which used fixed temporaries cpu_V0 and cpu_V1 and did the extraction with by-hand shift and logic ops, we use the TCG extract2 insn. We don't need to special case 0 or 8 immediates any more as the optimizer is sm

[PULL 12/23] target/arm: Convert Neon 2-reg-scalar VQDMULH, VQRDMULH to decodetree

Convert the VQDMULH and VQRDMULH insns in the 2-reg-scalar group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 3 +++ target/arm/translate-neon.inc.c | 29 +++ target/arm/translate.c | 42 ++

[PULL 10/23] target/arm: Convert Neon 2-reg-scalar integer multiplies to decodetree

Convert the VMLA, VMLS and VMUL insns in the Neon "2 registers and a scalar" group to decodetree. These are 32x32->32 operations where one of the inputs is the scalar, followed by a possible accumulate operation of the 32-bit result. The refactoring removes some of the oddities of the old decoder

[PULL 04/23] target/arm: Convert Neon 3-reg-diff VABAL, VABDL to decodetree

Convert the Neon 3-reg-diff insns VABAL and VABDL to decodetree. Like almost all the remaining insns in this group, these are a combination of a two-input operation which returns a double width result and then a possible accumulation of that double width result into the destination. Signed-off-by:

[PULL 01/23] target/arm: Fix missing temp frees in do_vshll_2sh

The widenfn() in do_vshll_2sh() does not free the input 32-bit TCGv, so we need to do this in the calling code. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/translate-neon.inc.c | 2 ++ 1 file changed, 2 insertions(+) diff --gi

[PULL 03/23] target/arm: Convert Neon 3-reg-diff narrowing ops to decodetree

Convert the narrow-to-high-half insns VADDHN, VSUBHN, VRADDHN, VRSUBHN in the Neon 3-registers-different-lengths group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-dp.decode | 6 +++ target/arm/translate-neon.inc.c | 87 ++

[PULL 09/23] target/arm: Add missing TCG temp free in do_2shift_env_64()

In commit 37bfce81b10450071 we accidentally introduced a leak of a TCG temporary in do_2shift_env_64(); free it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-neon.inc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/translate-neon.inc.c b/

[PULL 08/23] target/arm: Add 'static' and 'const' annotations to VSHLL function arrays

Mark the arrays of function pointers in trans_VSHLL_S_2sh() and trans_VSHLL_U_2sh() as both 'static' and 'const'. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-neon.inc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/tr

[PULL 00/23] target-arm queue

2020-06-15 16:36:34 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200616 for you to fetch changes up to 64b397417a26509bcdff44ab94356a35c7901c79: hw: arm: Set vendor property for IMX SDHCI emulations (2020-06-1

Re: [PATCH v2] migration: Count new_dirty instead of real_dirty

Hi Dave, On 2020/6/16 17:35, Dr. David Alan Gilbert wrote: > * Keqian Zhu (zhukeqi...@huawei.com) wrote: >> real_dirty_pages becomes equal to total ram size after dirty log sync >> in ram_init_bitmaps, the reason is that the bitmap of ramblock is >> initialized to be all set, so old path counts th

[PATCH 1/2] hw/misc/pca9552: Trace LED On/Off events

Signed-off-by: Philippe Mathieu-Daudé --- hw/misc/pca9552.c| 7 +++ hw/misc/trace-events | 3 +++ 2 files changed, 10 insertions(+) diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c index cac729e35a..a3d0decbff 100644 --- a/hw/misc/pca9552.c +++ b/hw/misc/pca9552.c @@ -17,6 +17,7 @@ #i

[PATCH 0/2] hw/misc/pca9552: Trace LEDs events, make LEDs 13-15 as GPIOs

The PCA9552 LEDs 13-15 can also be used as GPIOs. Philippe Mathieu-Daudé (2): hw/misc/pca9552: Trace LED On/Off events hw/misc/pca9552: Make LEDs 13-15 also GPIOs include/hw/misc/pca9552.h | 2 ++ hw/misc/pca9552.c | 25 + hw/misc/trace-events | 3 +++

[PATCH 2/2] hw/misc/pca9552: Make LEDs 13-15 also GPIOs

The PCA9552 has 3 GPIOs, add them. See 'PCA9552 Product Datasheet Rev. 05 - 9 March 2006', chapter 6.4 'Pins used as GPIOs': LED pins not used to control LEDs can be used as general purpose I/Os (GPIOs). For use as input, set LEDn to high-impedance (01) and then read the pin state via the

[PATCH v5 2/3] arm/acpi: Add the TPM2.0 device under the DSDT

In case it is dynamically instantiated, add the TPM 2.0 device object under the DSDT table in the ACPI namespace. Its HID is MSFT0101 while its current resource settings (CRS) property is initialized with the guest physical address and MMIO size of the device. Signed-off-by: Eric Auger Reviewed-b

Re: [PATCH v2] migration: Count new_dirty instead of real_dirty

* Keqian Zhu (zhukeqi...@huawei.com) wrote: > real_dirty_pages becomes equal to total ram size after dirty log sync > in ram_init_bitmaps, the reason is that the bitmap of ramblock is > initialized to be all set, so old path counts them as "real dirty" at > beginning. > > This causes wrong dirty r

[PATCH v5 1/3] acpi: Some build_tpm2() code reshape

Remove any reference to Acpi20TPM2 and adopt an implementation similar to build_ghes_v2(). Signed-off-by: Eric Auger Suggested-by: Igor Mammedov --- hw/acpi/aml-build.c | 45 ++--- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/hw/acpi/am

[PATCH v5 0/3] vTPM/aarch64 ACPI support

Those patches bring MMIO TPM TIS ACPI support in machvirt. On ARM, the TPM2 table is added when the TPM TIS sysbus device is dynamically instantiated in machvirt. Also the TPM2 device object is described in the DSDT. Many thanks to Ard for his support. Tested with LUKS partition automatic decry

[PATCH v5 3/3] docs/specs/tpm: ACPI boot now supported for TPM/ARM

ACPI boot now is supported. Let's remove the comment saying it is not. Signed-off-by: Eric Auger --- docs/specs/tpm.rst | 2 -- 1 file changed, 2 deletions(-) diff --git a/docs/specs/tpm.rst b/docs/specs/tpm.rst index 5e61238bc5..eeeb93730a 100644 --- a/docs/specs/tpm.rst +++ b/docs/specs/tpm.r

Re: [PATCH 1/2] virtio-ccw: fix virtio_set_ind_atomic

On Tue, 16 Jun 2020 07:58:53 +0200 Christian Borntraeger wrote: > > > On 16.06.20 06:50, Halil Pasic wrote: > > The atomic_cmpxchg() loop is broken because we occasionally end up with > > old and _old having different values (a legit compiler can generate code > > that accessed *ind_addr again

Re: [PATCH v5 1/2] target/arm: kvm: Handle DABT with no valid ISS

On Tue, 16 Jun 2020 at 09:33, Andrew Jones wrote: > > Hi Beata, > > I see Peter just picked this up, so I'm a bit late getting to it. I do > have a couple comments below though. I'll drop it from my queue again for the moment, then. thanks -- PMM

Re: [PATCH 1/1] os_find_datadir: search as in version 4.2

On Tue, 16 Jun 2020 at 00:00, Joe Slater wrote: > > Always look for ../share/qemu then ../pc-bios when looking for datadir. Could you provide some more context, please? Why is this change useful; presumably we broke some setup in 5.0, but what exactly ? I'm guessing this might be a regression in

Re: [PATCH v3] util/oslib-posix: : qemu_init_exec_dir implementation for Mac

On Mon, 15 Jun 2020 at 20:14, David CARLIER wrote: > > With this basic program > > #include > #include > > int main(void) > { > char buf[4096]; > uint32_t bufsize = sizeof(buf); > _NSGetExecutablePath(buf, &bufsize); > printf("%s\n", buf); > return 0; > } > > I get > > Davids-MacBook-Pro-2:Contr

Re: [PULL v2 0/5] Qcrypto next patches

On Mon, 15 Jun 2020 at 11:39, Daniel P. Berrangé wrote: > > The following changes since commit 7d3660e79830a069f1848bb4fa1cdf8f666424fb: > > Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagi= > ng (2020-06-12 23:06:22 +0100) > > are available in the Git repository at: >

[PULL 7/7] configure: Let SLOF be initialized by ./scripts/git-submodule.sh

From: Philippe Mathieu-Daudé The git-submodule.sh script is called by make and initialize the submodules listed in the GIT_SUBMODULES variable generated by ./configure. SLOF is required for building the s390-ccw firmware on s390x, since it is using the libnet code from SLOF for network booting.

[PULL 5/7] tests/qtest: Fix LGPL information in the file headers

It's either "GNU *Library* General Public License version 2" or "GNU Lesser General Public License version *2.1*", but there was no "version 2.0" of the "Lesser" license. So assume that version 2.1 is meant here. Message-Id: <20200605100645.6506-1-th...@redhat.com> Reviewed-by: Laurent Vivier Rev

[PULL 6/7] tests/acceptance: Add boot tests for sh4 QEMU advent calendar image

Now that we can select the second serial console in the acceptance tests (see commit 746f244d9720 "Allow to use other serial consoles than default"), we can also test the sh4 image from the QEMU advent calendar 2018. Message-Id: <20200515164337.4899-1-th...@redhat.com> Reviewed-by: Philippe Mathie

[PULL 4/7] fuzz: add oss-fuzz build-script

From: Alexander Bulekov It is neater to keep this in the QEMU repo, since any change that requires an update to the oss-fuzz build configuration, can make the necessary changes in the same series. Suggested-by: Philippe Mathieu-Daudé Signed-off-by: Alexander Bulekov Reviewed-by: Darren Kenny

[PULL 0/7] fuzzing and other test-related patches

Hi Peter, the following changes since commit 7d3660e79830a069f1848bb4fa1cdf8f666424fb: Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2020-06-12 23:06:22 +0100) are available in the Git repository at: https://gitlab.com/huth/qemu.git tags/pull-request-2020-

[PULL 3/7] fuzz: Add support for logging QTest commands

From: Alexander Bulekov Signed-off-by: Alexander Bulekov Message-Id: <20200529221450.26673-3-alx...@bu.edu> Reviewed-by: Darren Kenny Signed-off-by: Thomas Huth --- tests/qtest/fuzz/fuzz.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/tests/qtest/fuzz/fuzz.c b/te

[PULL 2/7] fuzz: skip QTest serialization

From: Alexander Bulekov The QTest server usually parses ASCII commands from clients. Since we fuzz within the QEMU process, skip the QTest serialization and server for most QTest commands. Leave the option to use the ASCII protocol, to generate readable traces for crash reproducers. Inspired-by:

[PULL 1/7] bios-tables-test: Fix "-tpmdev: invalid option"

From: Eric Auger When configure is run with "--disable-tpm", the bios-tables-test q35/tis test fails with "-tpmdev: invalid option". Skip the test if CONFIG_TPM is unset. Signed-off-by: Eric Auger Reported-by: Philippe Mathieu-Daudé Message-Id: <20200615135051.2213-1-eric.au...@redhat.com> Te

Re: [PATCH rc4 06/29] target/avr: Add defintions of AVR core types

Hi Michael, On 3/6/20 2:34 PM, Michael Rolnik wrote: > Hi all. > > are there any action items for me? I am not sure neither of the status of this. See below. > > Regards, > Michael Rolnik > > On Thu, Feb 27, 2020 at 10:38 AM Michael Rolnik > wrote: > > Hi all.

Re: [RFC v3 7/8] vhost-vdpa: introduce vhost-vdpa backend

On Mon, Jun 15, 2020 at 10:44 PM Laurent Vivier wrote: > > On 08/06/2020 22:14, Eric Blake wrote: > > On 5/29/20 9:06 AM, Cindy Lu wrote: > >> From: Tiwei Bie > > > > The original author is Tiwei Bie... > > > >> > >> Currently we have 2 types of vhost backends in QEMU: vhost kernel and > >> vhost

KVM call for 2020-06-30

Hi Please, send any topic that you are interested in covering. At the end of Monday I will send an email with the agenda or the cancellation of the call, so hurry up. After discussions on the QEMU Summit, we are going to have always open a KVM call where you can add topics. Call details: B

Re: KVM call for 2016-06-16

Juan Quintela wrote: > Hi Hi As there are no topics, this calls gets cancelled. Happy hacking. Later, Juan. > > Please, send any topic that you are interested in covering. > There is already a topic from last call: > > Last minute suggestion after recent IRC chat with Alex Bennée and > Thoma

Re: [PATCH] qga: Use gethostname() instead of g_get_host_name()

Hi On Tue, Jun 16, 2020 at 12:35 PM Michal Privoznik wrote: > Problem with g_get_host_name() is that on the first call it saves > the hostname into a global variable and from then on, every > subsequent call returns the saved hostname. Even if the hostname > changes. This doesn't play nicely wit

[PATCH] qga: Use gethostname() instead of g_get_host_name()

Problem with g_get_host_name() is that on the first call it saves the hostname into a global variable and from then on, every subsequent call returns the saved hostname. Even if the hostname changes. This doesn't play nicely with guest agent, because if the hostname is acquired before the guest is

Re: [PATCH v5 1/2] target/arm: kvm: Handle DABT with no valid ISS

Hi Beata, I see Peter just picked this up, so I'm a bit late getting to it. I do have a couple comments below though. Thanks, drew On Fri, May 29, 2020 at 12:27:56PM +0100, Beata Michalska wrote: > On ARMv7 & ARMv8 some load/store instructions might trigger a data abort > exception with no valid

Re: [RFC v3 6/8] vhost-backend: export the vhost backend helper

On 29/05/2020 16:06, Cindy Lu wrote: > export the helper then we can reuse some of them in vhost-vdpa > > Signed-off-by: Cindy Lu > --- > hw/virtio/vhost-backend.c | 34 ++- > include/hw/virtio/vhost-backend.h | 28 + > 2 files changed,

Re: [PATCH] hw/acpi: specify 64-bit acpi table

On Mon, 15 Jun 2020 18:36:54 -0600 "Jason A. Donenfeld" wrote: > SSDTs cannot address 64-bit physical addresses in 32-bit tables, so we please clarify what accesses waht within tables (i.e. be more concrete). > increment the revision to '2' so that these larger addresses are > addressable. This

Re: [RFC v3 5/8] vhost: introduce vhost_set_vring_ready method

On 29/05/2020 16:06, Cindy Lu wrote: > From: Jason Wang > > Vhost-vdpa introduces VHOST_VDPA_SET_VRING_ENABLE which complies the > semantic of queue_enable defined in virtio spec. This method can be > used for preventing device from executing request for a specific > virtqueue. This patch introdu

Re: [PATCH 4/7] hw/virtio/virtio-balloon: Rename timer field including 'ms' unit

On 16.06.20 09:51, Philippe Mathieu-Daudé wrote: > To make code review easier, append the timer unit (milli-seconds) > to its variable name. > > Signed-off-by: Philippe Mathieu-Daudé > --- > include/hw/virtio/virtio-balloon.h | 2 +- > hw/virtio/virtio-balloon.c | 14 -- > 2

Re: [RFC v3 4/8] virtio-pci: implement queue_enabled method

On 29/05/2020 16:06, Cindy Lu wrote: > From: Jason Wang > > With version 1, we can detect whether a queue is enabled via > queue_enabled. > > Signed-off-by: Jason Wang Add your S-o-b. > --- > hw/virtio/virtio-pci.c | 13 + > 1 file changed, 13 insertions(+) > > diff --git a/hw/v

[PATCH 7/7] hw/watchdog/wdt_aspeed: Reduce timer precision to micro-second

The current implementation uses nano-second precision, while the watchdog can not be more precise than a micro-second. Simplify by using a micro-second based timer. Rename the timer 'timer_us' to have the unit explicit. Inspired-by: Mark Cave-Ayland Signed-off-by: Philippe Mathieu-Daudé --- inc

[PATCH 5/7] hw/rtc/m48t59: Reduce timer precision to milli-second

The current implementation uses nano-second precision, while the RTC can not be more precise than a milli-second. Simplify by using a milli-second based timer. Rename the timer 'alrm_timer_ms' to have the unit explicit. Inspired-by: Mark Cave-Ayland Signed-off-by: Philippe Mathieu-Daudé --- hw/

[PATCH 4/7] hw/virtio/virtio-balloon: Rename timer field including 'ms' unit

To make code review easier, append the timer unit (milli-seconds) to its variable name. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/virtio/virtio-balloon.h | 2 +- hw/virtio/virtio-balloon.c | 14 -- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/inc

[PATCH 1/7] qemu-common: Briefly document qemu_timedate_diff() unit

It is not obvious that the qemu_timedate_diff() and qemu_ref_timedate() functions return seconds. Briefly document it. Signed-off-by: Philippe Mathieu-Daudé --- include/qemu-common.h | 1 + softmmu/vl.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/qemu-c

[PATCH 6/7] hw/ipmi/ipmi_bmc_extern: Reduce timer precision to milli-second

The current implementation uses nano-second precision, while the device can not be more precise than a milli-second. Simplify by using a milli-second based timer. Rename the timer 'extern_timer_ms' to have the unit explicit. Inspired-by: Mark Cave-Ayland Signed-off-by: Philippe Mathieu-Daudé Si

[PATCH 3/7] block/curl: Reduce timer precision to milli-second

The current implementation uses nano-second precision, while the block driver is only used with a milli-second precision. Simplify by using a milli-second based timer. Rename the timer 'timer_ms' to have the unit explicit. Inspired-by: Mark Cave-Ayland Signed-off-by: Philippe Mathieu-Daudé ---

[PATCH 0/7] misc: Reduce QEMUTimer pressure by using lower precision when possible

This series contains few patches resulting from the notes I took while reviewing Mark ADB series last Sunday, in particular: https://www.mail-archive.com/qemu-devel@nongnu.org/msg712078.html I have another patch for hw/input/hid.c but I prefer to hold it to test it more. Philippe Mathieu-Daudé (7

[PATCH 2/7] block/qcow2: Document cache_clean_interval field holds seconds

It is not obvious the 'cache_clean_interval' field holds a value expressing seconds. Add a brief comment. Signed-off-by: Philippe Mathieu-Daudé --- block/qcow2.h | 1 + 1 file changed, 1 insertion(+) diff --git a/block/qcow2.h b/block/qcow2.h index 7ce2c23bdb..fa5c2e64a1 100644 --- a/block/qcow

Re: [RFC v3 3/8] virtio-bus: introduce queue_enabled method

On 29/05/2020 16:06, Cindy Lu wrote: > From: Jason Wang > > This patch introduces queue_enabled() method which allows the > transport to implement its own way to report whether or not a queue is > enabled. > > Signed-off-by: Jason Wang Cindy, you must add your signed-off-by on all the patch yo

Re: [RFC v3 2/8] vhost_net: use the function qemu_get_peer

On 29/05/2020 16:06, Cindy Lu wrote: > user the qemu_get_peer to replace the old process > > Signed-off-by: Cindy Lu > --- > hw/net/vhost_net.c | 14 +- > 1 file changed, 9 insertions(+), 5 deletions(-) > > diff --git a/hw/net/vhost_net.c b/hw/net/vhost_net.c > index 6b82803fa7..d1d

Re: [PATCH v2 4/5] acpi: Enable TPM IRQ

Hi Stefan, On 6/15/20 7:11 PM, Stefan Berger wrote: > On 6/15/20 11:13 AM, Marc-André Lureau wrote: >> >>> diff --git a/include/hw/acpi/tpm.h b/include/hw/acpi/tpm.h >>> index 1a2a57a21f..063a9eb42a 100644 >>> --- a/include/hw/acpi/tpm.h >>> +++ b/include/hw/acpi/tpm.h >>> @@ -24,7 +24,7 @@ >>>  

Re: [PULL v2 00/58] virtio, acpi, pci: features, fixes, cleanups, tests

Hi, On 6/16/20 9:26 AM, Auger Eric wrote: > Hi Michael, > > + Stefan > > On 6/12/20 4:51 PM, Michael S. Tsirkin wrote: >> changes from v1: >> - printf format fixed for 32 bit hosts >> - a couple of bugfixes added >> >> The following changes since commit 49ee11555262a256afec592dfed7c5902d5eefd2:

[PATCH v2 0/2] target/mips: Add two groups of loongson-ext instructions

This is the sucessor of: "Basic TCG Loongson-3A1000 Support" Thanks! Jiaxun Yang (2): target/mips: Add loongson-ext lsdc2 group of instructions target/mips: Add loongson-ext lswc2 group of instrustions target/mips/translate.c | 437 1 file changed, 4

[PATCH v2 2/2] target/mips: Add loongson-ext lswc2 group of instrustions

LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE as "load/store quad word" and "shifted load/store" groups of instructions. Signed-off-by: Jiaxun Yang --- target/mips/translate.c | 258 1 file changed, 258 insertions(+) diff --git a/target/mips

[PATCH v2 1/2] target/mips: Add loongson-ext lsdc2 group of instructions

LDC2/SDC2 opcodes have been rewritten as "load & store with offset" group of instructions by loongson-ext ASE. Signed-off-by: Jiaxun Yang --- target/mips/translate.c | 179 1 file changed, 179 insertions(+) diff --git a/target/mips/translate.c b/target/m

[PATCH v2] target/mips: Fix PageMask with variable page size

Our current code assumed the target page size is always 4k when handling PageMask and VPN2, however, variable page size was just added to mips target and that's nolonger true. Signed-off-by: Jiaxun Yang --- v2: Remove Big Page support from this patch --- target/mips/cp0_helper.c | 41 +++

Re: [PULL v2 00/58] virtio, acpi, pci: features, fixes, cleanups, tests

Hi Michael, + Stefan On 6/12/20 4:51 PM, Michael S. Tsirkin wrote: > changes from v1: > - printf format fixed for 32 bit hosts > - a couple of bugfixes added > > The following changes since commit 49ee11555262a256afec592dfed7c5902d5eefd2: > > Merge remote-tracking branch > 'remotes/vivier2/t

Re: [PATCH v8 0/4] vhost-user block device backend implementation

On Mon, Jun 15, 2020 at 10:46:10AM +0200, Stefano Garzarella wrote: On Mon, Jun 15, 2020 at 02:46:40AM +0800, Coiby Xu wrote: Hi Stefano Garzarella, On Thu, Jun 11, 2020 at 02:37:03PM +0200, Stefano Garzarella wrote: > Hi Coiby Xu, > > On Fri, Jun 05, 2020 at 07:35:34AM +0800, Coiby Xu wrote: >

[PULL 28/33] net/colo-compare.c: Check that colo-compare is active

From: Lukas Straub If the colo-compare object is removed before failover and a checkpoint happens, qemu crashes because it tries to lock the destroyed event_mtx in colo_notify_compares_event. Fix this by checking if everything is initialized by introducing a new variable colo_compare_active whic

Re: [PATCH v9 0/5] vhost-user block device backend implementation

On Sun, Jun 14, 2020 at 12:16:28PM -0700, no-re...@patchew.org wrote: Patchew URL: https://patchew.org/QEMU/20200614183907.514282-1-coiby...@gmail.com/ Hi, This series failed the asan build test. Please find the testing commands and their output below. If you have Docker installed, you can p

Re: [PATCH v2 1/2] qemu-options.hx: Mark all hmat-cache attributes required

On 6/15/20 10:00 AM, Markus Armbruster wrote: Cc: the people involved in commit c412a48d4d "numa: Extend CLI to provide memory side cache information". Michal Privoznik writes: The documentation to `-numa hmat-cache` says that @node-id, @size and @level are the only required attributes. The r

<    1   2   3   4   5   6   >