Re: [PATCH] libqos: pci-pc: use 32-bit write for EJ register

On 23/06/20 22:55, Michael S. Tsirkin wrote: > On Tue, Jun 23, 2020 at 12:18:51PM -0400, Paolo Bonzini wrote: >> The memory region ops have min_access_size == 4 so obey it. >> >> Signed-off-by: Paolo Bonzini > > Reviewed-by: Michael S. Tsirkin > > I assume you are queueing this with the memory

[PATCH] scripts/simplebench: compare write request performance

The script 'bench_write_req.py' allows comparing performances of write request for two qemu-img binary files. Suggested-by: Denis V. Lunev Suggested-by: Vladimir Sementsov-Ogievskiy Signed-off-by: Andrey Shinkevich --- scripts/simplebench/bench_write_req.py | 150

[Bug 1884507] Re: 'none' machine should use 'none' display option

Actually, thinking about this twice, I think you made a wrong assumption here. "-display" is about the GUI backend that should be used. "-M" is about the emulated hardware. The emulated hardware options should never influence the host backend options. And it is e.g. perfectly valid to use the

Re: [PATCH] Revert "tests/migration: Reduce autoconverge initial bandwidth"

On 23/06/2020 19.35, Philippe Mathieu-Daudé wrote: > On 6/23/20 7:07 PM, Thomas Huth wrote: >> On 23/06/2020 17.39, Philippe Mathieu-Daudé wrote: >>> On 6/23/20 4:56 PM, Michael S. Tsirkin wrote: This reverts commit 6d1da867e65f ("tests/migration: Reduce autoconverge initial bandwidth")

Re: [PATCH v9 0/5] vhost-user block device backend implementation

On Fri, Jun 19, 2020 at 01:07:46PM +0100, Stefan Hajnoczi wrote: On Mon, Jun 15, 2020 at 02:39:02AM +0800, Coiby Xu wrote: v9 - move logical block size check function to a utility function - fix issues regarding license, coding style, memory deallocation, etc. I have replied with patches

Re: [PATCH v9 5/5] new qTest case to test the vhost-user-blk-server

On Thu, Jun 18, 2020 at 04:17:51PM +0100, Stefan Hajnoczi wrote: On Mon, Jun 15, 2020 at 02:39:07AM +0800, Coiby Xu wrote: This test case has the same tests as tests/virtio-blk-test.c except for tests have block_resize. Since vhost-user server can only server one client one time, two instances

Re: [PATCH v9 0/5] vhost-user block device backend implementation

On Thu, Jun 18, 2020 at 09:27:48AM +0100, Stefan Hajnoczi wrote: On Tue, Jun 16, 2020 at 02:52:16PM +0800, Coiby Xu wrote: On Sun, Jun 14, 2020 at 12:16:28PM -0700, no-re...@patchew.org wrote: > Patchew URL: https://patchew.org/QEMU/20200614183907.514282-1-coiby...@gmail.com/ > > > > Hi, > >

-enablefips

I never knew what this option did, but the answer is ... strange! It's only defined for linux, in os-posix.c. When called, it calls fips_set_state(true), located in osdep.c. This will read /proc/sys/crypto/fips_enabled and set the static global 'fips_enabled' to true if this setting is on.

Re: [PATCH v9 1/5] Allow vu_message_read to be replaced

On Thu, Jun 18, 2020 at 12:43:47PM +0200, Kevin Wolf wrote: Am 14.06.2020 um 20:39 hat Coiby Xu geschrieben: Allow vu_message_read to be replaced by one which will make use of the QIOChannel functions. Thus reading vhost-user message won't stall the guest. Signed-off-by: Coiby Xu

Re: sysbus failed assert for xen_sysdev

On Tue, Jun 23, 2020 at 9:22 AM Paul Durrant wrote: > > > -Original Message- > > From: Jason Andryuk > > Sent: 23 June 2020 13:57 > > To: Markus Armbruster > > Cc: Mark Cave-Ayland ; Anthony PERARD > > ; xen- > > devel ; Paul Durrant ; QEMU > > > > Subject: Re: sysbus failed assert

Re: sysbus failed assert for xen_sysdev

On Tue, Jun 23, 2020 at 7:46 AM Paul Durrant wrote: > > > -Original Message- > > From: Markus Armbruster > > Sent: 23 June 2020 09:41 > > To: Jason Andryuk > > Cc: Mark Cave-Ayland ; Anthony PERARD > > ; xen- > > devel ; Paul Durrant ; QEMU > > > > Subject: Re: sysbus failed assert

RE: [PATCH 0/2] net/colo-compare.c: Expose "max_queue_size" to users and clean up

> -Original Message- > From: Jason Wang > Sent: Tuesday, June 23, 2020 1:54 PM > To: Zhang, Chen ; Lukas Straub > > Cc: qemu-dev ; Zhang Chen > > Subject: Re: [PATCH 0/2] net/colo-compare.c: Expose "max_queue_size" to > users and clean up > > > On 2020/6/23 上午9:47, Zhang, Chen

Re: [PATCH] timer: Handle decrements of PIT counter

On Sat, Jun 13, 2020 at 02:19:12PM +0300, Roman Bolshakov wrote: > There's a fallback to PIT if TSC is not present but it doesn't work > properly. It prevents boot from floppy on isapc and 486 cpu [1][2]. > > SeaBIOS configures PIT in Mode 2. PIT counter is decremented in the mode > but

Re: how to build QEMU with the peripheral device modules

Hi , Thanks for the hints. I get better understanding to the kconfig tool now. I added "select TI_DMA" in my DSP kconfig file. It is done. best regards, xiaolei --Original-- From:"Philippe Mathieu-Daudé"

[PATCH V2 2/2] qemu-options.hx: Clean up and fix typo for colo-compare

From: Zhang Chen Fix some typo and optimized some descriptions. Signed-off-by: Zhang Chen --- qemu-options.hx | 32 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/qemu-options.hx b/qemu-options.hx index 3ee19a4b0d..aa7ffb34db 100644 ---

[PATCH V2 1/2] net/colo-compare.c: Expose compare "max_queue_size" to users

From: Zhang Chen This patch allow users to set the "max_queue_size" according to their environment. Signed-off-by: Zhang Chen --- net/colo-compare.c | 43 ++- qemu-options.hx| 5 +++-- 2 files changed, 45 insertions(+), 3 deletions(-) diff --git

[PATCH V2 0/2] net/colo-compare.c: Expose "max_queue_size" to users and clean up

From: Zhang Chen This series make a way to config COLO "max_queue_size" parameters according to user's scenarios and environments and do some clean up for descriptions. V2: - Rebase on upstream code. Zhang Chen (2): net/colo-compare.c: Expose compare "max_queue_size" to users

Re: [PATCH for-5.1 V5 2/4] hw/intc: Add Loongson liointc support

在 2020/6/23 22:50, Aleksandar Markovic 写道: уто, 23. јун 2020. у 14:13 Huacai Chen > је написао/ла: Loongson-3 has an integrated liointc (Local I/O interrupt controller). It is similar to goldfish interrupt controller, but more powerful (e.g., Any

Re: [PATCH] target/ppc: Remove TIDR from POWER10 processor

On Tue, Jun 23, 2020 at 05:45:34PM +0200, Cédric Le Goater wrote: > It is not part of Power ISA Version 3.1. Applied to ppc-for-5.1, thanks. > > Signed-off-by: Cédric Le Goater > --- > target/ppc/translate_init.inc.c | 5 - > 1 file changed, 5 deletions(-) > > diff --git

Re: [PATCH qemu v9] spapr: Implement Open Firmware client interface

Ping? On 02/06/2020 21:40, Alexey Kardashevskiy wrote: > Ping? > > On 13/05/2020 13:58, Alexey Kardashevskiy wrote: >> The PAPR platform which describes an OS environment that's presented by >> a combination of a hypervisor and firmware. The features it specifies >> require collaboration between

Re: [PATCH v11 00/61] target/riscv: support vector extension v0.7.1

Patchew URL: https://patchew.org/QEMU/20200623215920.2594-1-zhiwei_...@c-sky.com/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [PATCH v11 00/61] target/riscv: support vector extension v0.7.1 Type: series Message-id:

[PATCH v11 61/61] target/riscv: configure and turn on vector extension from command line

Vector extension is default off. The only way to use vector extension is 1. use cpu rv32 or rv64 2. turn on it by command line "-cpu rv64,x-v=true,vlen=128,elen=64,vext_spec=v0.7.1". vlen is the vector register length, default value is 128 bit. elen is the max operator size in bits, default

Re: [PATCH v6 0/4] Introduce Xilinx ZynqMP CAN controller

Patchew URL: https://patchew.org/QEMU/1592954616-65393-1-git-send-email-fnu.vik...@xilinx.com/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST

[PATCH v11 60/61] target/riscv: vector compress instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 5 target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 26

[PATCH v11 59/61] target/riscv: vector register gather instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 9 +++ target/riscv/insn32.decode | 3 + target/riscv/insn_trans/trans_rvv.inc.c | 78 + target/riscv/vector_helper.c| 60 +++

[PATCH v11 58/61] target/riscv: vector slide instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 18 target/riscv/vector_helper.c| 114 4 files

[PATCH v11 57/61] target/riscv: floating-point scalar move instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvv.inc.c | 49 + 2 files changed, 52 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index

[PATCH v11 56/61] target/riscv: integer scalar move instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 60 + target/riscv/internals.h| 6 +++ 3 files changed, 67 insertions(+) diff --git

[PATCH v11 55/61] target/riscv: integer extract instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 116 2 files changed, 117 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index

[PATCH v11 54/61] target/riscv: vector element index instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 25 + target/riscv/vector_helper.c| 24

[PATCH v11 53/61] target/riscv: vector iota instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 27 +++ target/riscv/vector_helper.c| 29

[PATCH v11 52/61] target/riscv: set-X-first mask bit

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 4 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvv.inc.c | 28 +++ target/riscv/vector_helper.c| 63 + 4

[PATCH v11 51/61] target/riscv: vmfirst find-first-set mask bit

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 19 +++ 4

[PATCH v6 0/4] Introduce Xilinx ZynqMP CAN controller

Changelog: v5 -> v6: Add ptimer based counter for time stamping on RX messages. Fix reset issues. Rebase the patches with master latest changes. Added reference clock property for CAN ptimer. v4 -> v5: Add XlnxZynqMPCAN controller id to debug messages. Drop parameter errp

[PATCH v11 50/61] target/riscv: vector mask population count vmpopc

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 20 4

[PATCH v11 49/61] target/riscv: vector mask-register logical instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 8 + target/riscv/insn_trans/trans_rvv.inc.c | 35 ++ target/riscv/vector_helper.c| 40

Re: [PULL v2 03/32] riscv: Generalize CPU init routine for the base CPU

On Tue, Jun 23, 2020 at 2:08 AM Markus Armbruster wrote: > > Bin Meng writes: > > > Hi Alistair, > > > > On Sat, Jun 20, 2020 at 1:09 AM Alistair Francis > > wrote: > >> > >> From: Bin Meng > >> > >> There is no need to have two functions that have exactly the same > >> codes for 32-bit and

[PATCH v11 48/61] target/riscv: vector widening floating-point reduction instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 3 ++ target/riscv/vector_helper.c| 46

Re: [PATCH] ibex_uart: fix XOR-as-pow

On Tue, Jun 23, 2020 at 1:07 PM Paolo Bonzini wrote: > > The xor-as-pow warning in clang actually detected a genuine bug. > Fix it. > > Signed-off-by: Paolo Bonzini > --- > hw/char/ibex_uart.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/char/ibex_uart.c

[PATCH v11 47/61] target/riscv: vector single-width floating-point reduction instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 10 +++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvv.inc.c | 5 target/riscv/vector_helper.c| 39

[PATCH v11 46/61] target/riscv: vector wideing integer reduction instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 7 +++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 4 target/riscv/vector_helper.c| 11

[PATCH v11 45/61] target/riscv: vector single-width integer reduction instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 18 ++ target/riscv/vector_helper.c|

[PATCH v11 44/61] target/riscv: narrowing floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 11 ++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 48 + target/riscv/vector_helper.c

[PATCH v11 43/61] target/riscv: widening floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 11 ++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 48 + target/riscv/vector_helper.c

[PATCH v11 42/61] target/riscv: vector floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 13 ++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvv.inc.c | 6 + target/riscv/vector_helper.c| 33

[PATCH v6 2/4] xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers

Connect CAN0 and CAN1 on the ZynqMP. Signed-off-by: Vikram Garhwal --- hw/arm/xlnx-zynqmp.c | 28 include/hw/arm/xlnx-zynqmp.h | 4 2 files changed, 32 insertions(+) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 1de9d4a..3f93524

[PATCH v6 3/4] tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller

The QTests perform five tests on the Xilinx ZynqMP CAN controller: Tests the CAN controller in loopback, sleep and snoop mode. Tests filtering of incoming CAN messages. Acked-by: Thomas Huth Signed-off-by: Vikram Garhwal --- tests/qtest/Makefile.include | 2 +

[PATCH v6 1/4] hw/net/can: Introduce Xilinx ZynqMP CAN controller

The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus implementation. Bus connection and socketCAN connection for each CAN module can be set through command lines. Example for using single CAN: -object can-bus,id=canbus0 \ -global

Re: [PATCH] i386: Mask SVM features if nested SVM is disabled

Patchew URL: https://patchew.org/QEMU/20200623230116.277409-1-ehabk...@redhat.com/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN

[PATCH v6 4/4] MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller

Reviewed-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Vikram Garhwal --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 63b3bb3..6f73a60 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1466,6 +1466,14 @@ F:

[PATCH v11 41/61] target/riscv: vector floating-point merge instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 4 +++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 38 + target/riscv/vector_helper.c

[PATCH v11 40/61] target/riscv: vector floating-point classify instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/fpu_helper.c | 33 + target/riscv/helper.h | 4 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 3 +

[PATCH v11 39/61] target/riscv: vector floating-point compare instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 37 + target/riscv/insn32.decode | 12 ++ target/riscv/insn_trans/trans_rvv.inc.c | 35 + target/riscv/vector_helper.c| 174

[PATCH v11 38/61] target/riscv: vector floating-point sign-injection instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 19 ++ target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 8 +++ target/riscv/vector_helper.c| 85

[PATCH v11 37/61] target/riscv: vector floating-point min/max instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 13 target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvv.inc.c | 6 ++ target/riscv/vector_helper.c

[PATCH v11 36/61] target/riscv: vector floating-point square-root instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 4 +++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvv.inc.c | 43 + target/riscv/vector_helper.c

[PATCH v11 35/61] target/riscv: vector widening floating-point fused multiply-add instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 17 + target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 +++ target/riscv/vector_helper.c| 91

[PATCH v11 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 49 + target/riscv/insn32.decode | 16 ++ target/riscv/insn_trans/trans_rvv.inc.c | 18 ++ target/riscv/vector_helper.c| 251

[PATCH v11 33/61] target/riscv: vector widening floating-point multiply

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 4 target/riscv/vector_helper.c| 22

[PATCH v11 32/61] target/riscv: vector single-width floating-point multiply/divide instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 16 target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 7 target/riscv/vector_helper.c| 49

[PATCH v11 31/61] target/riscv: vector widening floating-point add/subtract instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 17 +++ target/riscv/insn32.decode | 8 ++ target/riscv/insn_trans/trans_rvv.inc.c | 149 target/riscv/vector_helper.c

[PATCH] i386: Mask SVM features if nested SVM is disabled

QEMU incorrectly validates FEAT_SVM feature flags against GET_SUPPORTED_CPUID even if SVM features are being masked out by cpu_x86_cpuid(). This can make QEMU print warnings on most AMD CPU models, even when SVM nesting is disabled (which is the default). This bug was never detected before

[PATCH v11 30/61] target/riscv: vector single-width floating-point add/subtract instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 16 target/riscv/insn32.decode | 5 + target/riscv/insn_trans/trans_rvv.inc.c | 118 target/riscv/vector_helper.c

[PATCH v11 29/61] target/riscv: vector narrowing fixed-point clip instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 13 +++ target/riscv/insn32.decode | 6 + target/riscv/insn_trans/trans_rvv.inc.c | 8 ++ target/riscv/vector_helper.c| 141

[PATCH v11 28/61] target/riscv: vector single-width scaling shift instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 8 ++ target/riscv/vector_helper.c| 117

[PATCH v11 27/61] target/riscv: vector widening saturating scaled multiply-add

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 22 +++ target/riscv/insn32.decode | 7 + target/riscv/insn_trans/trans_rvv.inc.c | 9 ++ target/riscv/vector_helper.c| 205

[PATCH v11 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.inc.c | 4 + target/riscv/vector_helper.c| 107

[PATCH v11 25/61] target/riscv: vector single-width averaging add and subtract

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 5 ++ target/riscv/insn_trans/trans_rvv.inc.c | 7 ++ target/riscv/vector_helper.c| 100

[PATCH v11 24/61] target/riscv: vector single-width saturating add and subtract

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 10 + target/riscv/insn_trans/trans_rvv.inc.c | 16 + target/riscv/vector_helper.c| 385

[PATCH v11 23/61] target/riscv: vector integer merge and move instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_rvv.inc.c | 113 target/riscv/vector_helper.c

[PATCH v11 22/61] target/riscv: vector widening integer multiply-add instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 22 target/riscv/insn32.decode | 7 target/riscv/insn_trans/trans_rvv.inc.c | 9 + target/riscv/vector_helper.c|

[PATCH v11 21/61] target/riscv: vector single-width integer multiply-add instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 +++ target/riscv/vector_helper.c| 88

[PATCH v11 20/61] target/riscv: vector widening integer multiply instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 19 + target/riscv/insn32.decode | 6 +++ target/riscv/insn_trans/trans_rvv.inc.c | 8 target/riscv/vector_helper.c| 51

[PATCH v11 19/61] target/riscv: vector integer divide instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 target/riscv/vector_helper.c| 74

Re: [PATCH] tests/qht-bench: Adjust rate computation and comparisons

On 6/21/20 2:28 PM, Emilio G. Cota wrote: >> -if (info->r < resize_threshold) { >> +if (info->r <= resize_threshold) { >> size_t size = info->resize_down ? resize_min : resize_max; >> bool resized; > > This works, but only because info->r cannot be 0 since xorshift never

[PATCH v11 18/61] target/riscv: vector single-width integer multiply instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 33 + target/riscv/insn32.decode | 8 ++ target/riscv/insn_trans/trans_rvv.inc.c | 10 ++ target/riscv/vector_helper.c| 163

[PATCH v11 17/61] target/riscv: vector integer min/max instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 target/riscv/vector_helper.c|

[PATCH v11 16/61] target/riscv: vector integer comparison instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 57 +++ target/riscv/insn32.decode | 20 target/riscv/insn_trans/trans_rvv.inc.c | 46 + target/riscv/vector_helper.c

[PATCH v11 15/61] target/riscv: vector narrowing integer right shift instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 13 target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 90 + target/riscv/vector_helper.c

[PATCH v11 14/61] target/riscv: vector single-width bit shift instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 25 target/riscv/insn32.decode | 9 +++ target/riscv/insn_trans/trans_rvv.inc.c | 52 target/riscv/vector_helper.c

[PATCH v11 13/61] target/riscv: vector bitwise logical instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 25 target/riscv/insn32.decode | 9 + target/riscv/insn_trans/trans_rvv.inc.c | 11 ++ target/riscv/vector_helper.c

[PATCH v11 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 11 ++ target/riscv/insn_trans/trans_rvv.inc.c | 113 +++ target/riscv/vector_helper.c

[PATCH v11 11/61] target/riscv: vector widening integer add and subtract

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 49 +++ target/riscv/insn32.decode | 16 ++ target/riscv/insn_trans/trans_rvv.inc.c | 186

[PATCH v11 10/61] target/riscv: vector single-width integer add and subtract

Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 25 ++ target/riscv/insn32.decode | 10 + target/riscv/insn_trans/trans_rvv.inc.c | 291 target/riscv/vector_helper.c

[PATCH v11 09/61] target/riscv: add vector amo operations

Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Signed-off-by: LIU Zhiwei Reviewed-by: Alistair

[PATCH v11 08/61] target/riscv: add fault-only-first unit stride load

The unit-stride fault-only-fault load instructions are used to vectorize loops with data-dependent exit conditions(while loops). These instructions execute as a regular load except that they will only take a trap on element 0. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by:

[PATCH v11 07/61] target/riscv: add vector index load and store instructions

Vector indexed operations add the contents of each element of the vector offset operand specified by vs2 to the base effective address to give the effective address of each element. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson ---

[PATCH v11 06/61] target/riscv: add vector stride load and store instructions

Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from

Re: [PATCH v3 12/17] block/block-backend: convert blk io path to use int64_t parameters

On 4/30/20 6:10 AM, Vladimir Sementsov-Ogievskiy wrote: We are generally moving to int64_t for both offset and bytes parameters on all io paths. Main motivation is realization of 64-bit write_zeroes operation for fast zeroing large disk chunks, up to the whole disk. We chose signed type, to be

[PATCH v11 05/61] target/riscv: add an internals.h header

The internals.h keeps things that are not relevant to the actual architecture, only to the implementation, separate. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/internals.h | 24 1 file changed, 24

[PATCH v11 04/61] target/riscv: add vector configure instruction

vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by:

[PATCH v11 03/61] target/riscv: support vector extension csr

The v0.7.1 specification does not define vector status within mstatus. A future revision will define the privileged portion of the vector status. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 15 +

[PATCH v11 02/61] target/riscv: implementation-defined constant parameters

vlen is the vector register length in bits. elen is the max element size in bits. vext_spec is the vector specification version, default value is v0.7.1. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 7 +++

[PATCH v11 01/61] target/riscv: add vector extension field in CPURISCVState

The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Richard

Re: [PATCH 1/5] target/i386: implement special cases for fxtract

On Tue, 23 Jun 2020, Eduardo Habkost wrote: > > +if (EXPD(temp) == 0) { > > +int shift = clz64(temp.l.lower); > > +temp.l.lower <<= shift; > > Coverity reports the following. It looks like a false positive > because floatx80_is_zero() would be true if both

[PATCH v11 00/61] target/riscv: support vector extension v0.7.1

This patchset implements the vector extension for RISC-V on QEMU. You can also find the patchset and all *test cases* in my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v11). All the test cases are in the directory qemu/tests/riscv/vector/. They are riscv64 linux user mode

Re: [PATCH 1/5] target/i386: implement special cases for fxtract

On Thu, May 07, 2020 at 12:43:30AM +, Joseph Myers wrote: > The implementation of the fxtract instruction treats all nonzero > operands as normal numbers, so yielding incorrect results for invalid > formats, infinities, NaNs and subnormal and pseudo-denormal operands. > Implement appropriate

[Bug 1884831] Re: qemu-nbd fails to discard bigger chunks

Let's get nbd.ko out of the picture. The problem can be reproduced in user space (here, where I built qemu-nbd to log trace messages to stderr): $ truncate --size=3G file $ qemu-nbd -f raw file --trace=nbd_\* $ nbdsh -u nbd://localhost:10810 -c 'h.trim(3*1024*1024*1024,0)' Traceback (most recent

Re: [PATCH v10 06/61] target/riscv: add vector stride load and store instructions

On 2020/6/24 0:52, Alistair Francis wrote: On Fri, Jun 19, 2020 at 9:49 PM LIU Zhiwei wrote: Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified

[Bug 1884831] Re: qemu-nbd fails to discard bigger chunks

Hmm, carrying on further, with the nbd-client connection, I'm seeing that the kernel DID break things into two separate BLKDISCARD calls, as seen from the nbdkit side of things: # from the blkdiscard strace: ioctl(3, BLKGETSIZE64, [5368709120])= 0 ioctl(3, BLKSSZGET, [512]) = 0

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